JP2002158284A - Method for analyzing substrate noise of semiconductor integrated circuit and analyzing device therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method and device for solving the problem where the number of nodes of a model becomes very large for an extended period of simulation if correctly modeling the shapes of large numbers of minute substrate contacts in a substrate noise analysis which uses a semiconductor substrate model generated by mesh-division. SOLUTION: If a plurality of substrate contacts 105 are included in a single cell partitioned with cell border lines 202, a local voltage drop caused by a current concentration 203 near the contact is modeled using a contact equivalent resistor 204. Since a plurality of substrate contacts are allowed to be contained in a single cell, the entire chip is modeled by a rough mesh division for shorter simulation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for analyzing a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit analyzing apparatus and a board noise analyzing method for performing a circuit simulation including an influence of a parasitic element in the semiconductor integrated circuit.

[0002]

2. Description of the Related Art Since a semiconductor integrated circuit has a structure in which circuit elements and wiring are formed on a semiconductor substrate, in an analog / digital hybrid integrated circuit, noise generated from a digital circuit block causes a noise on the semiconductor substrate. Through the analog circuit block, thereby deteriorating the performance of the analog circuit. The noise transmitted through the semiconductor substrate is called "substrate noise". When designing an analog / digital hybrid integrated circuit, the influence of the substrate noise must be considered.

Reference 1 (Makoto Nagata, Atsushi Iwat
a, “Substrate Noise SimulationTechniques for A
nalog-Digital Mixed LSI Design, ”IEICE Transact
ion on Fundamentals, Vol.E82-A, No.2, pp.271-27
7, February 1999), as a cause of substrate noise, mentions the path through which the potential fluctuation of the ground supply line due to charge / discharge current at the time of digital circuit state transition enters the semiconductor substrate via the substrate contact. .

On the other hand, reference 2 (Balshaz R. Stanisi)
c, Nishath K. Verghese, Rob A. Rutenbar, L. Richard
Carleyand, David J. Allistot, "Addressing Substr
ateCoupling Mixed-Mode IC's: Simulation and Po
wer Distribution Synthesis, "IEEE Journal of
Solid-State Circuit, Vol.9, No.3, pp.226-238, Mar
ch 1994), the unit cell models 101 shown in FIG. 15 are connected three-dimensionally, and as shown in FIG.
4 shows the effectiveness of analyzing using a circuit simulator represented by “SPICE”.

The unit cell model 101 shown in FIG.
It is composed of two nodes 102 and six resistance elements 103. Here, 102 (C) is a node at the center of the block, 102 (F1) is a node on the upper surface of the block, 102 (F2) is a node on the right surface of the block, and 102 (F3). ) Is a node on the front surface, 102 (F4) is a node on the left surface, and 10 (F4)
2 (F5) is a node on the back side surface, and 102 (F6)
Is a node on the bottom surface, and 103 represents a resistance element between each node.

[0006] The resistance element 103 is essentially composed of a resistance component and a capacitance component. However, if the dielectric relaxation time determined by the resistivity and the dielectric constant of the substrate is faster than the speed of a signal handled by the circuit, the capacitance is reduced. By omitting the components, it is possible to approximate with only the resistance components.

Further, the resistance value of the resistance element 103 is calculated from the resistivity ρ of the semiconductor substrate by the following equation (1). The value also reflects that. Here, Rx, Ry, and Rz in the following equation (1) represent the resistance values of the resistance element 103 in the x, y, and z axis directions in FIG.

Rx = ρ · dx / (2 · dy · dz) Ry = ρ · dy / (2 · dx · dz) Rz = ρ · dz / (2 · dx · dy) (1)

A semiconductor substrate model 104 is created by connecting a plurality of unit cell models 101 three-dimensionally as shown in FIG.

At this time, reference numeral 105 in FIG. 16 denotes a substrate contact having a substrate resistivity different from that of the surrounding semiconductor substrate. Model as different values.

Next, when the semiconductor substrate model 104 is converted into an equivalent circuit, the resistance mesh model 10 shown in FIG.
7 is obtained.

At the position 108 corresponding to the substrate contact of the resistance mesh model 107, the digital circuit 10 is controlled so that noise from the digital circuit is applied.
9 and the parasitic resistance 110 (common impedance),
Further, the substrate noise analysis model 106 is created by connecting the analog transistor 111.

By performing a circuit simulation using the substrate noise analysis model 106, noise generated from the digital circuit at the time of switching and entering the semiconductor substrate via the substrate contact is reduced.
The effect on the operation of the analog circuit can be predicted.

On the other hand, Document 3 (Japanese Unexamined Patent Publication No. 10-261004)
Discloses a semiconductor integrated circuit analysis device that reduces the number of nodes for analyzing a substrate substrate by improving the structure of a resistance mesh. Reference 3
A substrate substrate of an integrated circuit using at least one of a resistive element, a capacitive element, and an inductive element,
The substrate is treated as an aggregate of unit solids modeled by the elements having nodes as connection points on at least the surface, and the substrate substrate is formed by using the modeled elements together with the linear elements and the non-linear elements constituting the integrated circuit. In a semiconductor integrated circuit analysis device that analyzes operation characteristics with a simulator, a unit solid is converted into data as a set of model structures in which nodes are arranged on each surface of the solid and nodes are used for connection with adjacent solids. There has been proposed a configuration in which an operation characteristic analysis process of the substrate substrate is performed by a circuit simulator using the above.

Reference 4 (Yoshitaka Murasaka, Makoto Nagata, Takashi Morie, Atsushi Iwata, "A Chip-Level Substrate Noise Analysis Method Using F-Matrix", IEICE Tech., ICD99-147, September 1999)
17, the node inside the semiconductor substrate is deleted from the model of FIG. 17 by using the multi-terminal F matrix, and a semiconductor substrate model having nodes only on the surface is created. It describes how to delete outside nodes.

[0016] However, the above-mentioned conventional technique has the following problems.

That is, in the above method, in order to faithfully model the shape of the substrate contact on the order of several μm, it is necessary to make the resistance mesh fine.
Then, the number of nodes becomes enormous, and there arises a problem that modeling of the whole chip and substrate noise simulation of the whole chip become impossible.

Japanese Patent Application No. 2000-048219 (not disclosed at the time of filing of the present application) describes a method of reducing the operation scale at the time of simulation by partially reducing a resistance mesh and using an F matrix model. However, if we try to faithfully model the structure of the huge number of circuit elements that make up the logic circuit, as a result,
The scale of the matrix operation becomes too large, making it impossible to create a model.

[0019]

SUMMARY OF THE INVENTION In the substrate noise analysis using a semiconductor substrate model created by mesh division, the present inventor has found that when the shape of an enormous number of minute substrate contacts is faithfully modeled. In order to solve the problem that the number of nodes in the model becomes enormous and the simulation becomes long, intensive research has led to the creation of a method and apparatus for making it possible to create a substrate noise analysis model with a small number of nodes. Was.

An object of the present invention is to model a behavior of an enormous number of circuit elements by using a coarse resistance mesh so that a substrate noise analysis model with a small number of nodes can be created when a semiconductor substrate model is created. To provide a method and apparatus.

Another object of the present invention is to provide a method and apparatus for shortening the simulation time and performing substrate noise simulation of the entire chip.

[0022]

SUMMARY OF THE INVENTION The present invention for solving the above problems treats a minute three-dimensional region in a semiconductor substrate as a unit solid having nodes as connection points, and the unit solid includes a resistance element, an inductive element, Modeled using at least one of the capacitance elements, the semiconductor substrate is treated as an aggregate of the unit solids, and a circuit element constituting a semiconductor integrated circuit is used together with the modeled semiconductor substrate using a circuit simulator. Analysis of operating characteristics by
In a method of analyzing a substrate noise of a semiconductor integrated circuit, a local voltage drop caused by a current concentration near a substrate contact is modeled by a resistance element, thereby modeling a substrate contact structure smaller in size than the unit solid. It becomes something.

In the present invention, the resistance value of the resistance element for modeling the voltage drop caused by the current concentration near the minute substrate contact on the surface of the semiconductor substrate is modeled by a hemispherical resistor.

According to the present invention, by combining circuit blocks designed for each functional block, the boundary of the unit solid is matched with the boundary of the circuit block when modeling an integrated circuit that has been designed as a whole. Let it be.

Further, the present invention provides a method for modeling the waveform of noise that enters the semiconductor substrate via a substrate contact due to a fluctuation in ground potential of the semiconductor integrated circuit by modeling the ground of the semiconductor integrated circuit. The entirety of the semiconductor integrated circuit chip is modeled with a small number of nodes by making it possible to express the nodes and removing unnecessary nodes.

[0026]

Embodiments of the present invention will be described. First, the principle and operation of the present invention will be described.
In the substrate noise analysis method for a semiconductor integrated circuit according to the present invention, a large number of substrate contacts are macro-modeled with one contact equivalent resistance, so that the contact potential is equivalently represented by one node.

More specifically, a method of modeling the contact equivalent resistance with a hemispherical resistor (FIG. 3); and a method of calculating the resistance value of the contact equivalent resistance using the density and distribution of the substrate contact. Means (S4 in FIG. 8) for obtaining using information.

Another feature is that a substrate noise analysis model with few nodes can be created by the macro modeling method of the present invention.

More specifically, a method (FIG. 5) for combining the above-mentioned contact equivalent resistance with a model of a semiconductor substrate modeled by a lattice-connected resistance element (FIG. 5); and a semiconductor substrate including a substrate contact. (S9 in FIG. 8).

Further, paying attention to the fact that noise that enters the semiconductor substrate via the substrate contact is caused by fluctuations in the ground potential of the integrated circuit, modeling the ground of the circuit makes it possible to reduce the number of nodes in the substrate. One of the features is to create a straight noise analysis model.

More specifically, a method of modeling the ground of the integrated circuit with a grid-connected resistance element (FIG. 12), and a method of deleting non-observable nodes included in the ground model (FIG. 13) S16).

Another feature is that the noise waveform applied to the ground model is obtained by using a power consumption analysis tool.

More specifically, a method is used in which the current consumption of a digital circuit block obtained by using a power consumption analysis tool is modeled by a current source and given to a substrate noise analysis model as a noise source (see FIG. 14). .

According to the present invention, a large number of substrate contacts are macro-modeled with one contact equivalent resistance. For this reason, when modeling a semiconductor substrate by mesh division, it is not necessary to faithfully model the shape of a minute substrate contact. As a result, the whole chip can be modeled by coarse mesh division,
It is possible to create a substrate noise analysis model with few nodes.

Further, according to the present invention, the ground of the integrated circuit is modeled by resistance elements connected in a lattice, and non-observable nodes included in the ground model are deleted.
The noise that enters the semiconductor substrate via the substrate contact is caused by a change in the ground potential of the integrated circuit, so that the above-described model can be simplified. Thus, the number of nodes included in the substrate noise analysis model can be further reduced.

Further, according to the present invention, the noise waveform applied to the ground model is preferably obtained by using a power consumption analysis tool. Ground potential fluctuations in integrated circuits are caused by pulse-like currents generated when digital circuits make state transitions.Digital circuits have a huge number of circuit elements and therefore require a long time for simulation in ordinary circuit simulations. It is expected to need.
On the other hand, the power consumption analysis tool calculates the power consumption by focusing on the number of transitions of the digital circuit, so that the simulation can be performed in a short time. An embodiment of the present invention will be described with reference to the drawings.

[First Embodiment] FIG. 1 is a diagram for explaining a semiconductor substrate model used in a substrate noise analysis method according to a first embodiment of the present invention. The semiconductor substrate is modeled by mesh division. FIG. 9 is a diagram for explaining a mesh division method when performing the mesh division.

Referring to FIG. 1, in the substrate noise analysis method according to the first embodiment of the present invention, a semiconductor substrate 201 is divided into meshes using a unit cell model 101.

In the conventional model shown in FIG. 16, in order to model a fine substrate contact, it is necessary to make the mesh division fine and make the size of the unit cell model smaller than the size of the substrate contact.

On the other hand, in the first embodiment of the present invention, the user can freely determine the fineness of the mesh division of the entire chip as long as the processing capacity and the storage capacity of the computer used for the simulation allow. I can do it. The finer the mesh division, the better the simulation accuracy is, but the longer the simulation time, so the user must take into account the performance of the computer used for the simulation so that the simulation time is within the allowable range. Determine the fineness of

When such a mesh division is performed, as shown in FIG. 1, a plurality of (many) substrate contacts 105 are included in one unit cell model 101 (S) corresponding to a portion of the semiconductor substrate surface. Will be.

In this model, the potentials of many substrate contacts included in one cell are equivalently represented by one node. This method will be described with reference to FIG. 2A and 2B are diagrams schematically showing a cross section of the semiconductor substrate in the vicinity of the substrate contact 105. In FIGS. 2A and 2B, reference numeral 202 denotes a mesh dividing line. Is represented.

FIG. 2A shows, as a comparative example of the present invention, a case where mesh division is performed by a conventional method as shown in FIG. 16, and the minimum dimension of the substrate contact 105 that can be expressed by a model is as follows. , Equal to the cell dimensions.

FIG. 2B shows that a plurality of substrate contacts 105 are provided in one cell because the mesh is divided as shown in FIG. 1 according to the first embodiment of the present invention.
Is included. In FIG. 2B, two substrate contacts 105 are included in one cell, but it is needless to say that the present invention is not limited to such a configuration.

Since the substrate contact is an entrance through which noise enters the semiconductor substrate, a current concentration 203 occurs near the substrate contact. Since the current density is inversely proportional to the square of the distance from the substrate contact, a sharp voltage drop occurs near the substrate contact.

As shown in FIG. 2A, if the modelable minimum dimension is the same as the cell dimension, the model is converted into an equivalent circuit and connected to the noise source 109, thereby A substrate noise analysis model as shown in FIG. 2 (C) is obtained. By performing a circuit simulation using this model, the effect of the voltage drop can also be predicted.

On the other hand, in the case of mesh division as shown in FIG. 2B, as shown in FIG. 2C, a noise source 109 (digital circuit serving as a noise source) is provided at a node corresponding to a substrate contact. When directly connected, the voltage drop cannot be represented by a model because the size of the cell is larger than the size of the substrate contact.

Therefore, in this embodiment, a substrate noise analysis model as shown in FIG. 2D is used to represent this voltage drop. In FIG. 2D,
A concept of a contact equivalent resistance 204 is newly introduced. This contact equivalent resistance 204 is for expressing the voltage drop.

Further, by introducing the contact equivalent resistance 204, the potential of the substrate contact becomes
Node 205 (digital circuit 109 and parasitic resistance 110
(The common impedance between the logic circuit block and the ground) and the contact point of the contact equivalent resistance 204), and the energy of the noise injected into the semiconductor substrate is reduced by the contact equivalent resistance 204. .

Therefore, the contact equivalent resistance 204 makes it possible to model the effect of voltage drop due to current concentration.

Various methods can be applied as a method for determining the magnitude of the contact equivalent resistance. Here, as an example, a method of modeling a contact equivalent resistance by a hemispherical resistance will be described.

FIG. 3 is an explanatory diagram for explaining the current concentration 203 on the substrate contact and the modeling of the voltage drop due to the current concentration.

In the example shown in FIG. 3, the substrate contact is modeled as a hemispherical conductor 301 having a radius a. Here, assuming that a voltage drop occurring near the substrate contact is Vc and a current flowing through the substrate contact is I, a contact equivalent resistance Rc of the substrate contact is expressed by the following equation (2).

Rc = Vc / I (2)

In this model, as shown in FIG. 3, the contact equivalent resistance Rc is modeled by a hemispherical resistor 302 having a radius b located around the substrate contact. The resistance value Rs of the hemispherical resistor 302 is given by the following equation (3).
It is represented by Here, ρ represents the resistivity of the semiconductor substrate.

Rs = ρ / 2π · (1 / a−1 / b) (3)

Next, FIG. 4 shows that the radius a of the substrate contact is 0.5 μm and the resistivity ρ of the semiconductor substrate is 15Ω.
cm, the hemispherical resistance 302 is calculated using the above equation (3).
Is a graph showing the result of obtaining the resistance value Rs of FIG.

Here, when the resistance value when the size of the hemispherical resistor 302 is infinitely large is defined as Ri, the value is expressed by the following equation (4). From FIG. 4, when b is approximately 5 μm, It can be seen that Rc = 0.9Ri.

That is, it can be said that 90% of the voltage drop due to the current concentration on the substrate contact occurs in the region where b <10a.

Ri is the limit value of Rs when the radius b of the hemispherical resistor 302 is infinite.

[0061] In other _{words, Ri = lim b → ∞ Rs} = ρ / 2πa = 47.8kΩ ... (4)

Therefore, in this model, the voltage drop due to current concentration on the substrate contact is b <10a
And the resistance value Rc of the contact equivalent resistance per substrate contact
Is the resistance value of the hemispherical resistor 302 of b = 10a.

The equation for calculating the resistance value is shown in the following equation (5).

Rc = ρ / 2π · (1 / a−1 / 10a) = 9ρ / (20πa) (5)

Next, a method for connecting this contact equivalent resistance to a resistance mesh representing a semiconductor substrate will be described with reference to FIG.
This will be described in detail with reference to FIG.

FIG. 5A shows that the center of the surface on the substrate front side is
A unit cell model provided with a plurality of substrate contacts 301 is shown, and reference numeral 202 denotes a cell boundary surface. Substrate contact 301 and node 303
Is calculated as follows.

First, in order to simplify the problem, FIG.
As shown in (B), the hemispherical interface 304 and the interface 30
5, the unit cell model is divided. Interface 305
Is a plane parallel to the surface of the semiconductor substrate and has a hemispherical boundary surface 30.
It is in contact with 4. With this division, the unit cell model
The area is divided into three areas: a substrate contact area 306, a cell center node area 307, and an intermediate area 308.

Then, the substrate contact 301
The resistance between node and node 303 is: substrate contact 301-hemispherical interface 30
4, the resistance between the hemispherical boundary surface 304 and the boundary surface 305, and the resistance between the boundary surface 305 and the node 303 can be considered as a combined resistance value when the resistance is connected in series.

At this time, the substrate contact 30
If the resistance between the 1-hemispherical boundary surface 304 corresponds to the contact equivalent resistance 204, the dimension r of the region 306 near the substrate contact becomes ten times the dimension of the substrate contact as described above.

The substrate contact 301-
The resistance value RC1 between the hemispherical boundary surfaces 304 is obtained by the following equation (6). Here, ρ is the resistivity of the semiconductor substrate.

RC1 = 9ρ / (20πr) (6)

Next, a method of calculating a resistance value between the boundary surface 305 and the node 303 will be described.

Resistance value R between boundary surface 305 and node 303
H1 is calculated from the following equation (7) in the same manner as the resistance value of the resistance element in FIG. 15 is obtained from the above equation (1).
Here, A is the cross-sectional area of the unit cell model.

RH1 = ρh / A (7)

Next, the hemispherical boundary surface 304-boundary surface 305
The resistance between them will be described. FIG. 6 is an enlarged view of this region, and 310 indicates the flow of current in this region.

As described above, in a region where the distance from the substrate contact is ten times the dimension of the substrate contact itself, the voltage drop becomes gentle. Accordingly, the change in the potential in the intermediate region 308 becomes gentler than that in the region 306 near the substrate contact.

Further, as shown in FIG.
At 08, the length of the path 310 through which the current flows is shorter than the area 307 near the cell center node.

Therefore, it can be said that the voltage drop in the intermediate region 308 is smaller than that in the region 306 near the substrate contact and the region 307 near the cell center node.

Therefore, the voltage drop in the intermediate region 308 is approximated by 0, and the resistance between the hemispherical boundary surface 304 and the boundary surface 305 is set to 0.

In the intermediate region 308, there is a current 310 (n) flowing into the adjacent unit cell model. If the thickness r of the intermediate region 308 is sufficiently smaller than d / 2, the size of the current 310 (n) becomes large. The current 310 flowing into this adjacent cell can be regarded as negligibly small.
(N) is approximated by 0.

As described above, by approximating the resistance value of the intermediate region 308 to 0, the substrate contact 301
The resistance value between the nodes 303 can be obtained as a combined resistance value when the resistor 204 in the region near the substrate contact and the resistor 309 in the region near the cell center node are connected in series as shown in FIG.

Here, the resistance 204 in the region near the substrate contact is equal to the contact equivalent resistance, and the resistance value is obtained from the above equation (6).

The resistance 30 in the region near the cell center node is
The resistance value of 9 is obtained from the above equation (7).

As described above, it is possible to connect the contact equivalent resistance and the resistance mesh representing the semiconductor substrate.

Next, a case where the position of the substrate contact is out of the center of the surface of the unit cell model on the substrate surface side as shown in FIG. 5D will be described.

As shown in FIG. 5D, when noise is applied from a substrate contact provided at a position deviated from the center of the surface of the unit cell model on the substrate surface side, the current intruding from the substrate contact is reduced. A model in which a part of the model flows into the adjacent unit cell model is appropriate.

However, to simplify the model,
The current flowing into the adjacent cell is omitted from the model, and the resistance between the substrate contact 301 and the node 303 is calculated in the same manner as in the model of FIG. That is,
The resistance value is the same when the substrate contact is located at the center of the surface of the unit cell model on the substrate front side and when it is located off the center.

When this approximation is performed, an analysis error may occur in the vicinity of the cell including the substrate contact, but the energy of noise injected into the cell can be correctly modeled. Noise distant from the substrate contact can be simulated correctly.

Next, a case where one cell includes many substrate contacts will be described.

FIG. 7 is a diagram for explaining a modeling method when one cell includes a large number of substrate contacts.

In general, in a semiconductor integrated circuit, it is often the case that adjacent circuit elements share a ground supply line.

Since the substrate contact is connected to the ground supply line, it can be considered that adjacent substrate contacts are conductive through the ground supply line.

Therefore, as shown in FIG. 7, the substrate contacts included in one cell are conductive, and the same noise waveform is injected into the semiconductor substrate. Shall be represented by

On the other hand, as shown in FIG. 5, when the semiconductor substrate is divided using a hemispherical boundary surface, as shown in FIG.
A region 306 (1) near the substrate contact, a region 306 (2) near the substrate contact,
The area is divided into an area 307 near the cell center node and an intermediate area 308.

Next, as described with reference to FIG. 5, when the resistance of the intermediate region 308 is approximated by 0, the connection between the node 311 and the node 303 is expressed by an equivalent circuit shown in FIG.

In the equivalent circuit of FIG.
The resistance value Re between the node and the node 303 is obtained from the following equation (8). RC1 represents a resistance value between the substrate contact 301 and the hemispherical boundary surface 304.
RH1 indicates a resistance value between the boundary surface 305 and the cell center node 303, and n indicates the number of contacts.
The resistance value Re is a combined resistance value in which n resistances of the resistance RC1 are connected in parallel and a resistance of the resistance RH1 is connected in series.

Re = RC1 / n + RH1 (8)

However, the substrate contacts included in one cell are close to each other, and the region 30 near the substrate contact of a plurality of substrate contacts is provided.
When 6 overlaps, the above equation (8) does not hold.

Region 306 near substrate contact
Overlap, the current density in the vicinity increases and the voltage drop becomes more severe. Therefore, the resistance value between the node 311 and the node 303 becomes higher than the calculation result by the above equation (8).

As described above, even when mesh division is performed such that one cell includes a large number of substrate contacts, the concept of contact equivalent resistance should be introduced if the distance between substrate contacts is large. This makes it possible to model a steep voltage drop near the substrate contact.

Further, according to this method, it is not necessary to faithfully model all the shapes of an enormous number of substrate contacts existing on a semiconductor integrated circuit, and the mesh division can be made coarse.

Therefore, a simulation result can be obtained within a practical processing time. Reference 4 (Yoshitaka Murasaka, Makoto Nagata, Takashi Morie, Atsushi Iwata, "A Chip-Level Substrate Noise Analysis Method Using F-Matrix", IEICE Tech.
-147, September 1999), a node located inside a semiconductor substrate can be deleted by multi-terminal F matrix operation. It is also possible to perform a simulation in a short time.

The analyzing apparatus according to the present invention comprises a data processing apparatus having a storage device, an output device, an input device, an arithmetic device, and the like, and is a unit having a node with a minute three-dimensional region in a semiconductor substrate as a connection point. Treated as a solid, a unit solid (cell) is modeled using at least one of a resistive element, an inductive element, and a capacitive element, and the semiconductor substrate is treated as an aggregate of the unit solid to constitute a semiconductor integrated circuit. A circuit device to be analyzed, together with the modeled semiconductor substrate, is analyzed by a simulation means. An analysis device for analyzing operation characteristics inputs layout information of the semiconductor integrated circuit from a storage device, and a substrate directly connected to the semiconductor substrate. Means for extracting a contact (S2 in FIG. 8), the resistivity of the semiconductor substrate, the density of the substrate contact, Fabric, based on said semiconductor meshing information of the substrate, means for calculating the contact equivalent resistance that models the local voltage drop caused by current concentration in the vicinity the substrate contact (S4 in FIG. 8)
Means for creating a semiconductor substrate model in which the contact equivalent resistance of each cell and the resistance mesh of the cell are combined and outputting the model to a storage device or an output device (S9 in FIG. 8). A simulation for examining the influence of noise is performed.

[Embodiment 1] Next, a first embodiment of the present invention will be described in detail with reference to the drawings. In the first embodiment of the present invention, a large number of fine substrate contacts are macro-modeled in one cell to model the entire semiconductor integrated circuit by coarse mesh division and simulate substrate noise. ing. In the first embodiment of the present invention, a method for automatically creating a model as described above using information on layout data of a semiconductor integrated circuit will be described.

FIG. 8 is a diagram for explaining the flow of processing according to the first embodiment of the present invention.

In step S2, information S3 of the distribution and density of the substrate contacts is obtained from the layout information S1. The layout information S1 is read out from the storage device.

The cross-sectional structure of a semiconductor integrated circuit is schematically shown in FIG. 9 in general. The contact 401 is:
(S)), and when it is connected to the N-well 403 (401
(N)) a polysilicon wiring 40 formed on the substrate 402
4 (401 (P)).

In this embodiment, only the contact 401 (S) directly connected to the semiconductor substrate is assumed as a noise source.

Therefore, here, only the information of the contact 401 (S) directly connected to the semiconductor substrate is extracted from the layout data of the semiconductor integrated circuit, and the contact equivalent resistance is obtained from the distribution and density.

In the layout data of a semiconductor integrated circuit, the shapes of wells, wirings, contacts, vias, etc. are recorded in separate layers. For this reason, in step S2 in FIG. 8, by performing a logical operation on the graphic between the layers of the layout data, it is possible to extract information on the distribution of only the substrate contact 401 (S) directly connected to the semiconductor substrate. it can.

Next, from the information S3 of the distribution and density of the substrate contact, the contact equivalent resistance S
5 is calculated (step S4).

Since the contact equivalent resistance is obtained for each cell, mesh division information S6 is required here.

At this time, in the present embodiment, in order to macro-model a large number of substrate contacts using the contact equivalent resistance, coarse division as described in the first embodiment is sufficient for mesh division. And 1
A cell may include multiple substrate contacts.

The method of obtaining the contact equivalent resistance S5 from the distribution and density of the substrate contacts has been described in the first embodiment.
7 information is required.

The contact equivalent resistance S5 obtained as described above is added to a resistance mesh S8 as shown in FIG.
Are combined by the method described in the first embodiment (step S9), and a semiconductor substrate model S10 is created.

The semiconductor substrate model S10 can simulate the influence of substrate noise by connecting a noise source and an analog circuit as shown in FIG.

In this model, since a large number of substrate contacts are macro-modeled using contact equivalent resistances, a semiconductor substrate can be modeled by coarse mesh division. Therefore, a semiconductor substrate model with few nodes can be created, and the analysis time can be reduced.

[Second Embodiment] Next, a second embodiment of the present invention will be described.
An embodiment will be described. FIG. 10 is a diagram illustrating a second embodiment of the present invention.

In recent years, in the design of integrated circuits, a hierarchical circuit design technique for designing a larger circuit by combining circuit blocks designed in units of functional blocks has become mainstream.

FIG. 10A shows circuit blocks 502 (A), 502 (B), 502 (C) and 50 which are separately designed.
2 (D) shows an integrated circuit whose overall design is made. At this time, the ground is often shared in one circuit block 502.

Since the substrate contact is connected to the ground supply line, one circuit block 50
It can be said that the substrate contact included in No. 2 injects noise having the same waveform into the semiconductor substrate. Conversely, the ground is often not shared between different circuit blocks.

When a semiconductor substrate model of this chip is created, if the mesh is divided using the boundary line shown by 503 (1) in FIG. The cell will include the substrate contacts of multiple circuit blocks.

For example, in FIG.
4 is a circuit block 502 (C) and a circuit block 502
(D) substrate contact is included. At this time, since the ground supply lines of different circuit blocks are not conducting, the cell 504 contains the circuit block 502
Noise having different waveforms is injected from the respective substrate contacts of (C) and the circuit block 502 (D).

In the first embodiment, when one cell includes a large number of substrate contacts, the substrate contacts are electrically connected to each other via a ground supply line, and the same noise waveform is applied to the semiconductor substrate. Was assumed to be injected.

However, when the cell crosses the boundary of the circuit block 502 as in the cell 504 in FIG. 10, one cell includes a substrate contact that generates noise having a different waveform.

Therefore, the mesh division as shown in FIG. 10A cannot be modeled by the method described in the first embodiment.

Therefore, in the second embodiment of the present invention,
The mesh dividing line when dividing the semiconductor substrate into meshes,
The above problem is solved by matching the boundary of the circuit block.

FIG. 10B shows a mesh dividing line 503.
(2) so that the boundary of the circuit block 502 coincides with
It is a figure showing the example which performed mesh division of a semiconductor substrate.

At this time, for a portion where the potential distribution may be complicated, such as near a corner of a circuit block, the analysis accuracy is improved by making the mesh division finer.

[Third Embodiment] Next, a third embodiment of the present invention will be described.
The embodiment will be described in detail with reference to the drawings. FIG. 11A shows an integrated circuit whose overall design is made by combining circuit blocks designed in units of functional blocks as described in the second embodiment of the present invention.

Circuit blocks 502 (E) and 502
The ground of (F) is a ground supply line 50
7, the connection is made to the input / output pad 508, and from here to the terminal of the integrated circuit using a bonding wire or the like.

Now, the integrated circuit of FIG.
As shown in (B), when the mesh is divided, nine cells are included in the circuit block 502 (E).
02 (F) includes six cells.

The circuit block includes many substrate contacts, and these substrate contacts are paths through which noise enters the semiconductor substrate. Need to inject noise into the cell.

That is, for each cell corresponding to a circuit block, the contact equivalent resistance 20 shown in FIG.
4. It is necessary to connect the noise source 109 and the parasitic resistance 110.

For this reason, the number of nodes increases during circuit simulation, and the simulation time becomes longer.

On the other hand, the above reference 4 (Yoshitaka Murasaka, Nagata
Shin, Takashi Morie, Atsushi Iwata, "Chip-Level Substrate Noise Analysis Method Using F-Matrix" IEICE Technical Report ICD99-147, September 1999). It can be deleted by F matrix operation.

Therefore, if the ground supply line in the circuit block is modeled and noise is applied only from one node of the model, the other nodes can eliminate the flow of current from outside the chip. The number of nodes can be reduced by the method using the multi-terminal F matrix.

According to the third embodiment of the present invention, as described above, the ground supply line of the circuit block is modeled, and noise is given only from one node of the model, thereby eliminating the number of other nodes. By creating a semiconductor substrate model with a small number of nodes, simulation can be performed in a short time.

Next, a method of modeling a ground supply line in a circuit block will be described with reference to FIG.

FIG. 12 is a view for explaining a semiconductor substrate model used in the third embodiment of the present invention. In FIG. 12, reference numeral 509 denotes a mesh-divided semiconductor substrate, and reference numeral 204 denotes a contact equivalent resistance.

As described in the second embodiment,
The ground supply line is often shared in the circuit block. On the other hand, the substrate contact is connected to the ground supply line, and when the ground potential fluctuates, it becomes noise and penetrates the semiconductor substrate via the substrate contact.

Therefore, the modeling of the ground supply line is as follows.
As shown in FIG. 12, the upper node 511 of the equivalent contact resistance 204 can be modeled by being connected in a grid by a resistance element 512 corresponding to a ground power supply wiring. Note that the contact equivalent resistance 20 in this model
4 and the wiring resistance 512 correspond to the unit cell model 10 in FIG.
1 can be expressed. Therefore, the contact equivalent resistance 20
1 and the entire semiconductor substrate including the wiring resistance 512 are shown in FIG.
7 can be represented by a resistance mesh model such as 107.

In the resistance mesh model, nodes from which current does not flow in / out can be deleted. FIG.
In the model of, nodes other than the node 513 into which the noise is injected can be deleted from the model because no current flows in and out. A method for removing unnecessary nodes is described in the above-mentioned reference 4 (Yoshitaka Murasaka, Makoto Nagata, Takashi Morie, Atsushi Iwata, "A Chip-Level Substrate Noise Analysis Method Using F-Matrix", IEICE Tech. September) Multi-terminal F
In addition to the method using a matrix, a method based on a matrix operation described in JP-A-10-261004 may be used.

Also, in the model shown in FIG.
13 is the observation point, and noise is applied from here.
The node 513 for injecting noise in this way is connected to the point 5 where the ground supply wiring 507 shown in FIG.
The closer to 10, the closer the characteristics of the model are to the real one,
More desirable.

Example 2 In the third embodiment,
The method has been described in which the ground power supply line of the semiconductor integrated circuit is modeled and noise is applied from one point of the ground power supply line model to reduce the number of nodes from the semiconductor substrate model. In a second embodiment of the present invention, a method for automatically creating the above model using the information of the layout data of the semiconductor integrated circuit and the boundary information of the circuit block will be described. FIG. 13 is a diagram illustrating the flow of processing according to the second embodiment of this invention. 13, the same processes as those in FIG. 8 are denoted by the same reference numerals. Hereinafter, steps added to FIG. 8 will be described.

First, paying attention to the fact that the ground power supply system is shared in one circuit block in the semiconductor integrated circuit, the circuit shown in FIG.
The ground feeder is modeled by a network such as 512 of step 2 (step S14). At this time, the calculation of the wiring resistance (step S12) includes the wiring resistivity S13.
And mesh division information S6 are required.

Next, the ground feed line model S14 created as described above is connected to the contact equivalent resistance S5 and the resistance mesh S8 described in the first embodiment (step S9), and a semiconductor substrate model S10 is created. I do. At this time, the ground feeder model S14 is the third feeder model of the present invention.
As described in the embodiment, only one node can be set as an observation point and other nodes can be deleted from the model.

Then, unnecessary nodes are deleted using information S15 indicating which node is set as the observation point (step S16). A method for removing unnecessary nodes is described in the above-mentioned reference 4 (Yoshitaka Murasaka, Makoto Nagata, Takashi Morie, Atsushi Iwata, "A Chip-Level Substrate Noise Analysis Method Using F-Matrix", IEICE Tech. September) Multi-terminal F
A method using a matrix and a method using a matrix operation described in JP-A-10-261004 are used.

According to the above procedure, a semiconductor substrate model S17 having fewer nodes than the semiconductor substrate model S10 of FIG. 8 can be created. Semiconductor substrate model S1
7 can simulate the effect of substrate noise by connecting a digital circuit or an analog circuit as a noise source, as shown in FIG. Can be obtained at

As described in the second embodiment of the present invention, when the semiconductor substrate is divided into meshes (step S18), the mesh division is performed using the circuit block boundary information S11 used in this embodiment. The lines may be aligned with the boundaries of the circuit blocks.

In addition, the noise waveform generated by the digital circuit is calculated in advance by another method, and the result of the simulation is applied to the node 513 as noise in a circuit simulation, so that the analysis time is reduced. You may.

The analysis apparatus according to the present invention calculates the wiring resistance of the ground power supply line of the circuit block by using the boundary information of the circuit block of the semiconductor integrated circuit and the wiring resistivity and the mesh division information. Means for creating a ground feed line model (S13 and S14 in FIG. 13), and means for connecting the created ground feed line model with the contact equivalent resistance and resistance mesh to create a semiconductor substrate model (FIG. 13 S9), the observable node information indicating which node is to be the observation point is input from the input device, and unnecessary nodes are deleted from the semiconductor substrate model. Means (S16) for creating and outputting to a storage device or an output device.

FIG. 14 shows an example in which noise generated from a digital circuit is modeled by a current source 602. In FIG. 14, reference numeral 601 denotes a semiconductor substrate model, 110 denotes a common impedance between the logic circuit block and the ground, and 111 denotes an analog transistor. Since the number of elements in a digital circuit is enormous, there is a possibility that the calculation scale will be enormous in a normal circuit simulation. For example, by using a power consumption analysis tool proposed in Since the current consumption is predicted based on the number of state transitions of the circuit, the simulation can be completed in a short time.

[0154]

As described above, according to the present invention, the following effects can be obtained.

A first effect of the present invention is that a substrate noise analysis model with a small number of nodes can be created.

The reason is that in the present invention, when modeling a semiconductor substrate by mesh division, it is not necessary to faithfully model the shape of minute substrate contacts. Because it can be modeled. Further, in the present invention, by modeling the ground of the integrated circuit with the resistive elements connected in a grid pattern, non-observable nodes included in the ground model can be deleted.

A second effect of the present invention is that the simulation can be performed in a short time.

The reason is that, in the present invention, a semiconductor substrate model having few nodes is used for the substrate noise simulation. Also, in the present invention, the noise waveform generated from the digital circuit is obtained by using a power consumption analysis tool. Since the number of elements in a digital circuit is enormous, a long time may be required for the simulation when calculating the noise waveform by circuit simulation.However, the power consumption analysis tool focuses on the number of transitions of the digital circuit and the power consumption , The simulation can be performed in a short time.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a modeling method according to a first embodiment of the present invention, and is a diagram illustrating a mesh division method when a semiconductor substrate is modeled by mesh division.

FIG. 2 is a diagram illustrating a contact equivalent resistance in the modeling method according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating a method for calculating a contact equivalent resistance value in the modeling method according to the first embodiment of the present invention.

FIG. 4 is a graph showing a calculation result of a resistance value according to the model of FIG. 3;

5 is a diagram illustrating a method of connecting a contact equivalent resistance calculated by the model of FIG. 3 and a resistance mesh representing a semiconductor substrate.

6 is a diagram showing a current flow in a region 308 of FIG.

FIG. 7 is a diagram illustrating a method of calculating a contact equivalent resistance value when one cell includes a large number of substrate contacts in the modeling method according to the first embodiment of the present invention.

FIG. 8 is a flowchart illustrating the operation of the first exemplary embodiment of the present invention.

FIG. 9 is a diagram illustrating a structure of a substrate contact in a semiconductor integrated circuit.

FIG. 10 is a diagram illustrating a modeling method according to a second embodiment of the present invention, and is a diagram illustrating a mesh division method when a semiconductor substrate is modeled by mesh division.

FIG. 11 is a diagram illustrating a modeling method according to a third embodiment of the present invention, and is a diagram illustrating a method of modeling an integrated circuit whose entire design has been performed by combining circuit blocks.

FIG. 12 is a diagram illustrating a modeling method according to a third embodiment of the present invention, and is a diagram illustrating a method of reducing the number of nodes from a model by modeling a ground power supply line of an integrated circuit.

FIG. 13 is a flowchart illustrating the operation of the second exemplary embodiment of the present invention.

FIG. 14 is a diagram showing an example in which noise generated from a digital circuit is modeled by a current source in the second embodiment of the present invention.

FIG. 15 is a diagram illustrating a conventionally proposed unit cell model.

FIG. 16 is a diagram illustrating a conventionally proposed method of modeling a semiconductor substrate.

FIG. 17 is a diagram illustrating a conventionally proposed substrate noise analysis model.

[Explanation of symbols]

Reference Signs List 101 unit cell model 102 node 103 resistance element 104 semiconductor substrate model expressed by unit cell 105 substrate contact 106 substrate noise analysis model 107 resistance mesh 108 node corresponding to substrate contact 109 digital circuit 110 parasitic resistance (common impedance) 111 Analog transistor 201 A semiconductor substrate model represented by a unit cell.
Model including many substrate contacts in cell 202 Mesh dividing line 203 Current concentration near substrate contact 204 Contact equivalent resistance 205 Node representing substrate contact potential 301 Hemispherical conductor modeling substrate contact 302 Hemispherical resistance Body 303 Cell center node 304 Hemispherical boundary surface 305 Boundary surface 306 Substrate contact vicinity region 307 Cell center vicinity 308 Intermediate region 309 Resistance between boundary surface 305 and node 303 310 Current flow in intermediate region 308 Contact 402 Semiconductor Substrate 403 N-well 404 Polysilicon wiring 405 Conductor wiring 406 Insulating film 502 Circuit block 503 Mesh dividing line 504 Overlap with circuit block boundary Cell 506 Integrated circuit in which the entire circuit is designed by combining circuit blocks 507 Ground supply wiring 508 I / O pad 509 Semiconductor substrate 510 represented by unit cell model 510 Points to which ground supply wiring is connected in circuit block 511 Contact equivalent Upper node of resistor 512 Wiring resistance of ground supply line of integrated circuit 513 Observation node 601 Semiconductor substrate 602 expressed by unit cell model Digital circuit (noise source) modeled by current source

Claims (24)

[Claims] 1. A small three-dimensional region in a semiconductor substrate is treated as a unit solid having nodes as connection points, and the unit solid is modeled using at least one of a resistance element, an inductive element, and a capacitance element. Treating the semiconductor substrate as an aggregate of the unit solid and performing an operation characteristic analysis on a circuit element constituting the semiconductor integrated circuit together with the modeled semiconductor substrate using a circuit simulator; In the analysis method, a local voltage drop caused by current concentration near the substrate contact is modeled by a resistance element, thereby modeling a substrate contact structure smaller in size than the unit solid. Substrate noise analysis method for a semiconductor integrated circuit. 2. The method according to claim 1, wherein a resistance value of a resistance element for modeling a voltage drop caused by a current concentration near a minute substrate contact on the surface of the semiconductor substrate is modeled by a hemispherical resistor. 2. The method for analyzing substrate noise of a semiconductor integrated circuit according to claim 1, wherein 3. When one unit solid includes a plurality of substrate contacts, a combined resistance value in which the number of the resistive elements equal to the number of substrate contacts included in the unit solid is connected in parallel is used. 2. The method according to claim 1, further comprising modeling a local voltage drop in the vicinity of the substrate contact when the unit solid includes a plurality of substrate contacts. 4. The semiconductor integrated circuit chip as a whole can be modeled with a small number of nodes by modeling a large number of minute substrate contacts on the surface of the semiconductor substrate with a small number of unit solids. 2. The method for analyzing substrate noise of a semiconductor integrated circuit according to claim 1, wherein 5. A small three-dimensional region in a semiconductor substrate is treated as a unit solid having a node as a connection point, and the unit solid is modeled using at least one of a resistance element, an inductive element, and a capacitance element. And treating the semiconductor substrate as an aggregate of the unit solids, and analyzing a circuit element constituting the semiconductor integrated circuit together with the modeled semiconductor substrate in an operation characteristic by a circuit simulator. By combining circuit blocks designed for each functional block, the boundary of the unit solid is matched with the boundary of the circuit block when modeling an integrated circuit that has been designed as a whole. A substrate noise analysis method for a semiconductor integrated circuit. 6. A small three-dimensional region in a semiconductor substrate is treated as a unit solid having a node as a connection point, and the unit solid is modeled using at least one of a resistance element, an inductive element, and a capacitance element. A semiconductor integrated circuit substrate noise analysis method in which the semiconductor substrate is treated as an aggregate of the unit solid body, and the circuit elements constituting the semiconductor integrated circuit are subjected to operation characteristic analysis with a circuit simulator together with the modeled semiconductor substrate. By modeling the ground of the semiconductor integrated circuit, the waveform of the noise that enters the semiconductor substrate via the substrate contact due to the fluctuation of the ground potential of the semiconductor integrated circuit can be expressed by one node. To model the entire semiconductor integrated circuit chip with a small number of nodes A method for analyzing a substrate noise of a semiconductor integrated circuit. 7. The noise waveform applied to the ground model is obtained by power consumption analysis means for obtaining power consumption by paying attention to the number of state transitions of a digital circuit, instead of a circuit simulator. A method for analyzing substrate noise of a semiconductor integrated circuit as described in the above. 8. A local voltage drop generated by current concentration near a substrate contact is modeled by a resistance element (referred to as “contact equivalent resistance”), and a plurality of substrates in a unit solid body (referred to as a “cell”) are modeled. 2. The method according to claim 1, wherein the potential of the contact is equivalently represented by one node potential. 9. The potential of said substrate contact is:
Circuit simulation for a substrate contact structure represented by a potential at a common connection point of the contact equivalent resistance corresponding to the substrate contact and a common impedance between a logic circuit formed on the semiconductor substrate and the logic circuit and ground. 9. The method for analyzing substrate noise of a semiconductor integrated circuit according to claim 8, wherein: 10. A model in which a resistance value of the contact equivalent resistance is modeled by a hemispherical resistor, and in connecting the contact equivalent resistance to a resistance mesh of a cell representing the semiconductor substrate, a hemispherical boundary of the hemispherical resistor. A single cell is divided into a plurality of regions by using a boundary surface formed of a plane and a plane parallel to the semiconductor substrate surface and in contact with the hemispherical boundary surface, and a resistance between the substrate contact and a cell center node is determined. 9. The substrate noise analysis method for a semiconductor integrated circuit according to claim 8, wherein the value is a combined resistance value of a resistance for each region between the substrate contact and the node. 11. The cell is divided into a region near each substrate contact, a region near a cell center node, and an intermediate region between the region near the substrate contact and the region near the cell center node. The method for analyzing substrate noise of a semiconductor integrated circuit according to claim 10. 12. A resistance value between the substrate contact and the cell center node is reduced by approximating a resistance value of the intermediate region to zero. 12. The method for analyzing substrate noise of a semiconductor integrated circuit according to claim 11, wherein said method is obtained as a combined resistance value of said resistances. 13. A plurality of substrate contacts included in one cell are electrically connected to each other via a ground supply line, and a resistance value of a contact equivalent resistance corresponding to each of the substrate contacts is determined by a hemispherical resistor. Modeling, the plurality of contact equivalent resistances, and a noise waveform that generates a noise at a common connection point potential between a logic circuit formed on the semiconductor substrate and a common impedance between the logic circuit and the ground, Using a hemispherical boundary surface of a hemispherical resistor having a contact equivalent resistance corresponding to each of the plurality of substrate contacts, a plurality of substrate contact vicinity regions, a cell center node vicinity region, and Between multiple substrate contact area and cell center node area The resistance in the intermediate area is approximated by 0, and the resistance between the noise source and the cell center node is calculated as the resistance between the substrate contact and the hemispherical boundary surface for each substrate contact. 12. The substrate noise analysis method for a semiconductor integrated circuit according to claim 11, wherein a parallel connection and a resistance value between the hemispherical boundary surface and the cell center node are represented by a combined resistance value. 14. A first step of inputting layout information of a semiconductor integrated circuit and extracting information of a substrate contact directly connected to a semiconductor substrate; information of distribution and density of the substrate contact; A second step of obtaining a contact equivalent resistance that models a local voltage drop caused by current concentration near a substrate contact from the resistivity of the semiconductor substrate and the mesh division information of the semiconductor substrate; and A third step of creating a semiconductor substrate model by combining a resistance mesh of a cell with an equivalent resistance, wherein a plurality of substrate contacts are included in one cell when one cell includes a plurality of substrate contacts in the mesh division. The potential of the straight contact is equivalently represented by one node potential, A substrate noise analysis method for a semiconductor integrated circuit, wherein a simulation for substrate noise analysis is performed on the created semiconductor substrate model. 15. The method according to claim 1, wherein in the third step,
A method of connecting the contact equivalent resistance described in any one of 0 to 13 to a resistance mesh representing the semiconductor substrate, wherein a cell resistance mesh is coupled to the contact equivalent resistance of each cell. Claim 14
A method for analyzing substrate noise of a semiconductor integrated circuit as described in the above. 16. A wiring resistance of a ground power supply line of a circuit block is calculated by using boundary information of a circuit block of the semiconductor integrated circuit, a wiring resistivity, and mesh division information, and the ground power supply line is gridded. To create a ground feed line model modeled by resistive elements connected in a 4th form
And a fifth step of connecting the created ground feed line model to the contact equivalent resistance and the resistance mesh to create a semiconductor substrate model. Or a substrate noise analysis method for a semiconductor integrated circuit according to 15. 17. The ground feeder model, wherein only one node is used as an observation point and other nodes can be deleted from the model, and observable node information indicating which node is used as an observation point. 17. A semiconductor integrated circuit according to claim 16, further comprising the step of: removing unnecessary nodes from the created semiconductor substrate model by using the above-mentioned method to create a semiconductor substrate model having a small number of nodes. Substrate noise analysis method. 18. The semiconductor device according to claim 16, wherein when dividing the semiconductor substrate into meshes, mesh division lines are made to coincide with the boundaries of the circuit blocks using boundary information of the circuit blocks. A substrate noise analysis method for a semiconductor integrated circuit. 19. A unit solid (referred to as a "cell") having a node with a minute three-dimensional region in a semiconductor substrate as a connection point, wherein the unit solid is at least one of a resistive element, an inductive element, and a capacitive element. Modeled using elements, treat the semiconductor substrate as an aggregate of the unit solid, and perform operation characteristic analysis on the circuit elements constituting the semiconductor integrated circuit, together with the modeled semiconductor substrate, by simulation means. In a semiconductor integrated circuit analyzer, means for inputting layout information of a semiconductor integrated circuit from a storage device and extracting a substrate contact directly connected to the semiconductor substrate; and a resistivity of the semiconductor substrate, a density of the substrate contact, Based on the distribution and mesh division information for dividing the semiconductor substrate, A means for calculating a contact equivalent resistance that models a local voltage drop generated by current concentration in the vicinity of the cell, and a semiconductor substrate model in which the contact equivalent resistance and the resistance mesh of the cell are combined to create a storage device or an output device. A semiconductor integrated circuit analyzing apparatus, comprising: an output unit; and a unit configured to execute a simulation for performing a substrate noise analysis on the created semiconductor substrate model. 20. A common connection between the potential of the substrate contact, the contact equivalent resistance corresponding to the substrate contact, and a logic circuit formed on the semiconductor substrate and a common impedance between the logic circuit and ground. 20. The semiconductor integrated circuit analyzer according to claim 19, wherein the potential is represented by a point potential, and the potentials of the plurality of substrate contacts are equivalently represented by one node potential. 21. Modeling the resistance value of the contact equivalent resistance with a hemispherical resistor, and connecting the contact equivalent resistance with a resistance mesh of a cell, the hemispherical boundary surface of the hemispherical resistor, and the semiconductor substrate. Means for dividing one cell into a plurality of regions by using a boundary surface formed of a plane parallel to the surface and abutting on the hemispherical boundary surface; and 20. A semiconductor according to claim 19, further comprising: means for generating a semiconductor substrate model in which the equivalent resistance of the contact and a resistance mesh are combined as a combined resistance value of the resistance of each region between a contact and the node. Integrated circuit analyzer. 22. A wiring resistance of a ground power supply line of a circuit block is calculated using boundary information of a circuit block of the semiconductor integrated circuit, a wiring resistivity, and mesh division information, and the ground power supply line is divided into a grid. Means for creating a ground feed line model modeled by resistive elements connected in a shape, and connecting the created ground feed line model to the contact equivalent resistance and resistance mesh to create a semiconductor substrate model 20. The semiconductor integrated analysis device according to claim 19, comprising: 23. The ground feed line model, wherein only one node is used as an observation point and other nodes can be deleted from the model, and observable node information indicating which node is used as an observation point. 23. The apparatus according to claim 22, further comprising: means for inputting a command, deleting unnecessary nodes from the semiconductor substrate model, creating a semiconductor substrate model with a small number of nodes, and outputting the model to a storage device or an output device. Semiconductor integrated analysis device. 24. Using the boundary information of the circuit block,
23. The semiconductor integrated circuit analysis device according to claim 22, further comprising means for matching a mesh dividing line of the semiconductor substrate with a boundary of the circuit block.