JP2004234618A - Semiconductor device model, and forming method and device thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To precisely perform an analysis of power source noise in a formation method of a semiconductor device model to be used for analysis of behavior of power source noise in a semiconductor device. <P>SOLUTION: The semiconductor device that is an object of power source noise analysis is divided to power source wiring, internal capacity, internal current consumption, and input/output cells, models (sub-models) of the power source wiring, internal capacity, internal current consumption and input/output cells are formed, and the models (sub-models) of the power source wiring, internal capacity, internal current consumption and input/output cells are connected, whereby the semiconductor device model for power source noise analysis for the semiconductor device as the object of power source noise analysis is formed. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device model (LSI model for power supply noise analysis) used when analyzing the behavior of power supply noise of a semiconductor device, and a method and apparatus for creating the same.
[0002]
[Prior art]
2. Description of the Related Art In recent years, with the development of fine processing technology for semiconductor devices, semiconductor devices have been increased in scale and speed, and the power supply voltage has been reduced. In addition, as the size of the semiconductor device increases, the functions that can be mounted on the semiconductor device increase, and the number of input / output cells required for communication with the outside tends to increase.
[0003]
Under such circumstances, the influence of power supply noise caused by inductance inside the semiconductor device and the influence of power supply noise caused by simultaneous switching of input / output cells and logic gates cannot be ignored. As a result, if a recent semiconductor device is designed without properly analyzing the influence of power supply noise, unexpected rework is forced.
[0004]
However, in the conventional power supply noise analysis method, a simple model in which the input / output cells and the packages connected to the input / output cells, the internal load, and the external load are represented by lumped constants is often used. Even when the power supply wiring network inside the semiconductor device is expressed as a distributed constant, the power supply wiring network is often expressed as an RC model of resistance and capacitance. Further, it is often the case that noise due to simultaneous switching of input / output cells and noise due to simultaneous switching of logic gates are separately modeled and analyzed separately.
[0005]
[Patent Document 1] JP-A-2001-222573
[0006]
[Problems to be solved by the invention]
As described above, in the conventional power supply noise analysis method, since a simple semiconductor device model is used, it is difficult to model a semiconductor device having a variety of wiring structures. It is possible to accurately model a semiconductor device in which power supply wiring is not uniform, such as a semiconductor device including a macro having a different operating voltage or a semiconductor device in which an internal ground line is intentionally divided. Therefore, there is a problem that power supply noise cannot be analyzed with high accuracy.
[0007]
In addition, problems such as the inability to properly handle input / output cells in which signals propagate in both directions and the load outside the semiconductor device are represented by lumped constant system resistance and capacitance, so that input / output cells can be determined Problems such as difficulty in adjusting the resistance and planning the wiring on the board, the interaction between power supply noise caused by switching of input / output cells and power supply noise caused by switching of logic gates, There is also a problem that the operation of the input / output cell under the power supply noise condition cannot be accurately analyzed.
[0008]
In view of the foregoing, an object of the present invention is to provide a semiconductor device model capable of analyzing power supply noise of a semiconductor device to be analyzed for power supply noise with high accuracy, and a method and apparatus for creating the same.
[0009]
[Means for Solving the Problems]
The method and apparatus for creating a semiconductor device model according to the present invention creates a model of a power supply wiring, an internal capacitance, an internal current consumption, and an input / output cell of a semiconductor device to be analyzed for power supply noise. The input / output cell models are combined to create a power supply noise analysis semiconductor device model for the power supply noise analysis target semiconductor device.
[0010]
The semiconductor device model of the present invention is configured by combining a power supply wiring, an internal capacitance, an internal current consumption, and an input / output cell model of the semiconductor device.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of a semiconductor device model, a method for producing the same, and a device according to the present invention will be described with reference to FIGS.
[0012]
FIG. 1 is a configuration diagram of an embodiment of a semiconductor device model creation device of the present invention. One embodiment of the semiconductor device model creating apparatus of the present invention divides a semiconductor device to be analyzed for power supply noise into a power supply wiring, an internal capacitance, an internal current consumption, and an input / output cell. Create a model of the output cell, combine these power supply wiring, internal capacitance, internal current consumption, and the model of the input / output cell, and create a power supply noise analysis semiconductor device model for the power supply noise analysis target semiconductor device. It is.
[0013]
In FIG. 1, reference numeral 1 denotes a semiconductor device model creation information storage unit that stores information necessary for creating a semiconductor device model for power supply noise analysis, and 2 denotes a semiconductor device model stored in the semiconductor device model creation information storage unit 1. A semiconductor device model creation unit for inputting model creation information to create a power supply noise analysis semiconductor device model, and a semiconductor device model for storing a power supply noise analysis semiconductor device model created by the semiconductor device model creation unit 2. It is a storage unit.
[0014]
In the semiconductor device model creation information storage 1, a semiconductor device layout information storage means 4 stores layout information of a power supply noise analysis target semiconductor device, and a semiconductor device 5 stores operation conditions of the power supply noise analysis target semiconductor device. Operating condition storage means, 6 is a semiconductor device load condition storage means for storing load conditions of a power supply noise analysis target semiconductor device, and 7 is a semiconductor device circuit description for storing circuit descriptions of input / output cells of the power supply noise analysis target semiconductor device. Storage means.
[0015]
In the semiconductor device model creation unit 2, a power supply wiring submodel creation unit 8 creates a power supply wiring model (hereinafter, referred to as a power supply wiring submodel) that can be analyzed by a circuit simulator from layout information of a semiconductor device to be analyzed for power supply noise. Reference numerals 9 and 9 denote an internal capacitance sub-model generating means for generating an internal capacitance model (hereinafter referred to as an internal capacitance sub-model) that can be analyzed by a circuit simulator from the layout information of the semiconductor device to be analyzed for power supply noise.
[0016]
Reference numeral 10 denotes an internal current consumption submodel creating unit that creates an internal current consumption model (hereinafter, referred to as an internal current consumption submodel) that can be analyzed by a circuit simulator from layout information and operating conditions of a semiconductor device to be analyzed for power supply noise. Is used to create an input / output cell model (hereinafter referred to as an input / output submodel) that can be analyzed by a circuit simulator from the layout information, operating conditions, load conditions, and circuit description of the input / output cells of the semiconductor device to be analyzed for power supply noise. Output submodel creation means.
[0017]
Reference numeral 12 denotes a power supply wiring submodel created by the power supply wiring submodel creation means 8, an internal capacitance submodel created by the internal capacitance submodel creation means 9, and an internal current consumption submodel created by the internal consumption current submodel creation means 10. And the input / output submodels created by the input / output submodel creation means 11 to create a power supply noise analysis semiconductor device model that can be analyzed by a circuit simulator for a power supply noise analysis target semiconductor device. Means.
[0018]
FIG. 2 is a configuration diagram of the power supply wiring sub-model creating means 8. In FIG. 2, reference numeral 13 denotes a power supply line dividing means for extracting a power supply line from layout information of a semiconductor device to be subjected to power supply noise analysis, and dividing the extracted power supply line into a plurality of power supply lines in a grid pattern. 13 is a power supply wiring sub-model resistance / inductance calculation means for calculating resistance and inductance for each power supply wiring divided by 13.
[0019]
Reference numeral 15 denotes a power supply wiring submodel circuit description creating means for creating a circuit description of a power supply wiring submodel that can be analyzed by a circuit simulator based on the calculation result of the power supply wiring submodel resistance / inductance calculation means 14. In addition, even if the power supply wiring network in the grid is of the same power supply type, it is generally composed of a plurality of wiring layers. May be synthesized. In creating the power supply wiring sub-model, there are a simplified model emphasizing analysis time and a detailed model emphasizing analysis accuracy.
[0020]
FIG. 3 is a configuration diagram of the internal capacitance sub-model creating means 9. In FIG. 3, reference numeral 16 extracts the capacitance between the power supply lines, the arrangement information of the decoupling capacitors, the arrangement information of the logic gates, and the arrangement information of the signal lines driven by the logic gates from the layout information of the semiconductor device to be analyzed for power supply noise. , Are internal capacitance dividing means for dividing them into a lattice like the case of dividing the power supply wiring.
[0021]
Reference numeral 17 denotes an internal capacitance calculating means for calculating the capacitance value in the lattice by combining the capacitance between the power supply wires, the capacitance of the decoupling capacitor, and the capacitance of the transistor included in each lattice. When calculating the capacitance in the internal capacitance calculation means 17, it is optimal to combine resistances connected in series with the capacitance and combining those having similar time constants determined by the resistance and the capacitance. is there. This makes it possible to accurately model the frequency characteristics of the decoupling cell and the frequency characteristics when the inactive logic gate behaves like a decoupling cell.
[0022]
Reference numeral 18 denotes an internal capacitance submodel circuit description creation unit that creates a circuit description of an internal capacitance submodel that can be analyzed by a circuit simulator based on the calculation result of the internal capacitance calculation unit 17. Internal capacitances with different time constant values are created as separate circuit descriptions.
[0023]
FIG. 4 is a configuration diagram of the internal current consumption sub-model creating means 10. In FIG. 4, reference numeral 19 denotes an internal current consumption dividing means for extracting the arrangement information of the logic gates from the layout information of the semiconductor device to be analyzed for power supply noise, and dividing the arrangement information into a grid pattern as in the case of dividing the power supply wiring.
[0024]
Reference numeral 20 denotes an internal current consumption calculation unit that combines the current consumption waveforms in consideration of the switching timing of the logic gate included in each grid and calculates the current consumption waveform in the grid. If the switching timing of the logic gates in the lattice is unknown, the average current consumption in one cycle is calculated from the operating frequency of the chip and the power consumption, and the current consumption is determined without changing the charge consumption in one cycle. Create a waveform.
[0025]
Reference numeral 21 denotes an internal current consumption submodel circuit description creation unit that creates a circuit description of an internal current consumption submodel that can be analyzed by a circuit simulator based on the calculation result of the internal current consumption calculation unit 20.
[0026]
FIG. 5 is a configuration diagram of the input / output sub-model creating means 11. Reference numeral 22 denotes an input / output cell dividing unit that extracts an arrangement of input / output cells from layout information of a semiconductor device to be analyzed for power supply noise. The input / output cells used for power supply noise analysis are classified into four types: an input cell model, an output cell model, an input / output cell model, and a power supply cell model.
[0027]
23 generates a signal of an external signal source in the case of the input cell model and the input / output cell model based on the operating condition of the semiconductor device to be analyzed for power supply noise, and generates the signal of the external signal source in the case of the output cell model and the input / output cell model. , An input signal generating means for generating a signal of an internal signal source and generating a control signal for switching the polarity (input or output) in the case of an input / output cell model.
[0028]
By properly setting the input signal generated by the input signal generating means 23, it is possible to analyze the noise generated by the simultaneous switching of the input and output cells and the influence of the delay variation of the input and output cells caused by the noise. It is possible. In addition, it is possible to analyze the behavior of the input / output cells when the input and output polarities are switched under such a power supply noise situation.
[0029]
Reference numeral 24 denotes the internal capacity driven by the input cell and the input / output cell, the resistance, capacitance, and inductance of the bonding wire and lead frame of the package, and the damping mounted on the printed circuit board, based on the load condition of the semiconductor device to be analyzed for power supply noise. It is a load generating means for creating a resistance, a distributed constant line as a signal wiring / power supply wiring, and an external load.
[0030]
Reference numeral 25 denotes a circuit description of input / output cells arranged in accordance with the arrangement of the input / output cells, and an input signal generated by the input signal generating means 23 and a load generated by the load generating means 24 are combined with the input / output to be analyzed by a circuit simulator. This is an input / output submodel circuit description creation unit that creates a circuit description of the submodel.
[0031]
FIG. 6 is a flowchart showing one embodiment of the semiconductor device model creation method of the present invention (semiconductor device model creation method using the semiconductor device model creation device of the present invention). One embodiment of the semiconductor device model creation method according to the present invention includes: (1) creation of a power supply wiring submodel by the power supply wiring submodel creation means 8; and (2) creation of an internal capacitance submodel creation means for a semiconductor device to be analyzed for power supply noise. 9 to create an internal capacitance submodel, 3) create an internal current consumption submodel by the internal current consumption submodel creation means 10, and 4) create an input / output submodel by the input / output submodel creation means 11. Finally, (5) a semiconductor device model for power supply noise analysis is created by the submodel coupling means 12.
[0032]
FIGS. 7 to 9 are conceptual diagrams of the power supply wiring sub-model created by the power supply wiring sub-model creation means 8. In the present embodiment, the power supply wiring is divided into a plurality of layers according to the type of power supply, and each layer is divided into a grid by the specified number of divisions, and the resistance and inductance of the power supply wiring present in each of the divided areas (power supply grid) are divided. Is assigned to a cross-shaped circuit model to be a power supply wiring sub-model.
[0033]
Note that the power supply wiring network in the grid is generally composed of a plurality of wiring layers even if the power supply type is the same, and upper and lower wiring layers are connected by vias (VIA). When creating the power supply wiring sub-model, the two-dimensional simplified power supply wiring sub-model is synthesized by combining the resistance and inductance of the power supply wiring of different wiring layers of the same power supply type in order to reduce the scale of the model and shorten the analysis time. In order to improve the accuracy of the model and the accuracy of the model, even if the power supply type is the same, the resistance and inductance of the power supply wiring in different wiring layers are individually modeled, and these are modeled as via wiring. , Two methods can be selected for creating a three-dimensional detailed power supply wiring sub model.
[0034]
FIG. 7 is an example of the simple power supply wiring sub model. In FIG. 7, 26 is a VDE wiring layer which is a 3.3V system power supply wiring layer, 27 is a VDD wiring layer which is a 1.2V system power supply wiring layer, and 28 is a 0V (ground) system power supply wiring layer VSS. A wiring layer 29 indicates one of the power supply wiring sub-models.
[0035]
That is, in the example of FIG. 7, the power supply wiring layer is a square of 2 mm × 2 mm, and is divided into a VDE wiring layer 26, a VDD wiring layer 27, and a VSS wiring layer 28, and the VDE wiring layer 26, the VDD wiring layer 27 and the VSS wiring layer 28 are each divided into 4 (vertical) × 4 (horizontal), and the resistance and the inductance of the power supply wiring existing in the divided grid region of 500 μm × 500 μm are reduced by the same wiring layer of the same power supply wiring type. After synthesizing, the power supply wiring sub-model is created by allocating it to a two-dimensional cross-shaped circuit model.
[0036]
FIG. 8 is an example of the simple power supply wiring sub model as in FIG. In FIG. 8, reference numeral 30 denotes a VDE wiring layer which is a 3.3V power supply wiring layer, 31 denotes a VDD wiring layer which is a 1.2V power supply wiring layer, 32 denotes a VSS wiring layer which is a 0V power supply wiring layer, Reference numerals 33 and 34 each indicate one of the power supply wiring sub-models.
[0037]
That is, in the example of FIG. 8, the power supply wiring layer is a square of 2 mm × 2 mm, and is divided into a VDE wiring layer 30, a VDD wiring layer 31, and a VSS wiring layer 32. These VDE wiring layers 30, VDD wiring layers 31 and the VSS wiring layer 32 are divided into 8 (vertical) × 8 (horizontal), respectively, and the resistance and the inductance of the power supply wiring existing in the divided grid area of 250 μm × 250 μm are set to different wiring layers of the same power supply wiring type. After synthesizing, the power supply wiring sub-model is created by allocating it to a two-dimensional cross-shaped circuit model.
[0038]
FIG. 9 shows an example of the detailed power supply wiring sub-model. In FIG. 9, reference numeral 35 denotes a VSS wiring first layer; 36, a VSS wiring second layer; 37, a VSS wiring third layer; A power supply wiring sub model, 40 is a via model, and 41 is a three-dimensional power supply wiring sub model.
[0039]
That is, in the example of FIG. 9, the power supply wiring layer is a square of 2 mm × 2 mm, and the VSS wiring, which is the power supply wiring layer of the 0 V system, includes the VSS wiring first layer 35, the VSS wiring second layer 36, and the VSS wiring first layer. It is composed of three wiring layers of three layers 37, and the connection between the layers is made by vias.
[0040]
Each of the wiring layers 35 to 37 is divided into 8 (vertical) × 8 (horizontal), and the resistance and inductance of the power supply wiring existing in the divided 250 μm × 250 μm grid region are determined for each power supply wiring type and for each wiring layer. The power supply wiring for the entire VSS is connected to the two-dimensional cross-shaped circuit model, and the via portion is also considered as a vertical power supply wiring. The three-dimensional detailed power supply wiring sub-model has been created. For a power supply type other than VSS (VDE wiring layer, VDD wiring layer, etc.), a three-dimensional detailed power supply wiring sub-model can be created in the same manner.
[0041]
In the case of the examples of FIGS. 7 to 9, depending on the location of the grid, a structure in which the power supply wiring is cut off may be considered, and if the cross-shaped circuit model is applied as it is, uncoupled resistance and inductance may remain. . In such a case, it is necessary to delete the relevant part. This processing can be performed manually, but can also be performed automatically by a program when the model is created. The power supply wiring sub-model 33 in FIG. 8 and the power supply wiring sub-models 38 and 39 in FIG. 9 are examples of one of the power supply wiring sub-models subjected to the deletion processing.
[0042]
By modifying the power supply wiring sub-model in this way, it becomes possible to model various wiring structures, and it is possible to model a flip-chip type semiconductor device, a semiconductor device including a macro having a different operating voltage, or the like. It is also possible to model a semiconductor device of a type in which power supply wiring is not uniform, such as a semiconductor device in which an internal ground line is divided.
[0043]
Further, when the substrate portion of the semiconductor device is regarded as a power supply wiring and the detailed power supply wiring sub-model creation method shown in FIG. 9 is applied, a substrate model that can be combined with the semiconductor device model can be created. By connecting the board model to the power supply wiring sub-model, it is possible to analyze the propagation of noise through the board.
[0044]
As for the values of resistance and inductance in the power supply wiring sub model and via model, values estimated from design specifications are set, or values extracted from an actual layout are used. In addition, in the examples of FIGS. 7 to 9, although the number of divisions is small, if the number of divisions is sufficiently large, the power supply wiring network is represented as a distributed constant line, and the behavior of the power supply wiring noise is described in detail. It becomes possible to analyze.
[0045]
FIG. 10 is a conceptual diagram of an example of the internal capacity sub model created by the internal capacity sub model creation means 9. 10, reference numeral 42 denotes a VDE power supply wiring submodel or VDD power supply wiring submodel, 43 denotes a VSS power supply wiring submodel, and 44 denotes an internal capacitance submodel. The internal capacitance submodel 44 includes a capacitance between power supply lines existing in a plane represented by the two power supply line submodels 42 and 43 of interest, a capacitance of a decoupling capacitor for reducing power supply noise, a logic The total value of the gate capacitance is defined as the capacitance.
[0046]
As described above, since the semiconductor device is divided into a lattice shape and modeling is performed with the total value of the capacitance existing inside each lattice as a unit, the distribution of the capacitance inside the semiconductor device can be expressed. It is possible to accurately analyze the effect of the capacitance component that reduces power supply noise, such as optimizing the arrangement of the ring capacitor.
[0047]
FIGS. 11 and 12 are conceptual diagrams of another example of the internal capacitance submodel created by the internal capacitance submodel creation means 9. 11 and 12, reference numeral 45 denotes an internal capacitance sub model. The internal capacitance submodel 45 includes a capacitance between power supply lines existing in a plane represented by the two power supply line submodels 42 and 43 of interest, a capacitance of a decoupling capacitor, and a capacitance of a logic gate that is not operating. And the capacitances of the signal wirings driven by the logic gates, and the resistance components present in series with the capacitances.
[0048]
The resistance component includes the resistance of the transistor inside the logic gate, the resistance of the signal wiring, and the like. As described above, since the semiconductor device is divided into a lattice shape and modeling is performed with the capacitance existing inside each lattice as a unit, the distribution of the capacitance inside the semiconductor device can be expressed.
[0049]
FIG. 11 is a simplified internal capacitance submodel obtained by combining these capacitance and resistance components existing in the region represented by one power supply wiring submodel into one. When the variation in the time constant determined by the capacitance existing inside the lattice region and its resistance component is small, the scale of the model can be reduced by using the simplified model.
[0050]
In general, there are various combinations of capacitance and resistance existing in the region, which means that the time constants are different. The difference in the time constant means the difference in the frequency characteristic, and the response of the internal capacitance to noise is not uniform.
FIG. 12 shows a detailed internal capacitance submodel used in such a case, in which models having close time constants are combined and modeled by a separate circuit for each group of time constants. By doing so, it becomes possible to analyze the difference in the frequency response of these internal capacitances to the noise of the semiconductor device.
[0051]
For example, if the logic gate and the decoupling cell are defined as separate internal capacitance models in FIG. 12, the model can correctly represent the frequency characteristics of the decoupling cell and the frequency characteristics of the inactive logic gate. By performing analysis using this model, it is possible to determine the type of decoupling cell and to optimize the arrangement.
[0052]
FIG. 13 is a conceptual diagram of the internal current consumption submodel created by the internal current consumption submodel creation means 10. In FIG. 13, reference numeral 46 denotes an internal current consumption sub model. The internal current consumption sub model 46 is defined as a current source of the total value of the current consumption of the logic gates existing in the plane represented by the power supply wiring sub models 42 and 43 of interest.
[0053]
The current consumption can be synthesized in consideration of the switch timing of each logic gate existing in the plane, or a value estimated by a designer can be set. It is also possible to combine only the clock circuits in the plane in consideration of the switch timing, and combine the remaining logic gates with the estimated values.
[0054]
As described above, regarding the internal current consumption, the distribution of the current consumption inside the semiconductor device is expressed because the semiconductor device is divided into a lattice shape and modeling is performed in consideration of the switch timing of the logic gates present therein. For example, current consumption waveforms can be individually set for a local arrangement of a clock buffer, a data path portion, a RAM, and the like, and power supply noise caused by current consumption by a logic gate inside a semiconductor device can be analyzed with high accuracy. It is possible to do.
[0055]
FIG. 14 is a conceptual diagram of an example of the input cell model created by the input / output submodel creation means 11. In this input cell model, a transistor level circuit description 47 of an input cell is arranged at an actual position of a semiconductor device, and an external signal 48, a distributed constant line 49, a damping resistor 50, a bonding wire / lead frame 51, and an internal load 52 are connected. It is composed.
[0056]
FIG. 15 is a conceptual diagram of another example of the input cell model created by the input / output submodel creating means 11. In this input cell model, a transistor level circuit description 47 of an input cell is arranged at an actual position of a semiconductor device, and an external signal 48, a distributed constant line 49, a damping resistor 50, a lead frame 51A, a bonding wire 51B, and an internal load 52 are connected. Connected and configured.
[0057]
Here, the distributed constant line 49 represents the wiring on the board outside the semiconductor device, and the internal load 52 represents the capacitance of the wiring connecting the input cell 47 and the logic gate and the gate capacitance of the logic gate itself. ing. The input cell model is also connected to power supply wiring sub-models 53, 54, and 55 that exist directly above the input cell of interest.
[0058]
14 and 15, the bonding wire / lead frame 51, the lead frame 51A, and the bonding wire 51B are each represented by one set of resistance and inductance for simplicity. It may be a circuit network composed of capacitance and inductance. Although FIG. 15 illustrates a semiconductor device mounted on a peripheral type, a flip-chip mounted semiconductor device can be expressed by making the bonding wires 51B correspond to bumps.
[0059]
FIG. 16 is a conceptual diagram of an example of the output cell model created by the input / output submodel creation means 11. In this output cell model, a transistor level circuit description 56 of an output cell is arranged at an actual position of a semiconductor device, and an external load 57, a distributed constant line 58, a damping resistor 59, a bonding wire / lead frame 60, and an internal signal 61 are connected. It is composed.
[0060]
FIG. 17 is a conceptual diagram of another example of the output cell model created by the input / output submodel creation means 11. In this output cell model, a transistor level circuit description 56 of an output cell is arranged at an actual position of a semiconductor device, and an external load 57, a distributed constant line 58, a damping resistor 59, a lead frame 60A, a bonding wire 60B and an internal signal 61 are connected. Connected and configured.
[0061]
Here, the distributed constant line 58 represents wiring on the board outside the semiconductor device, and the internal signal 61 represents the input signal waveform near the input terminal of the output cell 56. The output cell model is also connected to power supply wiring sub-models 62, 63, and 64 that are located directly above the output cell of interest.
[0062]
16 and 17, the bonding wire / lead frame 60, the lead frame 60A, and the bonding wire 60B are each represented by one set of resistance and inductance for simplicity. It may be a circuit network composed of capacitance and inductance. Although FIG. 17 illustrates a semiconductor device mounted on a peripheral type, a semiconductor device mounted on a flip chip can be expressed by making the bonding wires 60B correspond to bumps.
[0063]
FIG. 18 is a conceptual diagram of an example of an input / output cell model created by the input / output submodel creation means 11. In the input / output cell model, a transistor level circuit description 65 of the input / output cell is arranged at an actual position of the semiconductor device, and an external signal 66, an external load 67, an operation changeover switch 68, a distributed constant line 69, a damping resistor 70, a bonding wire -It is configured by connecting a lead frame 71, an internal load 72, an internal signal 73, and an internal operation switching signal (not shown).
[0064]
FIG. 19 is a conceptual diagram of another example of the input / output cell model created by the input / output submodel creation means 11. In the input / output cell model, a transistor level circuit description 65 of the input / output cell is arranged at an actual position of the semiconductor device, and an external signal 66, an external load 67, an operation changeover switch 68, a distributed constant line 69, a damping resistor 70, a lead frame 71A, a bonding wire 71B, an internal load 72, an internal signal 73, and an internal operation switching signal (not shown) are connected.
[0065]
In the case of an input / output cell, since it operates both as an input cell and an output cell, it has a configuration in which an operation switching mechanism is added to a combination of an input cell model and an output cell model. In the examples of FIGS. 18 and 19, the external operation is switched by the switch 68, but a transistor circuit such as an input / output cell can be used for this part.
[0066]
Here, the distributed constant line 69 represents wiring on the board outside the semiconductor device, and the internal load 72 represents the capacitance of the wiring connecting the input cell 65A and the logic gate and the input capacitance of the logic gate itself. ing. The internal signal 73 represents an input signal waveform near the input terminal of the output cell 65B.
[0067]
The input / output cell model is also connected to power supply wiring submodels 74, 75, and 76 that are located immediately above the output cell of interest. By appropriately setting the input / output switching control signal for the input / output cell model and performing the analysis, it is also possible to analyze the dynamic switching of the input / output cell operation mode (input mode or output mode). Become.
[0068]
In FIGS. 18 and 19, the bonding wire / lead frame 71, the lead frame 71A, and the bonding wire 71B are each represented by one set of resistance and inductance for simplicity. It may be a circuit network composed of capacitance and inductance. Although FIG. 19 illustrates a semiconductor device mounted on a peripheral type, a semiconductor device mounted on a flip chip can be expressed by making the bonding wires 71B correspond to bumps.
[0069]
FIG. 20 is a conceptual diagram of an example of the power supply cell model created by the input / output submodel creation means 11. The power supply cell model of VDE or VDD is configured by arranging a power supply cell 77 at an actual position of a semiconductor device, adding an external power supply (VDE or VDD) 78 and a bonding wire / lead frame 79, and includes a power supply wiring sub model 80. Connected to.
[0070]
In this example, the external power supply 78 is directly connected to the bonding wire / lead frame 79. However, between the external power supply 78 and the bonding wire / lead frame 79, a distributed constant line expressing power supply wiring on the board, A circuit network representing a power plane may be inserted. Although the bonding wire / lead frame 79 is represented by a single set of resistance and inductance for simplicity, it may be a circuit network composed of resistance, capacitance and inductance.
[0071]
The power supply cell model of VSS is configured by arranging a power supply cell 81 at an actual position of a semiconductor device, adding an external power supply (VSS) 82 and a bonding wire / lead frame 83, and connected to a power supply wiring sub model 84. . The power supply cells 77 and 81 have the same structure although the voltage values of the external power supplies 78 and 82 connected to each power supply type are different.
[0072]
In this example, the external power supply 82 is directly connected to the bonding wire / lead frame 83. However, between the external power supply 82 and the bonding wire / lead frame 83, a distributed constant line representing a power supply wiring on the board, A circuit network representing a power plane may be inserted. Although the bonding wire / lead frame 83 is represented by one set of resistance and inductance for simplicity, it may be a circuit network composed of resistance, capacitance and inductance.
[0073]
FIG. 21 is a conceptual diagram of another example of the power supply cell model created by the input / output submodel creation means 11. The power supply cell model of VDE or VDD is configured by arranging a power supply cell 85 at an actual position of a semiconductor device and adding an external power supply (VDE or VDD) 86, a lead frame 87, and a bonding wire 88. 89.
[0074]
In this example, the external power supply 86 is directly connected to the lead frame 87. However, between the external power supply 86 and the lead frame 87, a distributed constant line representing a power supply wiring on a board and a circuit representing a power supply plane are provided. A net may be inserted. In addition, the power supply cell 85 is represented by resistance / inductance. However, if a circuit description of the power supply cell is separately provided, it may be replaced with that. Although the lead frame 87 and the bonding wire 88 are each represented by one set of resistance and inductance for simplicity, this may be a circuit network composed of resistance, capacitance and inductance.
[0075]
The power supply cell model of VSS is configured by arranging a power supply cell 90 at an actual position of a semiconductor device, adding an external power supply (VSS) 91, a lead frame 92, and a bonding wire 93, and connected to a power supply wiring sub model 94. You. The power supply cells 85 and 90 have the same structure, although the voltage values of the external power supplies 86 and 91 connected for each power supply type are different.
[0076]
In this example, the external power supply 91 is directly connected to the lead frame 92. However, between the external power supply 91 and the lead frame 92, a distributed constant line representing a power supply wiring on a board or a circuit representing a power supply plane is provided. A net may be inserted. Although the inside of the power supply cell 90 is represented by resistance / inductance, if the circuit description of the power supply cell is separately provided, it may be replaced with that. Although the lead frame 92 and the bonding wire 93 are each represented by a single set of resistance and inductance for simplicity, a circuit network composed of resistance, capacitance and inductance may be used here.
[0077]
Although FIG. 21 illustrates a semiconductor device mounted on a peripheral type, a semiconductor device mounted on a flip chip can be expressed by making the bonding wires 88 and 93 correspond to bumps.
[0078]
As described above, the input / output submodels such as the input cell model, the output cell model, the input / output cell model, and the power supply cell model express the vicinity of the input / output cells of the actual semiconductor device in detail. By creating an output submodel, it is possible to analyze details of power supply noise near input / output cells.
[0079]
FIG. 22 is a conceptual diagram of an example of a semiconductor device model for power supply noise analysis created by the sub-model coupling unit 12 (one embodiment of the semiconductor device model of the present invention). In FIG. 22, reference numeral 95 denotes a semiconductor device, and power supply wiring submodels 97 and 98, an internal capacitance submodel 99, and an internal current consumption submodel 100 are created in a square portion 96. Also, 101 is an input cell model, 102 is an output cell model, 103 is an input / output cell model, and 104 and 105 are power supply cell models.
[0080]
FIG. 23 is a conceptual diagram of another example of the semiconductor device model for power supply noise analysis created by the sub-model coupling unit 12 (another embodiment of the semiconductor device model of the present invention). In FIG. 23, reference numeral 106 denotes a semiconductor device, and power supply wiring submodels 108 and 109, an internal capacitance submodel 110, and an internal current consumption submodel 111 are created in a die portion 107 of the semiconductor device. Reference numeral 112 denotes an input cell model, 113 denotes an output cell model, 114 denotes an input / output cell model, and 115 and 116 denote power cell models.
[0081]
In the examples of FIGS. 22 and 23, the case where a peripheral type package is used is described as an example. Similarly, a semiconductor device model for power supply noise analysis can be created for a flip-chip type semiconductor device arranged at the position of.
[0082]
24 and 25 are diagrams showing examples of power supply noise analysis results using a semiconductor device model for power supply noise analysis created by using the method and apparatus for creating a semiconductor device model according to the present invention. In this example, simultaneous switching of logic gates occurs locally, then simultaneous switching of input / output cells occurs, and then simultaneous switching of logic gates occurs locally at the center of the semiconductor device. .
[0083]
FIG. 24 is a voltage waveform graph near the center of the semiconductor device of the VDD wiring and the VSS wiring. During power supply noise analysis, the current consumption in the logic gate and the simultaneous switching of the input and output cells are set, so the observed power supply noise depends on the power supply on each power supply wiring in the presence of both these effects. It is noise.
[0084]
According to the power supply noise analysis result, both in-phase noise and anti-phase noise are generated between the VDD wiring and the VSS wiring, that is, between the power supplies of the logic gates inside the semiconductor device. The main cause of common-mode noise is simultaneous switching of input / output cells, and the main cause of negative-phase noise is simultaneous switching of logic gates.
[0085]
FIG. 25 is a graph showing the voltage distribution of the VSS wiring of the entire semiconductor device. FIG. 25A shows the time point 0 on the graph shown in FIG. 24, and FIG. 25B shows the time point 2.475 ns on the graph shown in FIG. ing. FIG. 25B shows that the amplitude of the power supply noise increases due to local current consumption at the center of the semiconductor device.
[0086]
In this manner, when the power supply noise analysis results at each time are collected in order of time to create a moving image, it is possible to observe where power supply noise occurs inside the semiconductor device and how it propagates to the surroundings, The range in which the noise reduction effect of the decoupling capacitor is effective can be checked.
[0087]
As described above, in the present embodiment, a power supply wiring submodel, an internal capacitance submodel, an internal current consumption submodel, and an input / output submodel are created for a semiconductor device to be analyzed for power supply noise. The values of various parameters given to the device can be set in consideration of design specifications or can be set to values extracted from actual layout information, and include flip-chip type semiconductor devices, macros with different operating voltages, etc. High-precision modeling is possible for a semiconductor device or a semiconductor device in which power supply wiring is not uniform, such as a semiconductor device in which an internal ground line is intentionally divided.
[0088]
In addition, simultaneous switching noise of input / output cells and simultaneous switching noise of logic gates can be analyzed at the same time, so that simultaneous switching noise caused by input / output cells and simultaneous switching noise caused by logic gates exist. It is possible to express the generation process and spatial distribution of power supply noise of the entire semiconductor device, and to observe how the delay of input / output cells changes due to the power supply noise.
[0089]
In addition, the power supply wiring submodel is created for each type of power supply wiring in units of grid-divided semiconductor devices to be analyzed for power supply noise, so they are modeled individually according to the type and location of power supply wiring Since the minimum unit of the circuit model is a circuit composed of a cross-shaped resistor and an inductance, a value estimated by a designer is set as the value of the resistance and the inductance of the circuit, or It is possible to set a value extracted from the actual layout, and it is possible to express the difference depending on the location of the wiring shape as a distribution constant, and to perform a detailed power supply network analysis.
[0090]
In addition, the internal capacitance submodel is a model of the capacitance or the capacitance and the resistance existing in the plane represented by the power wiring submodel of interest. The capacitance includes the capacitance between the power wiring and the power wiring. Since it is assumed that the capacity of the logic gate included in the plane when divided into a lattice and the capacity of the decoupling capacitor intentionally arranged by the designer are included, the arrangement density of the power supply wiring, the logic gate, and the decoupling capacitor is included. The variation in the capacitance distribution due to the difference can be expressed.
[0091]
In addition, since the internal current consumption submodel is a model of the current consumption in the plane represented by the power supply wiring submodel of interest, the difference in the arrangement density of the logic gates inside the semiconductor device and the current consumption for each macro are calculated. Modeling can be performed, and variations in current consumption inside the semiconductor device can be expressed.
[0092]
In addition, since the input / output submodel expresses in detail the vicinity of the input / output cells of the actual semiconductor device, it is possible to analyze the details of power supply noise near the input / output cells. Furthermore, since the input / output cell model in the input / output sub-model can express dynamic switching between the input mode and the output mode, it is also possible to analyze noise generated when the operation is switched. .
[0093]
Therefore, according to the present embodiment, since a detailed model of the entire semiconductor device to be analyzed for power supply noise can be created, the behavior of power supply noise can be analyzed with high accuracy, and not only inside the semiconductor device, Optimization outside the semiconductor device, such as selection of a package, wiring on a board, and adjustment of damping resistance, can be performed.
[0094]
In particular, the analysis of the temporal change and spatial distribution of noise appearing on the power supply wiring of the semiconductor device in the presence of the switching noise of the logic gate of the semiconductor device and the switching noise of the input / output cells of the semiconductor device, and This is useful when analyzing the delay fluctuation of the input / output cell of the semiconductor device due to.
[0095]
Here, to summarize the present invention, the present invention includes the following semiconductor device model creation method and device, semiconductor device model, and semiconductor device substrate model.
[0096]
(Supplementary Note 1) A step of creating a model of a power supply wiring, an internal capacitance, an internal current consumption, and an input / output cell of a semiconductor device to be analyzed for power supply noise, and the power supply wiring, the internal capacitance, the internal current consumption, and the input / output cell A method of creating a semiconductor device model for power supply noise analysis for the semiconductor device to be analyzed for power supply noise.
[0097]
(Supplementary Note 2) The method of creating a semiconductor device model according to Supplementary Note 1, wherein the model of the power supply wiring is created for each type of power supply wiring in units of a region obtained by dividing the semiconductor device into a lattice.
[0098]
(Supplementary Note 3) The semiconductor device model creation method according to Supplementary Note 1, wherein the power supply wiring model is configured by applying a circuit model in which a resistance and an inductance are arranged in a cross shape.
[0099]
(Supplementary Note 4) The power supply wiring model is created by synthesizing different wiring layers of the same power supply type for each type of power supply wiring in units of regions obtained by dividing the semiconductor device into a lattice. 3. The method for creating a semiconductor device model according to claim 1.
[0100]
(Supplementary Note 5) As the power supply wiring model, a two-dimensional model is created for each type of power supply wiring and for each power supply wiring layer in units of regions obtained by dividing the semiconductor device into a lattice, and different power supply wiring layers of the same power supply type are used. 3. The method for creating a semiconductor device model according to claim 1, wherein the two-dimensional models are connected as a three-dimensional model by connecting via models.
[0101]
(Supplementary Note 6) The method of creating a semiconductor device model according to Supplementary Note 1, wherein the model of the internal capacitance is created in units of a capacitance existing in a plane represented by a model of a power supply wiring of interest.
[0102]
(Supplementary note 7) The method of creating a semiconductor device model according to supplementary note 1, wherein the model of the internal capacitance is created in consideration of a capacitance and a resistance existing in a plane expressed by a model of a power supply wiring of interest.
[0103]
(Supplementary Note 8) The method of creating a semiconductor device model according to Supplementary Note 1, wherein the model of the internal current consumption is created in units of a current consumption in a plane represented by a model of a power supply wiring of interest.
[0104]
(Supplementary Note 9) The step of creating a model of the power supply wiring includes extracting a power supply wiring from the layout information of the semiconductor device, and dividing the extracted power supply wiring into a plurality of power supply wirings in a grid pattern. 2. The semiconductor according to claim 1, further comprising: calculating a resistance and an inductance for each of the power supply wirings divided by the step (a), and creating a circuit description of a model of the power supply wiring based on the calculation result of the step. Device model creation method.
[0105]
(Supplementary Note 10) The step of creating the model of the internal capacitance includes the step of extracting the capacitance between power supply wirings and the arrangement information of the decoupling capacitor and the logic gate from the layout information of the semiconductor device, and dividing them into a grid. Calculating the capacitance value in the lattice by combining the capacitance of the power supply wiring, the capacitance of the decoupling capacitor, and the capacitance of the logic gate included in each of the lattices divided by the step; 2. The method according to claim 1, further comprising the step of creating a circuit description of the model of the internal capacitance based on the result.
[0106]
(Supplementary Note 11) The step of creating the model of the internal current consumption includes a step of extracting the arrangement information of the logic gates from the layout information of the semiconductor device and dividing the same into a grid shape, A step of synthesizing a current consumption waveform in consideration of the timing of switching of the logic gates included therein, and calculating a current consumption waveform in the grid; and 2. The method for creating a semiconductor device model according to claim 1, further comprising the step of creating a circuit description.
[0107]
(Supplementary Note 12) The step of creating the model of the input / output cell includes the step of extracting the arrangement of the input / output cell from the layout information of the semiconductor device and the operation of the input / output cell based on the operating condition of the semiconductor device to be analyzed for power supply noise. In the case of a cell model and an input / output cell model, a signal of an external signal source is generated.In the case of an output cell model and an input / output cell model, a signal of an internal signal source is generated. Is the process of generating a control signal to switch the polarity, the process of creating the internal capacitance, the bonding wire / lead frame resistance / capacity / inductance, the damping resistance, the distributed constant line, and the external load. Arranging a circuit description of a cell, and combining the input signal and the load with the cell description to create a circuit description of a model of the input / output cell. Appendix 1 semiconductor device modeling method according.
[0108]
(Supplementary Note 13) Means for creating a model of a power supply line, an internal capacitance, an internal current consumption, and an input / output cell of a semiconductor device to be analyzed for power supply noise, and the power supply line, the internal capacitance, the internal current consumption, and the input / output cell A semiconductor device model for power supply noise analysis for the semiconductor device to be analyzed for power supply noise.
[0109]
(Supplementary Note 14) The means for creating a model of the power supply wiring, internal capacitance, internal current consumption, and input / output cells of the semiconductor device includes: means for creating a model of the power supply wiring from layout information of the semiconductor device; Means for creating the model of the internal capacitance from the layout information, means for creating the model of the internal current consumption from the layout information and operating conditions of the semiconductor device, and the layout information, operating conditions, load conditions and 14. The semiconductor device model creation apparatus according to claim 13, further comprising means for creating a model of the input / output cell from a circuit description of the input / output cell.
[0110]
(Supplementary Note 15) The means for creating a model of the power supply wiring includes: extracting a power supply wiring from the layout information of the semiconductor device; and dividing the extracted power supply wiring into a plurality of power supply wirings in a grid pattern. 15. A semiconductor device according to claim 14, further comprising: means for calculating resistance and inductance for each of the power supply wirings divided according to (1), and means for creating a circuit description of a model of the power supply wiring based on the calculation result of the means. Equipment model creation equipment.
[0111]
(Supplementary Note 16) The means for creating the model of the internal capacitance includes a means for extracting capacitance between power supply wirings and arrangement information of a decoupling capacitor and a logic gate from layout information of the semiconductor device, and dividing these into a grid. Means for calculating a capacitance value in the grid by combining the capacity of the power supply wiring, the capacity of the decoupling capacitor, and the capacity of the logic gate included in each of the grids divided by the means; 15. The semiconductor device model creation apparatus according to claim 14, further comprising means for creating a circuit description of the model of the internal capacitance based on a result.
[0112]
(Supplementary note 17) The semiconductor device model creation apparatus according to supplementary note 16, wherein the means for calculating the capacitance value also calculates a component of a resistance connected in series with the capacitance.
[0113]
(Supplementary Note 18) The means for creating the model of the internal current consumption includes means for extracting arrangement information of logic gates from layout information of the semiconductor device and dividing the information into grids, and for each of the grids divided by the means. Means for synthesizing the current consumption waveform in consideration of the switching timing of the logic gate included in the circuit, and calculating the current consumption waveform in the lattice; based on the calculation result of the means, the model of the internal current consumption model 15. The semiconductor device model creation device according to claim 14, further comprising means for creating a circuit description.
[0114]
(Supplementary Note 19) The means for creating the model of the input / output cell includes a means for extracting the arrangement of the input / output cell from the layout information of the semiconductor device, and an input based on the operating condition of the semiconductor device to be analyzed for the power supply noise. In the case of a cell model and an input / output cell model, a signal of an external signal source is generated.In the case of an output cell model and an input / output cell model, a signal of an internal signal source is generated. Means for generating a control signal for switching the polarity, means for creating internal capacitance, bonding wire / lead frame resistance / capacity / inductance, damping resistance, distributed constant line, external load, and input / output according to the arrangement of input / output cells Means for arranging a circuit description of a cell, and combining the input signal and load with the cell description to create a circuit description of a model of an input / output cell. Appendix 14 The semiconductor device model generating apparatus according.
[0115]
(Supplementary Note 20) A semiconductor device model comprising a combination of a power supply wiring, an internal capacitance, an internal current consumption, and an input / output cell model of the semiconductor device.
[0116]
(Supplementary Note 21) The creation and coupling of the power supply wiring, internal capacitance, internal current consumption, and input / output cell model of the semiconductor device are performed by the semiconductor device model creation method described in Appendix 1 or the semiconductor device model creation device described in Appendix 13. 21. The semiconductor model according to supplementary note 20, wherein:
[0117]
(Supplementary Note 22) A semiconductor device board model creation method for creating a semiconductor device board model that can be combined with the semiconductor device model created by the semiconductor device model creation method according to Supplementary Note 1, wherein the semiconductor device board model is the semiconductor A method for creating a substrate model of a semiconductor device, wherein the device is created in units of regions obtained by dividing the device into a lattice.
[0118]
【The invention's effect】
As described above, according to the present invention, a model of the power supply wiring, the internal capacitance, the internal current consumption, and the input / output cell of the semiconductor device to be analyzed for power supply noise is created, and the power supply wiring, the internal capacitance, the internal current consumption, and the input / output cell are created. By combining the output cell models and creating a power supply noise analysis semiconductor device model for the power supply noise analysis target semiconductor device, a detailed model of the entire power supply noise analysis target semiconductor device can be created. Therefore, the behavior of the power supply noise of the power supply noise analysis target semiconductor device can be analyzed with high accuracy.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an embodiment of a semiconductor device model creation device of the present invention.
FIG. 2 is a configuration diagram of a power supply wiring sub-model creation unit included in an embodiment of the semiconductor device model creation device of the present invention.
FIG. 3 is a configuration diagram of an internal capacitance sub-model creating unit included in an embodiment of the semiconductor device model creating apparatus of the present invention.
FIG. 4 is a configuration diagram of an internal current consumption sub-model creating unit included in an embodiment of the semiconductor device model creating apparatus of the present invention.
FIG. 5 is a configuration diagram of an input / output submodel creation unit included in an embodiment of the semiconductor device model creation device of the present invention.
FIG. 6 is a flowchart of one embodiment of a semiconductor device model creation method of the present invention (a semiconductor device model creation method using one embodiment of the semiconductor device model creation device of the present invention).
FIG. 7 is a conceptual diagram of an example of a power supply wiring sub-model created by a power supply wiring sub-model creation means included in an embodiment of the semiconductor device model creation apparatus of the present invention.
FIG. 8 is a conceptual diagram of another example of the power supply wiring sub-model created by the power supply wiring sub-model creation means provided in one embodiment of the semiconductor device model creation apparatus of the present invention.
FIG. 9 is a conceptual diagram of still another example of the power supply wiring sub-model created by the power supply wiring sub-model creation means provided in one embodiment of the semiconductor device model creation apparatus of the present invention.
FIG. 10 is a conceptual diagram of an example of an internal capacitance sub-model created by an internal capacitance sub-model creating means included in an embodiment of the semiconductor device model creating apparatus of the present invention.
FIG. 11 is a conceptual diagram of another example of the internal capacitance sub-model created by the internal capacitance sub-model creating means included in one embodiment of the semiconductor device model creating apparatus of the present invention.
FIG. 12 is a conceptual diagram of still another example of the internal capacitance sub-model created by the internal capacitance sub-model creating means included in one embodiment of the semiconductor device model creating apparatus of the present invention.
FIG. 13 is a conceptual diagram of an internal current consumption submodel created by an internal current consumption submodel creation unit included in an embodiment of the semiconductor device model creation apparatus of the present invention.
FIG. 14 is a conceptual diagram of an example of an input cell model created by an input / output sub-model creating means included in an embodiment of the semiconductor device model creating apparatus of the present invention.
FIG. 15 is a conceptual diagram of another example of the input cell model created by the input / output sub-model creating means included in one embodiment of the semiconductor device model creating apparatus of the present invention.
FIG. 16 is a conceptual diagram of an example of an output cell model created by an input / output sub-model creating means included in an embodiment of the semiconductor device model creating apparatus of the present invention.
FIG. 17 is a conceptual diagram of another example of the output cell model created by the input / output sub-model creating means included in one embodiment of the semiconductor device model creating apparatus of the present invention.
FIG. 18 is a conceptual diagram of an example of an input / output cell model created by an input / output submodel creation unit included in an embodiment of the semiconductor device model creation apparatus of the present invention.
FIG. 19 is a conceptual diagram of another example of the input / output cell model created by the input / output submodel creation means provided in one embodiment of the semiconductor device model creation apparatus of the present invention.
FIG. 20 is a conceptual diagram of an example of a power supply cell model created by an input / output sub-model creation means provided in an embodiment of the semiconductor device model creation apparatus of the present invention.
FIG. 21 is a conceptual diagram of another example of the power supply cell model created by the input / output submodel creation means provided in the embodiment of the semiconductor device model creation apparatus of the present invention.
FIG. 22 is a conceptual diagram illustrating an example of a semiconductor device model for power supply noise analysis (an embodiment of the semiconductor device model of the present invention) created by a sub-model coupling unit included in an embodiment of the semiconductor device model creating device of the present invention; FIG.
FIG. 23 illustrates another example of a semiconductor device model for power supply noise analysis created by a sub-model coupling unit included in an embodiment of the semiconductor device model creation device of the present invention (another embodiment of the semiconductor device model of the present invention). FIG.
FIG. 24 is a diagram showing an example of a power supply noise analysis result using a semiconductor device model created using one embodiment of the semiconductor device model creation device of the present invention.
FIG. 25 is a diagram illustrating an example of a power supply noise analysis result using a semiconductor device model created using one embodiment of the semiconductor device model creation device of the present invention.
[Explanation of symbols]
1 .... Semiconductor device model creation information storage unit
2 ... Semiconductor device model creation unit
3. Semiconductor device model storage
4. Semiconductor device layout information storage means
5. Semiconductor device operating condition storage means
6. Semiconductor device load condition storage means
7. Semiconductor device circuit description storage means
8 Power supply wiring submodel creation means
9: Internal capacity submodel creation means
10. Internal current consumption submodel creation means
11 Input / output submodel creation means
12 ... Submodel combining means
13 Power supply wiring dividing means
14 Power supply wiring submodel resistance / inductance calculation means
15 Power supply wiring submodel circuit description creation means
16. Internal capacity dividing means
17 ... Internal capacity calculation means
18. Internal capacitance submodel circuit description creation means
19: Internal current consumption dividing means
20 Internal current consumption calculation means
21: Internal current consumption submodel circuit description creation means
22 ... Input / output cell dividing means
23 input signal generating means
24 ... Load generating means
25 Input / output submodel circuit description creation means

Claims (6)

A step of creating a model of a power supply wiring, an internal capacitance, an internal current consumption, and an input / output cell of a semiconductor device to be analyzed for power supply noise;
Combining the power supply wiring, the internal capacitance, the internal current consumption, and the input / output cell model to create a power supply noise analysis semiconductor device model for the power supply noise analysis target semiconductor device. Semiconductor device model creation method. 2. The power supply wiring model is created by combining different wiring layers of the same power supply type with each other for each type of power supply wiring in units of a region obtained by dividing the semiconductor device into a grid. The semiconductor device model creation method described in the above. As the power supply wiring model, a two-dimensional model is created for each type of power supply wiring and for each power supply wiring layer in units of regions obtained by dividing the semiconductor device into a grid, and two-dimensional models of different power supply wiring layers of the same power supply type 2. The method according to claim 1, wherein the three-dimensional model is created by connecting the components with a via model. Means for creating a model of power supply wiring, internal capacitance, internal current consumption and input / output cells of a semiconductor device to be analyzed for power supply noise;
Means for combining the power supply wiring, the internal capacitance, the internal current consumption, and the input / output cell model to create a power supply noise analysis semiconductor device model for the power supply noise analysis target semiconductor device. Semiconductor device model creation device. A semiconductor device model comprising a combination of a power supply wiring, an internal capacitance, an internal current consumption, and an input / output cell model of the semiconductor device. A semiconductor device substrate model creation method for creating a semiconductor device substrate model connectable to a semiconductor device model created by the semiconductor device model creation method according to claim 1, wherein the semiconductor device substrate model comprises a grid of the semiconductor device. A method for creating a semiconductor device substrate model, wherein the semiconductor device is created in units of regions divided in a shape.

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