JP4539376B2 - Transmission signal waveform analysis method and program - Google Patents

Description

  The present invention relates to a transmission signal waveform analysis method and program for analyzing the influence of power supply noise generated inside a semiconductor device on a printed board on a transmission signal between the semiconductor devices on the printed board.

  In recent years, various problems due to power supply noise generated inside a large scale integrated circuit (LSI) mounted on a printed circuit board have become apparent. The power supply noise generated inside the LSI is a power supply voltage fluctuation generated by simultaneous operation of circuits (core logic circuit and I / O circuit) inside the LSI.

  The power supply noise generated inside the LSI propagates not only inside the LSI but also to the printed circuit board. This not only causes circuit malfunctions inside the LSI or on the printed circuit board, but also enters the inter-LSI transmission signal waveform, resulting in a transmission signal waveform. This is a factor that causes logic misrecognition due to quality degradation and timing margin cracking due to delay variation.

  Due to the increase in power supply noise due to the increase in LSI speed, the number of pins, and the increase in current, and the reduction in power supply noise tolerance due to the transmission signal waveform and timing accompanying the increase in bus clock speed and voltage, the power supply noise is transmitted between LSIs. The impact on the market is expected to increase. For this reason, it is desirable to design the circuit in consideration of the influence of power supply noise on the inter-LSI transmission signal.

  Conventionally, as a transmission signal waveform analysis method for analyzing the influence of power supply noise generated inside an LSI on an inter-LSI transmission signal, the power supply structure of each part of the LSI die, package, and printed circuit board and the structure of the inter-LSI transmission signal (driver) A method of using a power supply noise analysis model in which I / O, inter-LSI signal wiring, and receiver I / O) are modeled as a unit is known.

  However, since this transmission signal waveform analysis method models the power supply structure of each part of the LSI die, package, and printed circuit board and the structure of the transmission signal between LSIs, the transmission circuit model becomes very large. One or two days are required to perform one analysis.

  Here, for example, in order to obtain the worst value of the delay fluctuation amount of the transmission signal between LSIs due to power supply noise, the timing of the signal input to the output circuit of the LSI is shifted with respect to the power supply noise, and analysis is performed multiple times. However, in this transmission signal waveform analysis method, there is a problem in that a simulation that takes 1 to 2 days per analysis must be executed a plurality of times, which requires a lot of time.

  Further, since this transmission signal waveform analysis method is mainly intended to analyze power supply noise, signal wiring between LSIs is roughly modeled. For this reason, there is a problem that the influence (transmission signal waveform quality deterioration amount, transmission signal delay fluctuation amount) that the power supply noise has on the inter-LSI transmission signal cannot be analyzed with high accuracy. If the inter-LSI signal wiring is modeled in detail, the analysis accuracy can be improved. However, in this case, there is a problem that the simulation time is increased.

In this way, in the conventional transmission signal waveform analysis method that models the power supply structure of each part of the LSI die, package, and printed circuit board and the structure of the transmission signal between LSIs, the power supply noise generated inside the LSI is transmitted between the LSIs. Since it is not possible to analyze the effects on signals in a short time and with high accuracy, in the past, not only the power supply noise generated inside the LSI but also various noises were taken into account by allowing the designer to comply with the rule-based design rules. I have done circuit design.
JP 2004-54522 A JP 2000-35984 A Japanese Patent Laid-Open No. 11-45294 JP 2005-31850 A

  However, when a rule-based design rule is used, the design rule can be observed if the operation speed of the transmission circuit is slow. However, if the operation speed is increased, the design rule is uniformly satisfied. It becomes difficult to perform circuit design.

  This is because the rule-based design rules are set in such a way that the normal operation of the circuit can be surely guaranteed if the various rules in which various types of noise occur are considered and the rules are observed. This is because it is a rule, and the design will not converge if it tries to satisfy the rule uniformly. On the other hand, if the design is neglected, there is a problem that a problem is detected at the stage of actual operation after manufacture and a large rework occurs.

  In view of these points, the present invention analyzes the influence of power supply noise generated inside a semiconductor device on a printed circuit board on a transmission signal between semiconductor devices in a short time and with high accuracy, and performs normal operation of the circuit based on the analysis. It is an object of the present invention to provide a transmission signal waveform analysis method and program that can guarantee the design and use design rules with high design easiness.

  The transmission signal waveform analysis method of the present invention is a transmission signal waveform analysis method for analyzing a waveform of a transmission signal output from a semiconductor device on a printed circuit board and transmitted on the printed circuit board, and extracting a power supply noise waveform by simulation And a transmission signal waveform analysis step of analyzing the transmission signal waveform by simulation by inserting the power noise waveform into a transmission signal waveform analysis model modeling only the signal of interest and the power noise inflow path. Is.

  A transmission signal waveform analysis program of the present invention is a transmission signal waveform analysis program for causing a computer to perform waveform analysis of a transmission signal output from a semiconductor device on a printed board and transmitted on the printed circuit board. A power noise analysis step for extracting and a transmission signal waveform analyzing step for analyzing the transmission signal waveform by inserting the power noise waveform into a transmission signal waveform analysis model in which only the signal of interest and the power noise inflow path are modeled. It is to execute.

  According to the present invention, since the transmission signal waveform analysis is performed by inserting the power supply noise waveform into the transmission signal waveform analysis model in which only the signal of interest and the power supply noise inflow path are modeled, the transmission signal between the power supply structure and the semiconductor device is analyzed. Compared to the case where the transmission signal waveform analysis is performed by modeling the structure as a unit, the transmission circuit model is reduced in size, and the effect of power supply noise generated inside the semiconductor device on the transmission signal between the semiconductor devices is analyzed in a short time. And it can be performed with high accuracy. Therefore, the normal operation of the circuit can be ensured on an analysis basis, and design rules with high designability can be used.

  FIG. 1 is a flowchart showing an embodiment of a transmission signal waveform analysis method of the present invention. One embodiment of the transmission signal waveform analysis method of the present invention includes a power supply noise analysis step S1 and a transmission signal waveform analysis step S2.

  Here, the layout information of the LSI die section is referred to as DIE layout information, the layout information of the LSI package section is referred to as PKG layout information, and the layout information of the printed circuit board section is referred to as PCB layout information.

  Also, the power supply noise analysis model of the LSI die section is the power supply noise analysis DIE model, the power supply noise analysis model of the LSI package section is the power supply noise analysis PKG model, and the power supply noise analysis model of the printed circuit board section is the power supply noise analysis model. It is called a PCB model for analysis.

  Further, the power supply noise waveform of the die portion of the LSI is referred to as a DIE power supply noise waveform, the power supply noise waveform of the LSI package portion is referred to as a PKG power supply noise waveform, and the power supply noise waveform of the printed circuit board portion is referred to as a PCB power supply noise waveform.

  In the power noise analysis step S1, first, the power noise analysis DIE model 13 using the DIE layout information 10, the power noise analyzing PKG model 14 using the PKG layout information 11, and the PCB layout information 12 are stored. The used power supply noise analysis PCB model 15 is created (steps P1 to P3).

  Next, a circuit analysis simulation using a circuit analysis simulator is performed for each of the power supply noise analysis DIE model 13, the power supply noise analysis PKG model 14, and the power supply noise analysis PCB model 15, and the DIE section power supply noise waveform 16 and The PKG power noise waveform 17 and the PCB power noise waveform 18 are acquired (step P4).

  In the transmission signal waveform analysis step S2, first, for the transmission signal waveform analysis, the DIE layout information 10, the PKG layout information 11, and the PCB layout information 12 are used to model only the signal of interest and the inflow path of power supply noise to the signal of interest. The model 19 is created (step Q1).

  Next, the DIE section power noise waveform 16, the PKG section power noise waveform 17 and the PCB section power noise waveform 18 are inserted into the transmission signal waveform analysis model 19 to perform a circuit analysis simulation using a circuit analysis simulator, and the transmission signal waveform. As an analysis result, a transmission signal waveform quality degradation amount 20 and a transmission signal delay fluctuation amount 21 are calculated (step Q2).

  FIG. 2 is a waveform diagram for explaining a transmission signal waveform quality deterioration amount. In FIG. 2, reference numerals 23 to 26 denote input signal waveforms of the transmission signal receiving side LSI, reference numeral 23 denotes a power source having no power noise, so-called H level signal waveform under an ideal power source, and reference numeral 24 denotes an inside of the transmission signal transmitting side LSI. The H level signal waveform affected by the generated power supply noise, 25 is the L level signal waveform under the ideal power supply, 26 is the L level signal waveform affected by the power supply noise generated inside the transmission signal transmission side LSI, ΔV1 .About..DELTA.V4 indicates the amount of transmission signal waveform quality degradation due to power supply noise.

  That is, in this example, the transmission signal waveform quality degradation amount is due to the influence of the power supply noise generated inside the transmission signal transmission side LSI when the H level and the L level of the input signal of the transmission signal reception side LSI under the ideal power supply respectively. It is the amount of change when it fluctuates.

  FIG. 3 is a waveform diagram for explaining the transmission signal delay variation. In FIG. 3, 28 is an input signal of the output circuit of the transmission signal transmission side LSI, 29 and 30 are input signals of the input circuit of the transmission signal reception side LSI, 29 is an input signal under an ideal power source, and 30 is a transmission signal. An input signal affected by power supply noise generated in the transmission side LSI, T is a delay time of a transmission signal under an ideal power supply, and ΔT is a transmission signal delay fluctuation amount due to power supply noise.

  That is, in this example, the transmission signal delay variation is the delay time of the transmission signal from the input terminal of the transmission signal transmission side LSI under the ideal power source to the input terminal of the transmission signal reception side LSI. This is the amount of fluctuation when it fluctuates due to power supply noise generated inside the transmission signal transmission side LSI.

  FIG. 4 is a conceptual diagram of an LSI-mounted printed circuit board subject to transmission signal waveform analysis and a power supply noise analysis model. In FIG. 4, 33 is an LSI mounting printed circuit board, and 34 is a power supply noise analysis model.

  In the LSI mounting printed circuit board 33, 35 is a printed circuit board, 36 is a signal wiring, 38 is a VDE (for example, 3.3V) power wiring, 39 is a VDD (for example 1.0V) power wiring, and 40 is VSS (0V). ) Power supply wirings 41, 42 and 43 are insulating layers.

  Further, 44 is a transmission signal transmission side LSI, and 45 is a transmission signal reception side LSI that receives a transmission signal transmitted by the transmission signal transmission side LSI 44. In the transmission signal transmitting side LSI 44, 46 is a die, 47 is a package, 48 is a bonding wire, and 49 is a lead frame.

  In this example, the power supply noise analysis model 34 includes a power supply noise analysis DIE model 13, a power supply noise analysis PKG model 14, and a power supply noise analysis PCB model 15.

  In the power supply noise analysis PCB model 15, 50 is a signal wiring model, 51 is a model of the transmission signal receiving side LSI 45, and the transmission signal receiving side LSI 45 is modeled by an input capacitance C. Note that 52 indicates a part of the VDE power supply wiring model, 53 indicates a part of the VDD power supply wiring model, and 54 indicates a part of the VSS power supply wiring model.

  FIG. 5 is a diagram for explaining the power supply noise analysis DIE model 13. In FIG. 5, 56 is a VDE power supply wiring layer, 57 is a VDD power supply wiring layer, 58 is a VSS power supply wiring layer, and the DIE model 13 for power supply noise analysis includes a core logic circuit model obtained by modeling a core logic circuit, an I / O An I / O circuit model obtained by modeling an O circuit is included.

  Reference numeral 59 denotes one of the core logic circuit models. That is, the core logic circuit unit is modeled with a structure called a power unit (hereinafter referred to as PU). This is a technique of dividing the core logic circuit section into small regions (PU) and expressing the electrical characteristics by a spatial distribution of PU units.

  This method has a great merit that the whole image of the spatial distribution of power supply noise can be expressed with a small number of elements. The PU size is determined by the trade-off between the required spatial resolution and computer resources. Typically, a rectangle having a side of about 100 to 200 μm is used.

  The PU has a structure in which four types of elements, an inductance L, a resistance R, a capacitance C, and a current I, are coupled in a grid pattern for each power source type. The inductance L and the resistance R represent the in-plane distribution of the power supply wiring. In general, the size of the PU is usually coarser than that of the actual power supply wiring, but it is represented by an LR value obtained by synthesizing all the power supply wirings in the PU.

  The capacitance C expresses the capacitance distribution in the core logic circuit section. The main components of the capacitor C are a power supply wiring, a capacitor cell, a standard cell, a macro capacitor, and a well capacitance of a silicon substrate. The capacitor C is obtained by adding these capacitors. The current I represents the in-plane distribution of current consumption in the core logic circuit section and the change over time, and is a combination of all standard cells and macro currents in the PU.

  Reference numeral 60 denotes one of the I / O circuit models, and reference numeral 61 denotes an I / O cell. In this example, for the I / O circuit unit, LSI signals and power sources are modeled separately for each pin. The net list of the I / O circuit section is insufficient in accuracy with a model such as IBIS (IO Buffer Information Specification) normally used in printed circuit board design, and it is preferable to use a net list including transistors. is there. The I / O cell includes an input cell, an output cell, and an input / output cell.

  FIG. 6 is a diagram for explaining the power supply noise analysis PKG model 14. The power supply noise analysis PKG model 14 can use a net list created by a commercially available electrical characteristic extraction tool. However, when the circuit scale becomes large, it can be modeled as shown in FIG. it can.

  In this example, a bonding wire, a lead frame signal wiring, and various power supply wirings of the lead frame are modeled, 62 is a bonding wire model, 63 is a lead frame signal wiring model, and 64 is a lead frame power supply. The wiring model is shown.

  The bonding wire is modeled by a ladder circuit of an inductance L, a resistor R, and a capacitor C for both the signal wiring and various power supply wirings, and the capacitor C is connected to the power supply wiring model directly below. The signal wiring of the lead frame is modeled by a ladder circuit of an inductance L, a resistance R, and a capacitance C, and the capacitance C is connected to a power supply wiring model directly below.

  The lead frame power supply wiring having a plane structure is divided into meshes, and each mesh is modeled by a two-dimensional ladder circuit of an inductance L, a resistance R, and a capacitance C. A capacitor C expresses a parasitic capacitance between the power supply wirings.

  For the LRC values of the bonding wire model 62, the lead frame signal wiring model 63, and the power supply wiring model 64, a commercially available electrical characteristic extraction tool is used to extract the LRC value on a unit scale. Assign to LRC.

  FIG. 7 is a diagram for explaining the power supply noise analysis PCB model 15. In FIG. 7, 66 is a bypass capacitor and 67 is an OBP (On Board Power Supply). In this example, the printed circuit board 35 includes a signal wiring 36, various power supply wirings 38 to 40, a bypass capacitor 66, an OBP 67, and a transmission signal receiving side. The LSI 45 is modeled, 68 is a signal wiring model, 69 is a power supply wiring model, 70 is a bypass capacitor model, and 71 is an OBP model.

  The signal wiring 36 is modeled by a ladder circuit of an inductance L, a resistance R, and a capacitor C, and the capacitor C is connected to a power supply wiring model directly below. The power supply wirings 38 to 40 are modeled by a two-dimensional ladder circuit having an inductance L, a resistance R, and a capacitance C by dividing a plane into polygonal meshes. This realizes high-speed and high-precision analysis.

  The bypass capacitor 66 models not only the capacitance C but also ESR (Equivalent Series Resistance) and ESL (Equivalent Series Inductance). Thereby, the frequency characteristic of the bypass capacitor 66 can be expressed accurately. The OBP 67 can be modeled as an ideal power supply, but can also have frequency characteristics.

  FIG. 8 is a diagram for explaining the transmission signal waveform analysis model 19. In the transmission signal waveform analysis model 19, 74 is a transmission signal waveform analysis model for the die 46 of the transmission signal transmission side LSI 44 (hereinafter referred to as a DIE model for transmission signal waveform analysis), and 75 is a package 47 of the transmission signal transmission side LSI 44. A transmission signal waveform analysis model (hereinafter referred to as a transmission signal waveform analysis PKG model), 76 is a transmission signal waveform analysis model of the printed circuit board 35 (hereinafter referred to as a transmission signal waveform analysis PCB model).

  In the DIE model 74 for analyzing the transmission signal waveform, 77 is an output cell, 78 is an input terminal of the output cell 77, 79 is a power supply noise waveform insertion portion provided corresponding to the VDE power supply wiring, and 80 corresponds to the VDD power supply wiring. A power supply noise waveform insertion unit 81 and a power supply noise waveform insertion unit 81 are provided corresponding to the VSS power supply wiring.

  By inserting the corresponding power supply noise waveform among the power supply noise waveforms 16 extracted in the power supply noise analysis step S1 into the power supply noise waveform inserting sections 79 to 81, a power supply noise inflow path to the transmission signal of interest in the die 46 is formed. Can be reproduced.

  In the transmission signal waveform analysis PKG model 75, reference numeral 82 denotes a bonding wire model, 83 denotes a lead wire signal wiring model, and 84 to 87 denote power supply noise waveform insertion portions. Note that the signal wiring of the lead frame is expressed by a ladder circuit of an inductance L, a resistance R, and a capacitance C.

  By inserting the power noise waveform of the corresponding part of the power noise waveform 17 extracted in the power noise analysis step S1 into the power noise waveform inserting sections 84 to 87, the power noise flows into the transmission signal of interest in the package 47. The route can be reproduced.

  In the transmission signal waveform analysis PCB model 76, 88 is a signal wiring model, 89 is a model of the transmission signal receiving side LSI 45, and 90 to 92 are power supply noise waveform insertion units. The transmission signal receiving side LSI 45 is modeled by a capacity C representing the input capacity.

  By inserting the power noise waveform of the corresponding part of the power noise waveform 18 extracted in the power noise analysis step S1 into the power noise waveform inserting sections 90 to 92, the power noise flows into the transmission signal on the printed circuit board 35. The route can be reproduced.

  FIG. 9 is a waveform diagram for explaining the procedure when the transmission signal waveform quality degradation amount 20 is calculated. FIG. 9A shows a signal and power supply voltage applied to the input terminal of the output circuit of the transmission signal transmission side LSI 44, and FIG. 9B shows an input signal of the transmission signal reception side LSI 45. VDE, VDD, and VSS are the power supply voltages VDE, VDD, and VSS at the die 46.

  When the transmission signal waveform quality degradation amount 20 is calculated, for example, an H level signal 94 is first applied to the input terminal of the output circuit of the transmission signal transmission side LSI 44 as shown in FIG. In this way, for example, as shown in FIG. 9B, the H level signal 95 affected by the power supply noise can be obtained, and as a result, the difference from the H level signal 96 under the ideal power supply is obtained. Transmission signal waveform quality degradation amounts ΔV5 and ΔV6 at a certain H level can be obtained.

  Next, similarly, an L level signal 97 is applied to the input terminal of the output circuit of the transmission signal transmission side LSI 44 as shown in FIG. In this way, for example, as shown in FIG. 9B, the L level signal 98 affected by the power supply noise can be obtained, and thereby the difference from the L level signal 99 under the ideal power supply is obtained. Transmission signal waveform quality degradation amounts ΔV7 and ΔV8 at a certain L level can be obtained.

  FIG. 10 is a waveform diagram for explaining the procedure when the transmission signal delay variation 21 is calculated. 10A shows a signal and power supply voltage applied to the input terminal of the output circuit of the transmission signal transmission side LSI 44, and FIG. 10B shows an input signal of the transmission signal reception side LSI 45.

  When the transmission signal delay variation 21 is calculated, for example, a rising transition signal 100 is given to the input terminal of the output circuit of the transmission signal transmission side LSI 44 as shown in FIG. In this way, for example, as shown in FIG. 10B, the rising transition signal 101 affected by the power supply noise can be obtained as the input signal of the transmission signal receiving side LSI 45. The time difference from the rising transition signal 102 in FIG. 1, that is, the transmission signal delay variation ΔT can be obtained. A falling transition signal may be given to the input terminal of the output circuit of the transmission signal transmission side LSI 44.

  FIG. 11 is a waveform diagram for explaining the procedure for calculating the worst value of the transmission signal delay variation. When calculating the worst value of the transmission signal delay fluctuation amount, the transition timing of the rising transition signal 100 given to the input terminal of the output circuit of the transmission signal transmission side LSI 44 is sufficiently shorter than the fluctuation cycle of the power supply noise waveform. By sweeping, the worst value of the transmission signal delay fluctuation amount can be obtained.

  FIG. 12 is a conceptual diagram of a computer for carrying out one embodiment of the transmission signal waveform analysis method of the present invention. In FIG. 12, reference numeral 200 denotes a CPU (central processing unit), 201 denotes a DRAM (dynamic random access memory) used by the CPU 200, 202 denotes input means, 203 denotes display means, and 204 denotes an HDD (hard disk device). Reference numeral 205 denotes a transmission signal waveform analysis program.

  In addition to the transmission signal waveform analysis program 205, the HDD 204 includes DIE layout information 10, PKG layout information 11, PCB layout information 12, a power noise analysis DIE model 13, a power noise analysis PKG model 14, and a power noise analysis. PCB model 15, DIE section power noise waveform 16, PKG section power noise waveform 17, PCB section power noise waveform 18, transmission signal waveform analysis model 19, transmission signal waveform quality degradation amount 20, transmission signal delay fluctuation amount 21, etc. Also used for.

  In the transmission signal waveform analysis program 205, 206 is a power supply noise analysis DIE model creation program, 207 is a power supply noise analysis PKG model creation program, 208 is a power supply noise analysis PCB model creation program, and 209 is a circuit analysis simulator (circuit analysis program). , 210 is a transmission signal waveform analysis model creation program.

  The power supply noise analysis DIE model creation program 206 is a program for creating the power supply noise analysis DIE model 13 using the DIE layout information 10, and the power supply noise analysis DIE model creation program 206 is used to configure the CPU 200. Step P1 can be executed by functioning as a power supply noise analysis DIE model creation means.

  The power noise analysis PKG model creation program 207 is a program for creating the power noise analysis PKG model 14 using the PKG layout information 11, and the CPU 200 is executed using the power noise analysis PKG model creation program 207. Step P2 can be executed by functioning as a power noise analysis PKG model creation means.

  The power supply noise analysis PCB model creation program 208 is a program for creating the power supply noise analysis PCB model 15 using the PCB layout information 12, and the power supply noise analysis PCB model creation program 208 is used to control the CPU 200. Step P3 can be executed by functioning as a power supply noise analysis PCB model creation means.

  The circuit analysis simulator 209 performs circuit analysis simulation for each of the power supply noise analysis DIE model 13, the power supply noise analysis PKG model 14, and the power supply noise analysis PCB model 15, and the DIE section power supply noise waveform 16 and the PKG section. A program for obtaining a power supply noise waveform 17 and a PCB part power supply noise waveform 18 and performing a circuit analysis simulation on a transmission signal waveform analysis model 19 to obtain a transmission signal waveform quality degradation amount 20 and a transmission signal delay variation 21. It is.

  By using the circuit analysis simulator 209, the CPU 200 can function as a power supply noise waveform calculating unit, so that the step P4 can be executed, and the CPU 200 can calculate the transmission signal waveform quality deterioration amount calculating unit and the transmission signal delay variation calculating unit. By functioning as means, step Q2 can be executed.

  The transmission signal waveform analysis model creation program 210 creates a transmission signal waveform analysis model 19 that models only the inflow path of the signal of interest and power supply noise from the DIE layout information 10, the PKG layout information 11, and the PCB layout information 12. Step Q1 can be executed by causing the CPU 200 to function as a transmission signal waveform analysis model creation means using this transmission signal waveform analysis model creation program 210.

  That is, in one embodiment of the transmission signal waveform analysis method of the present invention, the CPU 200 functions as power supply noise analysis means in the power supply noise analysis step S1, and functions as transmission signal waveform analysis means in the transmission signal waveform analysis step S2. Become.

  As described above, in one embodiment of the transmission signal waveform analysis method of the present invention, the entire process is divided into the power supply noise analysis process S1 and the transmission signal waveform analysis process S2, and in the power supply noise analysis process S1, the DIE layout information 10 and Using the PKG layout information 11 and the PCB layout information 12, the DIE power noise waveform 16, the PKG power noise waveform 17, and the PCB power noise waveform 18 are calculated.

  Then, in the transmission signal waveform analysis step S2, a transmission signal waveform analysis model 19 in which only the signal of interest and the inflow path of power supply noise to the signal of interest are modeled from the DIE layout information 10, the PKG layout information 11, and the PCB layout information 12. The DIE section power supply noise waveform 16, the PKG section power supply noise waveform 17 and the PCB section power supply noise waveform 18 are inserted into the transmission signal waveform analysis model 19, and a circuit analysis simulation is performed by a circuit analysis simulator. It is assumed that the quality degradation amount 20 and the transmission signal delay fluctuation amount 21 are calculated.

  Thus, according to one embodiment of the transmission signal waveform analysis method of the present invention, the DIE unit power noise waveform is added to the transmission signal waveform analysis model 19 in which only the target signal and the power noise inflow path to the target signal are modeled. 16 and PKG power noise waveform 17 and PCB power noise waveform 18 are inserted and the circuit analysis simulation is performed, so that the scale of the model of the circuit to be designed can be reduced.

  Therefore, unlike the conventional example in which the power supply structure of each part of the LSI die, package, and printed circuit board and the structure of the transmission signal between the LSIs are modeled as one unit and the transmission signal waveform analysis is performed, the power supply noise generated inside the LSI is reduced. Analysis of the influence on the inter-LSI transmission signal can be performed in a short time and with high accuracy. As a result, normal operation of the circuit can be ensured on an analysis basis, and design rules with high design easiness can be used.

  Here, when the present invention is arranged, the present invention includes at least the following transmission signal waveform analysis method and transmission signal waveform analysis program.

  (Appendix 1) A transmission signal waveform analysis method for analyzing a waveform of a transmission signal output from a semiconductor device on a printed circuit board and transmitted on the printed circuit board, wherein a power supply noise analysis step extracts a power supply noise waveform by simulation; And a transmission signal waveform analysis step of analyzing the transmission signal waveform by simulation by inserting the power noise waveform into a transmission signal waveform analysis model in which only the signal of interest and the power noise inflow path are modeled Waveform analysis method.

  (Supplementary Note 2) The power source noise analysis step includes the steps of determining the power source noise of the semiconductor device die, the semiconductor device package, and each part of the printed circuit board from the layout information of each part of the printed circuit board. The method according to claim 1, further comprising the steps of: creating an analysis model; and extracting a power supply noise waveform of each part of the printed circuit board and a die of the semiconductor device from the power supply noise analysis model. Transmission signal waveform analysis method.

  (Supplementary Note 3) The transmission signal waveform analysis step includes a step of creating the transmission signal waveform analysis model from layout information of each die of the semiconductor device, a package of the semiconductor device, and each part of the printed circuit board. The transmission signal waveform analysis method according to appendix 1 or 2.

  (Supplementary note 4) The transmission signal waveform analysis method according to supplementary note 1, 2, or 3, wherein the transmission signal waveform analysis in the transmission signal waveform analysis step is to calculate a transmission signal waveform quality degradation amount.

  (Supplementary Note 5) The transmission signal waveform analysis method according to Supplementary Note 1, 2, or 3, wherein the transmission signal waveform analysis in the transmission signal waveform analysis step calculates a transmission signal delay variation.

  (Supplementary Note 6) A step of calculating the worst value of the transmission signal delay variation amount by performing a plurality of analyzes by sweeping the transition timing of the input signal to the output circuit of the semiconductor device with respect to the power supply noise waveform. The transmission signal waveform analysis method according to appendix 5, characterized by comprising:

  (Supplementary note 7) A transmission signal waveform analysis program for causing a computer to execute waveform analysis of a transmission signal output from a semiconductor device on a printed circuit board and transmitted on the printed circuit board, and extracting a power supply noise waveform And causing the computer to execute a transmission signal waveform analysis step of analyzing the transmission signal waveform by inserting the power supply noise waveform into a transmission signal waveform analysis model in which only the signal of interest and the power supply noise inflow path are modeled. Transmission signal waveform analysis program.

  (Supplementary Note 8) The power source noise analyzing step includes power source noise of the semiconductor device die, the semiconductor device package, and each part of the printed circuit board from the layout information of each part of the printed circuit board and the die of the semiconductor device. The method according to claim 7, further comprising the steps of: creating an analysis model; and extracting a power supply noise waveform of each part of the printed circuit board and a die of the semiconductor device from the power supply noise analysis model. Transmission signal waveform analysis program.

  (Supplementary note 9) The transmission signal waveform analysis step includes a step of creating the transmission signal waveform analysis model from layout information of each die of the semiconductor device, a package of the semiconductor device, and each part of the printed circuit board. The transmission signal waveform analysis program according to appendix 7 or 8.

  (Supplementary note 10) The transmission signal waveform analysis program according to supplementary note 7, 8 or 9, wherein the transmission signal waveform analysis in the transmission signal waveform analysis step calculates a transmission signal waveform quality deterioration amount.

  (Supplementary note 11) The transmission signal waveform analysis program according to supplementary note 7, 8 or 9, wherein the transmission signal waveform analysis in the transmission signal waveform analysis step calculates a transmission signal delay variation.

  (Supplementary Note 12) The worst-case value of the transmission signal delay variation amount is calculated by performing a plurality of analyzes by sweeping the transition timing of the input signal to the output circuit of the semiconductor device with respect to the power supply noise waveform. The transmission signal waveform analysis program according to appendix 11, which is characterized by

It is a flowchart which shows one Embodiment of the transmission signal waveform analysis method of this invention. It is a wave form diagram for demonstrating the transmission signal waveform quality degradation amount computed with one Embodiment of the transmission signal waveform analysis method of this invention. It is a wave form diagram for demonstrating the transmission signal delay fluctuation amount calculated by one Embodiment of the transmission signal waveform analysis method of this invention. It is a conceptual diagram of an LSI mounting printed circuit board subject to transmission signal waveform analysis and a model for power supply noise analysis. It is a figure for demonstrating the DIE model for power supply noise analysis created with one Embodiment of the transmission signal waveform analysis method of this invention. It is a figure for demonstrating the PKG model for power supply noise analysis created with one Embodiment of the transmission signal waveform analysis method of this invention. It is a figure for demonstrating the PCB model for power supply noise analysis produced with one Embodiment of the transmission signal waveform analysis method of this invention. It is a figure for demonstrating the model for transmission signal waveform analysis created with one Embodiment of the transmission signal waveform analysis method of this invention. It is a wave form diagram for demonstrating the procedure in the case of calculating the transmission signal waveform quality degradation amount by one Embodiment of the transmission signal waveform analysis method of this invention. It is a wave form diagram for demonstrating the procedure in the case of calculating the transmission signal delay variation | change_quantity in one Embodiment of the transmission signal waveform analysis method of this invention. It is a wave form diagram for demonstrating the procedure in the case of calculating the worst value of the transmission signal delay variation | change_quantity in one Embodiment of the transmission signal waveform analysis method of this invention. It is a conceptual diagram of the computer for enforcing one Embodiment of the transmission signal waveform analysis method of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... DIE layout information 11 ... PKG layout information 12 ... PCB layout information 13 ... DIE model for power supply noise analysis 14 ... PKG model for power supply noise analysis 15 ... PCB model for power supply noise analysis 16 ... DIE part power supply noise waveform 17 ... PKG part Power supply noise waveform 18 ... PCB power supply noise waveform 19 ... Transmission signal waveform analysis model 20 ... Transmission signal waveform quality degradation amount information 21 ... Transmission signal delay fluctuation amount 200 ... CPU
201 ... DRAM
202 ... Input means 203 ... Display means 204 ... HDD
205 ... Transmission signal waveform analysis program 206 ... Power supply noise analysis DIE model creation program 207 ... Power supply noise analysis PKG model creation program 208 ... Power supply noise analysis PCB model creation program 209 ... Circuit analysis simulator (circuit analysis program)
210 ... Transmission signal waveform analysis model creation program

Claims (4)

A transmission signal waveform analysis method for analyzing a waveform of a transmission signal output from a semiconductor device on a printed circuit board and transmitted on the printed circuit board,
A central processing unit included in the computer is used to analyze power source noise of each die of the semiconductor device, the package of the semiconductor device, and each part of the printed circuit board from layout information of the die of the semiconductor device, the package of the semiconductor device, and each part of the printed circuit board. create a model, from the power supply noise analysis model, die of the semiconductor device, a power supply noise analysis step to extract the package, and power supply noise waveform of the printed circuit board each unit of the semiconductor device,
Transmission the central processing unit in which the computer has found by inserting the power supply noise waveform only the modeled transmission signal waveform analysis model power supply noise flowing path to the attention signal and the focus signal performs heat transmission signal waveform analysis A transmission signal waveform analysis method comprising a signal waveform analysis step. 2. The transmission signal waveform analysis method according to claim 1 , wherein the transmission signal waveform analysis in the transmission signal waveform analysis step calculates a transmission signal delay variation. The central processing unit of the computer sweeps the transition timing of the input signal to the output circuit of the semiconductor device with respect to the power supply noise waveform and executes the analysis a plurality of times, thereby causing the worst transmission signal delay variation amount. The transmission signal waveform analysis method according to claim 2, further comprising a step of calculating a value. A transmission signal waveform analysis program for causing a computer to perform waveform analysis of a transmission signal output from a semiconductor device on a printed circuit board and transmitted on the printed circuit board,
From the layout information of the semiconductor device die, the semiconductor device package, and each part of the printed circuit board, a power noise analysis model of the semiconductor device die, the semiconductor device package, and each part of the printed circuit board is created, and the power noise A power supply noise analysis step for extracting power supply noise waveforms of the die of the semiconductor device, the package of the semiconductor device and each part of the printed circuit board from the analysis model ;
Causing the computer to execute a transmission signal waveform analysis step of analyzing the transmission signal waveform by inserting the power noise waveform into a transmission signal waveform analysis model that models only the signal of interest and the power noise inflow path to the signal of interest. Transmission signal waveform analysis program characterized by

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