JP2001222573A - Power source model for semiconductor integrated circuit for emi simulation and designing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily and exactly perform EMI simulation, which is conventionally difficult, from a printed circuit board power source system. SOLUTION: The inside of an LSI is replaced with one of inverter circuits 3 and 4, output terminal 77, gate circuit 2 composed of wiring capacitance between first and second power sources 7 and 8, and equivalent internal capacitors 9-11 having serial resistors. In such a model, since the number of transistors is remarkably reduced in comparison with reality, the EMI simulation can be performed with reduced calculation time and without damaging exactness. Besides, since the detailed data of transistors are not required for this model, an LSI maker can provide the model to a user without leaking confidential information such as circuit information inside the LSI to the others.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply model of a semiconductor integrated circuit for EMI simulation and a method of designing the same, and more particularly, to an LSI (Large) describing a transistor.
The present invention relates to a power supply model and a design method thereof.

[0002]

2. Description of the Related Art An example of this kind of conventional technology is "changeable board design, pre-verification becomes essential in the advent of the 100 MHz era".
(Nikkei Electronics) 1998, 4-6 Publication date: April 6, 1998: p143, 111, FIG. 9 (hereinafter referred to as reference 1), and “Models of Int.
EGRated Circuits for EMIB
ehavioral Simulation ”, IE
C TC93 NewWork Item Propo
sal, 1997.5.515 Date of issue: 1995
May 15, p4, FIG. (3) (hereinafter referred to as Document 2). In addition, JP-A-10-548
No. 65 (hereinafter referred to as Reference 3) and JP-A-11-1
Japanese Patent Application Laid-Open No. 20214 (hereinafter referred to as Document 4) discloses a similar technique.

In order to suppress electromagnetic wave radiation noise generated from electronic equipment, it is effective and economical to take measures at the design stage. Therefore, many designers consider EMI (Electro-Magnetic Int.)
Introducing a simulator and taking countermeasures.

[0004]

However, the reality is that the simulation results do not always agree with the actually measured values. One of the causes is that many simulators do not analyze the power supply system. As an example, there is an IBIS model as a representative of a device model currently used in an EMI simulator. What is IBIS?
O BufferInformation Speci
Input buffer
This is a model of the output buffer. SPICE
In an EMI simulator based on (circuit simulator), a current is obtained by incorporating such a circuit element model, and a radiation electromagnetic field is calculated from the current.

As can be seen from this, the existing LS
The EMI simulation model of I mainly considers analysis of a signal system of an LSI, and does not consider an analysis method using other terminals such as a power supply terminal and a GND terminal.

However, actually, the power supply current of the LSI is I
Not only the / O buffer, but also all internal circuits not directly related to the signal terminals are connected and contain many high-frequency components, so that the radiated electromagnetic field due to the power supply current cannot be ignored. Therefore, in order to analyze EMI of an electronic device, it is indispensable to analyze a power supply current of a printed circuit board and analyze a radiation electromagnetic field generated by the power supply current.

Here, a problem arises. When analyzing EMI on a printed circuit board, a model of an LSI mounted on the printed circuit board is required in addition to a transmission line model of the printed circuit board wiring. As a format of the LSI model, there are a transistor description format and an operation level description format. The transistor description format is an accurate description of the circuit configuration inside the LSI using a transistor model and a model of wiring resistance and capacitance, and is generally used for LSI design. The behavioral level description format is a simplified version of the transistor description format, and is generally used for noise verification of a printed circuit board (the above-described IBIS model is also the behavioral level description format). Let us consider the case of analyzing the radiated electromagnetic field from the power supply using these two models.

First, when a power supply current is obtained in a transistor description format, it is necessary to analyze all circuits inside the LSI, but the circuit scale inside the LSI is enormous. FIG. 5 shows a schematic diagram of an equivalent circuit for analysis in a transistor description format. In the figure, reference numeral 38 denotes an EMI simulation model of a semiconductor integrated circuit in a transistor description format;
Denotes a first power supply terminal, 40 denotes a second power supply terminal, and 41 denotes a transistor block. As an example, a mask ROM having a relatively small circuit scale has about 5,000 transistors constituting the inside, and an MPU having a large circuit scale has more than one million transistors.

In the conventional analysis of only the signal terminal, an LSI
Can be omitted only for the I / O buffer, but since all the circuits are connected to the power supply terminal, the circuit cannot be omitted. Therefore, E
The amount of calculation of the MI simulator is enormous compared to that of the signal system, and it is difficult or impossible to perform analysis. Further, the user needs to receive the LSI model from the LSI maker, but the transistor description model contains a lot of information that is confidential to the LSI maker, such as the transistor structure and manufacturing method or the circuit configuration inside the LSI. Therefore, LSI manufacturers cannot provide transistor description models to users of other companies.

[0010] For analysis using a behavioral level description format model, the following model is currently proposed. FIG. 6 shows an operation level description model formed by a current source and an impedance connected in parallel to the current source.
5, the same components as those in FIG. 5 are denoted by the same reference numerals, and the description thereof will be omitted. Reference numeral 42 denotes a power supply model for EMI simulation of a semiconductor integrated circuit in a behavior level description format,
3 is a current source, 44 is the impedance of the circuit, and 45 is the current of the current source. The power supply current waveform of the LSI is reproduced from the current source. However, there is a problem with this method.

The internal impedance of a power supply terminal of an LSI originally changes depending on the input state of a signal and the voltage of the power supply terminal. This change in resistance causes a complicated current waveform to flow. The power supply current waveform flowing from the current source is obtained by measuring the current flowing through the power supply terminal by measuring the actual circuit.
It is obtained by converting the current waveform. When performing the analysis in the frequency domain, the conversion method is not so difficult because the impedance becomes constant if the frequency is constant.

However, when performing an analysis in the time domain, the impedance does not fluctuate with time and thus does not become a constant value, the conversion method is very complicated, and it is very difficult to obtain the current waveform of the current source in the time domain. It is.

When the current waveform is actually measured and the current waveform of the LSI is obtained from the result, the information of the impedance of the circuit in the DC power supply is already included in the current waveform. Since the model also has an impedance in the circuit, the effect of the impedance is seen twice, and an accurate LSI current waveform cannot be obtained.

When it is desired to obtain a truly accurate power supply terminal current of a circuit, a simulation using a transistor description model as shown in FIG. 5 described above may be performed.
It is not realistic because the above-mentioned problem still occurs.

The above problems can be summarized as follows. The first problem is that the conventional transistor description format L
With the SI model, it is impossible or very difficult to perform EMI simulation of the power supply system. The reason is that the circuit scale inside the LSI is enormous, and it is difficult to perform a simulation without a circuit as in the analysis of signal terminals.

The second problem is that EMI simulation in the time domain is extremely difficult with the conventional LSI model of the behavior level description format. The reason is that it is very difficult to represent the current waveform of the current source of the LSI model in the behavioral level description format because the impedance inside the circuit is not constant in the time domain.

A third problem is that in the conventional EMI simulation, analysis in an accurate state cannot be performed. The reason is that when the LSI is actually operating, only a part of the LSI is operating, and only the operating part is considered for analysis.

An object of the present invention is to provide a power supply model of a semiconductor integrated circuit for EMI simulation and a method of designing the power supply model for easily and accurately performing an EMI simulation from a power supply system of a printed circuit board, which has been difficult in the past. It is in.

[0019]

According to the present invention, there is provided a power supply model of a semiconductor integrated circuit for EMI simulation for a printed circuit board and a semiconductor integrated circuit, wherein the power supply model has a power supply. It is characterized by including an inverter unit to be supplied, and an equivalent internal capacitance unit connected between the output of the inverter unit and the power supply.

According to another aspect of the present invention, there is provided a method of designing a power supply model of a semiconductor integrated circuit for EMI simulation for a printed circuit board and a semiconductor integrated circuit, wherein the power supply model is a semiconductor device to be subjected to the EMI simulation. It is designed based on all circuit connection information of the integrated circuit.

EMI of the Invention and Other Inventions According to the Invention
The simulation model is expressed in a transistor description format, and simulates a radiation electromagnetic field generated on a printed circuit board. In this transistor description type LSI power supply model, the number of constituent transistors is much smaller than the actual one. The EMI simulator uses this model to determine the power supply current flowing on the printed circuit board wiring. This model is created by extracting the operating part from the netlist of the actual LSI and reducing the number of transistors as described above. Also, the remaining non-operating parts are simplified, and an LSI power supply model is created as a whole.

By modeling the LSI power supply system with the equivalent capacitance of the inverter circuit, the calculation load of the EMI simulator is reduced as compared with the conventional transistor description model, and the power supply current analysis can be performed more easily. I can do it. In addition, by considering the non-operating part on the EMI simulation, the behavior becomes closer to the actual operation of the LSI, so that a more accurate power supply current of the LSI can be obtained. Further, since detailed information on the circuit configuration and device structure inside the LSI is not included in the model, the LSI maker can present it to the user.

[0023]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows a power supply model for EMI simulation of a semiconductor integrated circuit based on claim 2 (first embodiment). Referring to FIG. 1, a simulation model includes an operation signal source (clock signal source) 1, an inverter circuit 2, a P-channel transistor 3, an N-channel transistor 4, a first load capacitance 5, and a second load capacitance. 6, a first power supply 7, a second power supply 8, a first equivalent internal capacitance 9, a second equivalent internal capacitance 10, a third equivalent internal capacitance 11, and a second equivalent internal capacitance. (Capacity part) 1
2, a series resistance 13 of a second equivalent internal capacitance, a series resistance 14 of a third equivalent internal capacitance, a third equivalent internal capacitance (capacitance part) 15, and a series resistance 16 of a first equivalent internal capacitance.
And a power supply model 18 for EMI simulation of the semiconductor integrated circuit according to the second aspect.

The P-channel transistor 3 connected between the first power supply 7 and the output terminal 77 and the wiring capacitance, and the N-channel transistor 4 connected between the second power supply 8 and the output terminal 77 and the wiring capacitance are combined. It is called a gate circuit.
Reference numeral 1 denotes a signal source which continuously sends a signal of a constant frequency. A portion operated by the signal is replaced by a single gate circuit shown in 2, and a non-operating portion is replaced by a second one of 10 and 11.
It is represented by the third equivalent internal capacitance. Further, the first equivalent internal capacitance of 9 is a constant value which is determined at the stage of designing the LSI and is not related to the internal operation state.

FIG. 2 shows a power supply model for simulation based on claim 3 (second embodiment). FIG.
The only difference is that the gate circuit has two stages.
That is, instead of the P-channel transistor 3, the N-channel transistor 4, the first load capacitance 5, the second load capacitance 6, and the output terminal 77 in FIG. Channel transistors 21 and 26, first load capacitors 22 and 27, second load capacitors 23 and 28, first output terminal 78 and output terminal 79
And

In FIGS. 1 and 2, the gate electrode width, the gate electrode capacitance, and the wiring capacitance of the transistor in the gate circuit are halved, and the ON resistance of the transistor is doubled, so that the average current in a certain time is equalized. Has become.

FIG. 3 shows a simulation model in the case where there are a plurality of power supply systems based on claim 4 (third embodiment). When there are a plurality of power supply systems such as 33 and 34 and 35 and 36, each of the different parts of the power supply system such as 31 and 32 is replaced with a model as shown in FIG. 1 or FIG.

FIG. 4 shows a simulation model when the inside of the LSI is divided into a plurality of blocks according to the fifth and sixth aspects (fourth embodiment). FIG. 1 or FIG. 2 for each block divided by the arrangement information or the operation timing.
The configuration is replaced with a model like That is,
The inside of the semiconductor integrated circuit is divided into a plurality of groups with gate circuits within a certain signal propagation delay time as the same timing group, and each group has an inverter circuit and a load capacitance. Incidentally, reference numeral 37 in FIG. 4 denotes a power supply model for EMI simulation of the semiconductor integrated circuit divided into blocks.

Next, a method of designing the power supply model will be described. FIGS. 7 to 21 show a method of designing a model according to claims 2 and 3 corresponding to claims 8 to 22, respectively.

FIGS. 7 and 12 show that all gate circuits operating at the operating frequency or the clock frequency are extracted from all the circuit information of the LSI (S1 in FIG. 7 and S2 in FIG. 12).
6), a method in which an operating part is configured by one (FIG. 7) or two (FIG. 12) gate circuits based on the information (S2 to S4 in FIG. 7 and S27 to S29 in FIG. 12). It can be seen that the model of claim 3 has half the gate width and load capacity of the transistor as compared to the model of claim 2. This method is referred to as pattern 1.

FIGS. 8 and 13 show the number of gate circuits operating at the operating frequency or the clock frequency from all circuit information of the LSI (S5 in FIG. 8 and S3 in FIG. 13).
0), and furthermore, the operating part is set to 1 together with the information on the average value of the gate width, gate capacitance, and wiring capacitance of the transistor.
This is a method using one (FIG. 8) or two (FIG. 13) gate circuits (S6 to S8 in FIG. 8 and S31 to S in FIG. 13).
33). In this case as well, it can be seen that the gate width and the load capacitance of the transistor in the model of claim 3 are half those of the model of claim 2. This method is referred to as pattern 2.

FIGS. 9 and 14 show the counting of the number of all gate circuits from all the circuit information of the LSI (S9 of FIG. 9 and FIG. 14).
S34), the information of the average value of the gate width, the gate capacitance, and the wiring capacitance of the transistor, and the information of the average operation rate are combined, and one (FIG. 9) or two (FIG. 1) operating portions are operated.
This is a method configured by the gate circuit of 4) (S10 in FIG. 9).
To S13 and S35 to S38 in FIG. 14). In this case as well, it can be seen that the gate width and the load capacitance of the transistor in the model of claim 3 are half those of the model of claim 2. This method is referred to as pattern 3.

FIGS. 10 and 15 show that the number of all gate circuits is counted from the entire circuit information of the LSI (S14 in FIG. 10 and S39 in FIG. 15), and further, the average of the gate width, gate capacitance, and wiring capacitance of the transistor. In this method, the operating part is configured by one (FIG. 10) or two (FIG. 15) gate circuits together with the value information and the maximum operation rate information (S15 to S18 in FIG. 9 and FIG. 9). 15 S40 to S43). In this case as well, it can be seen that the gate width and the load capacitance of the transistor in the model of claim 3 are half those of the model of claim 2. This method is referred to as pattern 4.

FIGS. 11 and 16 show the number of all gate circuits counted from all circuit information of the LSI (S19 in FIG. 11 and S44 in FIG. 16).
In addition, information on the average value of the gate width, gate capacitance, and wiring capacitance of the transistor, information on the average current of the entire circuit, and the result of deriving the average current of the basic circuit using the average value transistor and the wiring capacitance At the same time, the operating part is configured by one (FIG. 11) or two (FIG. 16) gate circuits (S20 to S25 in FIG. 11 and S45 to S50 in FIG. 16). In this case as well, it can be seen that the gate width and the load capacitance of the transistor in the model of claim 3 are half those of the model of claim 2. This method is referred to as pattern 5.

FIG. 17 shows a method in which the portion operating in pattern 1 is obtained and the remaining portion is replaced with second and third equivalent internal capacitances (S51 to S54 in FIG. 17). When a portion that operates using pattern 1 is configured, the remaining portion is obtained by this method, and hence the pattern 1 includes a method of replacing the remaining portion with an equivalent internal capacitance in the future.

FIG. 18 shows a method of replacing the remaining portion obtained from the portion operating in pattern 2 with the second and third equivalent internal capacitances (S55 to S58 in FIG. 18). As information, besides the information used in pattern 2
An average value of the N resistance is required. When a part that operates using pattern 2 is configured, the remaining part is obtained by this method. Therefore, in the future, the remaining part will be referred to as pattern 2 including a method of replacing the remaining part with an equivalent internal capacitance.

FIG. 19 shows a method in which a portion operating in pattern 3 is obtained and the remaining portion is replaced with second and third equivalent internal capacities (S59 to S64 in FIG. 18). As information, besides the information used in pattern 3, the O
An average value of the N resistance is required. When a part that operates using pattern 3 is configured, the remaining part is obtained by this method. Therefore, in the future, the remaining part will be referred to as pattern 3 including a method of replacing the remaining part with an equivalent internal capacitance.

FIG. 20 shows a method in which the portion operating in pattern 4 is obtained and the remaining portion is replaced with second and third equivalent internal capacitances (S65 to S70 in FIG. 20). As information, besides the information used in pattern 4
An average value of the N resistance is required. When a part that operates using pattern 4 is configured, the remaining part is obtained by this method. Therefore, in the future, the remaining part will be referred to as pattern 4 including a method of replacing it with an equivalent internal capacitance.

FIG. 21 shows a method in which the portion operating in pattern 5 is obtained and the remaining portion is replaced with second and third equivalent internal capacitances (S71 to S77 in FIG. 21). As information, besides the information used in pattern 5, the O
An average value of the N resistance is required. When a portion operating using pattern 5 is configured, the remaining portion is obtained by this method, and hence the pattern 5 will be used in the future including a method of replacing the remaining portion with an equivalent internal capacitance.

Further, there is proposed a support system for designing a power supply model for EMI simulation of a semiconductor integrated circuit to which the design method from pattern 1 to pattern 5 is applied (claim 23). Further, an apparatus for performing EMI simulation using the models of claims 2 to 6 is proposed (claim 24).

Next, another embodiment of the present invention will be described. 22 and 23 show examples of simulation using a power supply model for EMI simulation of a semiconductor integrated circuit actually designed.

FIG. 22 shows a printed circuit board (Print
It is an example of simulation of ed Circuit Board (PCB) (fifth embodiment). Lead frames such as 47 and 50, and 53 and 5
A transmission line such as 4 and a decoupling capacitor 55 for suppressing EMI such as 55 are connected, and an EMI simulation close to an actual PCB can be performed. 46 is the EMI of the semiconductor integrated circuit.
A power supply model for simulation, 48 is the inductance of the lead frame on the first power supply side, 49 is the resistance of the lead frame on the first power supply side, 51 is the inductance of the lead frame on the second power supply side, and 52 is the second lead frame. The resistance of the lead frame on the power supply side, 56 is the equivalent series inductance of the decoupling capacitor, 57 is the equivalent capacitance of the decoupling capacitor, and 58 is the equivalent series resistance of the decoupling capacitor.

FIG. 23 shows an example of a simulation when a capacitance such as 61 is placed inside the LSI. This capacitance is created by using a gap in the LSI, and has the effect of suppressing EMI. Such a configuration of the LSI can also be performed using the proposed model. Reference numeral 30 denotes a semiconductor integrated circuit (LSI); 59, a capacitance loaded in the LSI; 60, an equivalent series inductance of the capacitance loaded in the LSI; and 62, an equivalent series resistance of the capacitance loaded in the LSI.

Next, a sixth embodiment of the present invention will be described with reference to the drawings. Referring to FIG.
A processing device 64 including a PU 65 and a storage device 66, an output device 70, and a database 63 are provided. Further, the device type and element connection information 68 of the power supply model shown in FIG. 1 or FIG. (Hereinafter, referred to as a model generation program) for realizing the flow chart 6
9 is provided. This recording medium 67
May be a magnetic disk, a semiconductor memory, a CD-ROM, or another recording medium. The database 63 stores all circuit connection information of the semiconductor integrated circuits shown in FIGS.

The model generation program is read from the recording medium 67 into the processing device 64, and controls the operation of the processing device 64. For example, when the process illustrated in FIG. 7 is executed, data such as the gate width and the gate capacitance of the gate circuit operating at the operating frequency is extracted from the database 63, and information of the extracted circuit is stored in the storage device 66. Then, the stored information of the circuit is sequentially read out WP, CP, CL1, W
N, CN, and CL2 are calculated and stored in the storage device 66,
Next, a first load capacity and a second load capacity are calculated. Then, the calculation result is output from the output device 70. This output contains all the information necessary to create the inverter section of the power supply model shown in FIG. 8 to 11 can be similarly performed.

Similarly, the processing shown in FIGS. 12 to 16 is similarly performed, so that the output device 70 outputs data including all the information necessary for creating the inverter unit of the power supply model shown in FIG. be able to.

Similarly, the processing shown in FIGS. 17 to 21 is similarly performed, so that the output device 70 can output the second equivalent internal capacity and the third equivalent internal capacity of the power supply model shown in FIG. 1 or FIG. It is possible to output data including all information necessary for creating the capacity.

The first equivalent internal capacitance is a numerical value that can be obtained from the arrangement shape information of the N-type well instead of the information on the entire circuit connection of the semiconductor integrated circuit.

Therefore, by performing the above processing, all the information necessary for creating the power supply model shown in FIG. 1 or FIG. 2 can be obtained.

The program recorded on the recording medium is not only a model generation program but also an EMI simulation program to be described later, and by executing the program, a current distribution or an electromagnetic field on the printed circuit board is obtained. It is also possible to output a distribution.

Whether the description of FIG. 1 or FIG. 2 is used as the power supply model, and FIGS.
17 to 21 and the flow to be used can be selected.

Next, a seventh embodiment of the present invention will be described with reference to the drawings. FIG. 25 shows an EMI simulation apparatus for a printed circuit board using the power supply model shown in FIG. 1 or FIG. Here, power supply model data 71 output to the output device 70 as input data,
The circuit constant value of the element on the printed circuit board and the data 72 of the connection information are stored in a circuit analysis simulator (Simula).
Tion Program with Integra
ted Circuit Emphasis: SPIC
E) By inputting to 73, the current distribution 74 on the printed circuit board can be obtained. By inputting the obtained current distribution 74 to the electromagnetic field analysis simulator 75, the electromagnetic field distribution 76 can be output.

The simulator used this time is a package software called RADIUS-WB PACKAGE of Applied Simulation Technology (APSIM). In this package, A for circuit analysis
There is a tool called psimSPICE, which corresponds to the circuit analysis simulator 73, and can determine the current distribution on the printed circuit board. In this package, R
There is a tool called ADIA, which is compatible with the electromagnetic field analysis simulator 75, and can determine the electromagnetic field distribution from the current distribution obtained by ApsimSPICE.

FIG. 26 shows an example of analysis of a printed circuit board using the software and the EMI simulation apparatus shown in FIGS. The data obtained by analyzing the time waveform of the current at an arbitrary point on a certain printed circuit board and performing the Fourier transform to obtain the frequency spectrum are graphs indicated by broken lines in FIG. In the actual printed circuit board, the current flowing at the same point is compared with the value (graph indicated by the solid line) actually measured by the magnetic field probe MP10L (Nippon Electric Vacuum Glass Products), and a very good agreement is obtained. Can be confirmed.

The power supply model for the EMI simulation has been described above.
Not limited to EMI simulation
It can be used for general analysis of power supply current of SI and printed circuit boards. As an example, in an LSI constituted by a CMOS circuit, it is also used to simulate a voltage drop (IR drop) of an LSI power supply system caused by an impedance of wiring and a lead frame in the LSI chip due to an instantaneous simultaneous current change inside the chip. It is possible.

[0057]

According to the present invention, an EMI of a semiconductor integrated circuit for a printed circuit board and a semiconductor integrated circuit is provided.
A power supply model for simulation, wherein the power supply model includes an inverter unit to which power is supplied, and an equivalent internal capacitance unit connected between the output of the inverter unit and the power supply. EMI simulation from the substrate power supply system can be easily and accurately performed.

According to another aspect of the present invention, there is provided a method of designing a power supply model for an EMI simulation of a semiconductor integrated circuit for a printed circuit board and a semiconductor integrated circuit, wherein the power supply model includes the EMI simulation. Since the design is performed based on all circuit connection information of the target semiconductor integrated circuit, it is possible to easily and accurately perform an EMI simulation from a printed circuit board power supply system, which has been difficult in the past.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a power supply model 1 for EMI simulation of a semiconductor integrated circuit according to the present invention.

FIG. 2 is a circuit diagram of a power supply model 2 for EMI simulation of the semiconductor integrated circuit of the present invention.

FIG. 3 shows an EM of a semiconductor integrated circuit when there are a plurality of power supply systems.
It is a block diagram of an I simulation model.

FIG. 4 is a configuration diagram of an EMI simulation model of a semiconductor integrated circuit when the inside is divided into a plurality of blocks.

FIG. 5 is a configuration diagram of a power supply model for EMI simulation of a conventional semiconductor integrated circuit in a transistor description format.

FIG. 6 is a circuit diagram of a power supply model for EMI simulation of a conventional semiconductor integrated circuit in a behavioral level description format.

FIG. 7 is a flowchart illustrating a method 1 of designing a gate circuit portion of a power supply model 1 for EMI simulation of a semiconductor integrated circuit.

FIG. 8 is a flowchart showing a method 2 of designing a gate circuit portion of a power supply model 1 for EMI simulation of a semiconductor integrated circuit.

FIG. 9 is a flowchart illustrating a method 3 of designing a gate circuit portion of a power supply model 1 for EMI simulation of a semiconductor integrated circuit.

FIG. 10 is a flowchart illustrating a design method 4 of a gate circuit portion of a power supply model 1 for EMI simulation of a semiconductor integrated circuit.

FIG. 11 is a flowchart showing a method 5 of designing a gate circuit portion of a power supply model 1 for EMI simulation of a semiconductor integrated circuit.

FIG. 12 is a flowchart illustrating a design method 1 of a gate circuit portion of a power supply model 2 for EMI simulation of a semiconductor integrated circuit.

FIG. 13 is a flowchart illustrating a method 2 of designing a gate circuit portion of a power supply model 2 for EMI simulation of a semiconductor integrated circuit.

FIG. 14 is a flowchart illustrating a method 3 of designing a gate circuit portion of a power supply model 2 for EMI simulation of a semiconductor integrated circuit.

FIG. 15 is a flowchart illustrating a design method 4 of a gate circuit portion of a power supply model 2 for EMI simulation of a semiconductor integrated circuit.

FIG. 16 is a flowchart showing a method 5 of designing a gate circuit portion of a power supply model 2 for EMI simulation of a semiconductor integrated circuit.

FIG. 17 is a flowchart showing a method 1 of designing second and third equivalent internal capacitances of power supply models 1 and 2 for EMI simulation of a semiconductor integrated circuit.

FIG. 18 is a flowchart illustrating a second design method 2 of the second and third equivalent internal capacitances of the power supply models 1 and 2 for EMI simulation of the semiconductor integrated circuit.

FIG. 19 is a flowchart showing a second and third equivalent internal capacitance designing method 3 of the power supply models 1 and 2 for EMI simulation of the semiconductor integrated circuit.

FIG. 20 is a flowchart showing a second and third equivalent internal capacitance designing method 4 of the power supply models 1 and 2 for EMI simulation of the semiconductor integrated circuit.

FIG. 21 is a flowchart showing a second and third equivalent internal capacitance designing method 5 of the power supply models 1 and 2 for EMI simulation of the semiconductor integrated circuit.

FIG. 22 is a circuit diagram illustrating an example of a simulation of a printed circuit board.

FIG. 23 is a circuit diagram illustrating an example of a simulation when a capacitor is inserted in an LSI;

FIG. 24 is an operation diagram of a model generation program.

FIG. 25 is an operation diagram of an EMI simulation program for a printed circuit board.

FIG. 26 is an example of an analysis result of EMI simulation on a printed circuit board.

[Explanation of symbols]

 Reference Signs List 1 operation signal source 2 inverter circuit 3, 20, 25 P-channel transistor 4, 21, 26 N-channel transistor 5, 6 Load capacitance 22, 23 Load capacitance 27, 28 Load capacitance 7, 8 Power supply 9, 10, 11 Equivalent internal capacitance 63 Database 64 Processing device 65 CPU 66 Storage device 67 Recording medium 68, 72 Element type and element connection information 69 Program 70 Output device 71 Power supply model data

Claims (43)

[Claims] 1. A power supply model of a semiconductor integrated circuit for EMI simulation for a printed circuit board and a semiconductor integrated circuit, wherein the power supply model includes an inverter to which power is supplied, an output of the inverter, and the power supply. A power supply model characterized by including an equivalent internal capacitance section connected therebetween. 2. An inverter unit comprising: a signal source corresponding to an operation state of the semiconductor integrated circuit; a P-channel transistor having the signal source as an input and connected between a first power supply and an output terminal; and a second power supply. One inverter circuit including an N-channel transistor connected between output terminals; a first load capacitance connected between an output terminal of the inverter circuit and a first power supply; and an output terminal of the inverter circuit. A second load capacitance connected between the second power supplies, and the equivalent internal capacitance section is a semiconductor integrated circuit having a series resistance connected between the first power supply and the second power supply. A first equivalent internal capacitance consisting of a junction capacitance between an N-type well connected to one power supply and a P-type substrate connected to a second power supply, and a series resistance based on a gate capacitance of a P-channel transistor. 2. The power supply model according to claim 1, wherein the power supply model comprises a second equivalent internal capacitance having a second equivalent internal capacitance and a third equivalent internal capacitance having a series resistance based on a gate capacitance of the N-channel transistor. 3. The inverter circuit according to claim 2, wherein the first load capacitance and the second load capacitance are replaced by a P-channel transistor and a second power supply connected between a first power supply and an output terminal. A first inverter circuit including an N-channel transistor connected between output terminals; a first load capacitance connected between an output terminal of the first inverter circuit and a first power supply; A second load capacitance connected between the output terminal of the inverter circuit and the second power supply, and a P-type power supply connected between the first power supply whose output terminal is connected to the input terminal and the output terminal of the first inverter circuit. A second inverter circuit including a channel transistor, an N-channel transistor connected between a second power supply and an output terminal, and a third inverter connected between an output terminal of the second inverter circuit and the first power supply. Load capacity and before 3. The power supply model according to claim 2, wherein the power supply model comprises an output terminal of the second inverter circuit and a fourth load capacitance connected between the second power supply. 4. A power supply model comprising a plurality of sets of power supply systems, the power supply model comprising the same number of sets as the power supply system. 5. A power supply model, wherein the inside of a semiconductor integrated circuit is divided into a plurality of blocks based on arrangement information, and each block has the model according to claim 1. 6. The semiconductor integrated circuit according to claim 1, wherein a gate circuit within a predetermined signal propagation delay time is divided into a plurality of groups as a same timing group, and each group is divided into a plurality of groups. A power supply model having an inverter circuit and a load capacity. 7. A method for designing a power supply model of a semiconductor integrated circuit for EMI simulation for a printed circuit board and a semiconductor integrated circuit, wherein the power supply model is used for all circuit connection information of the semiconductor integrated circuit to be subjected to EMI simulation. A method for designing a power supply model of a semiconductor integrated circuit for EMI simulation, characterized in that the power supply model is designed based on the above. 8. A total sum of individual gate width dimensions of all P-channel transistors that are performing switching operation at the same clock frequency or operating frequency from all circuit connection information of the semiconductor integrated circuit is calculated for each P-channel transistor of the power supply model. And the sum of the gate capacity of each P-channel transistor and the wiring capacity between the output and the first power supply is taken as the first load capacity of the power supply model, and the sum of the individual gate width dimensions of all N-channel transistors is 8. The EMI according to claim 7, wherein the dimensions of the N-channel transistor of the power supply model are used, and the sum of the gate capacitance of each N-channel transistor and the wiring capacitance between the output and the second power supply is the second load capacitance of the power supply model. A method for designing a power supply model of a semiconductor integrated circuit for simulation. 9. The product of the number of P-channel transistors switching at the same clock frequency or operating frequency and the average gate width of the P-channel transistors from all circuit connection information of the semiconductor integrated circuit, The product of the average gate capacitance of the P-channel transistor, the sum of the average wiring capacitance between the output and the first power supply, and the number of P-channel transistors is defined as the first load capacitance of the power supply model. The product of the number of transistors and the average gate width of the N-channel transistor is defined as the dimension of the N-channel transistor of the power supply model. The sum of the average gate capacitance of the N-channel transistor, the output, and the average wiring capacitance between the second power supply and N-channel A product of the number of transistors and a second load capacitance of the power supply model Item 7. A method for designing a power supply model of a semiconductor integrated circuit for EMI simulation according to Item 7. 10. The product of the average operating rate of the semiconductor integrated circuit, the number of all P-channel transistors, and the average gate width of the P-channel transistors is defined as the size of the P-channel transistor of the power supply model, and the average gate capacitance of the P-channel transistors is The product of the sum of the average wiring capacitance between the output and the first power supply, the average operation rate, and the number of all P-channel transistors is defined as the first load capacitance of the power supply model, and the average operation rate and the number of all N-channel transistors are used. And the average gate width dimension of the N-channel transistor as the dimension of the N-channel transistor of the power supply model, the sum of the average gate capacity of the N-channel transistor, the output and the average wiring capacity between the second power supply, the average operation rate, and the total 8. The EMI spot according to claim 7, wherein a product of the number of N-channel transistors and the number of N-channel transistors is used as a second load capacitance of the power supply model. Design method of power supply model of simulation semiconductor integrated circuit. 11. The product of the maximum operating rate of the semiconductor integrated circuit, the number of all P-channel transistors, and the average gate width of the P-channel transistors is defined as the size of the P-channel transistors of the power supply model, and the average gate capacitance of the P-channel transistors is determined. The product of the sum of the average wiring capacitance between the output and the first power supply, the maximum operation rate, and the number of all P-channel transistors is defined as the first load capacitance of the power supply model, and the maximum operation rate and the number of all N-channel transistors are used. The product of the average gate width of the N-channel transistor and the average gate width of the N-channel transistor is defined as the dimension of the N-channel transistor of the power supply model. 8. The EMI spot according to claim 7, wherein a product of the number of N-channel transistors and the number of N-channel transistors is used as a second load capacitance of the power supply model. Design method of power supply model of simulation semiconductor integrated circuit. 12. An inverter circuit comprising a P-channel transistor and an N-channel transistor having an average gate width with respect to an average power supply current of the whole semiconductor integrated circuit, and a first average load connected between an output terminal thereof and a first power supply. The ratio of the average power supply current of one basic gate circuit composed of a capacitor and an output terminal and a second average load capacitance connected between the second power supply is defined as a power supply current ratio. The product of the number of all P-channel transistors and the average gate width of the P-channel transistors is defined as the dimension of the P-channel transistor of the power supply model, and the sum of the average gate capacitance of the P-channel transistors and the average wiring capacitance between the output and the first power supply The product of the power supply current ratio and the number of all P-channel transistors is defined as the first load capacitance of the power supply model. The product of the number of all N-channel transistors and the average gate width of the N-channel transistors is defined as the dimensions of the N-channel transistors in the power supply model, and the sum of the average gate capacitance of the N-channel transistors and the average wiring capacitance between the output and the second power supply. 8. The method of designing a power supply model of a semiconductor integrated circuit for EMI simulation according to claim 7, wherein a product of the power supply current ratio and the number of all N-channel transistors is used as a second load capacitance of the power supply model. 13. A power supply model for a P-channel transistor which performs a switching operation at the same clock frequency or operating frequency based on all circuit connection information of the semiconductor integrated circuit. The dimensions of the respective P-channel transistors of the first and second inverter circuits, and the half of the sum of the gate capacitance of each P-channel transistor and the wiring capacitance between the output and the first power supply are defined as the first value of the power supply model. And a third load capacitance. For all N-channel transistors, a half of the sum of the individual gate widths is set as the size of each of the N-channel transistors of the first and second inverter circuits of the power supply model. The half value of the sum of the gate capacitance of the N-channel transistor and the wiring capacitance between the output and the second power supply is set to the value of the power supply model. 8. The method for designing a power supply model of a semiconductor integrated circuit for EMI simulation according to claim 7, wherein the second and fourth load capacitances are used. 14. A value which is a half of the product of the number of P-channel transistors switching at the same clock frequency or operating frequency and the average gate width of the P-channel transistors from all circuit connection information of the semiconductor integrated circuit. The dimensions of the respective P-channel transistors of the first and second inverter circuits of the power supply model, and the sum of the average gate capacitance and output of the P-channel transistors and the average wiring capacitance between the first power supply and the number of P-channel transistors Half the value of the product is the first and third load capacitance of the power supply model, and half the value of the product of the number of N-channel transistors and the average gate width of the N-channel transistor is the first and second load capacitance of the power supply model. N of each of the inverter circuits
The half of the product of the average gate capacitance of the N-channel transistor and the sum of the average wiring capacitance between the output and the second power supply and the number of N-channel transistors is defined as the second and fourth power supply model. 8. The method for designing a power supply model of a semiconductor integrated circuit for EMI simulation according to claim 7, wherein the load capacity is set to: 15. A value which is a half of a product of an average operating rate of the semiconductor integrated circuit, the number of all P-channel transistors, and an average gate width dimension of the P-channel transistors is set to each of the first and second inverter circuits of the power supply model. And the half of the product of the sum of the average gate capacitance of the P-channel transistor, the output, and the average wiring capacitance between the first power supply, the average operating rate, and the number of all P-channel transistors, The first and second inverter circuits of the power supply model are defined as half of the product of the average operation rate, the number of all N-channel transistors, and the average gate width of the N-channel transistors. , The average gate capacitance of the N-channel transistor and the average wiring capacitance between the output and the second power supply. 8. The power supply model of the semiconductor integrated circuit for EMI simulation according to claim 7, wherein a half value of a product of the sum of the average operation rate and the number of all N-channel transistors is used as the second and fourth load capacitances of the power supply model. Design method. 16. A value which is a half of a product of a maximum operation rate of the semiconductor integrated circuit, the number of all P-channel transistors, and an average gate width of the P-channel transistors is set to each of the first and second inverter circuits of the power supply model. And the half of the product of the sum of the average gate capacitance of the P-channel transistor, the output, and the average wiring capacitance between the output and the first power supply, the maximum operation rate, and the number of all the P-channel transistors. The first and second inverter circuits of the power supply model are defined as the first and third load capacitances of the model, and half the product of the maximum operation rate, the number of all N-channel transistors, and the average gate width of the N-channel transistors. , The average gate capacitance of the N-channel transistor and the average wiring capacitance between the output and the second power supply. 8. The power supply model of the semiconductor integrated circuit for EMI simulation according to claim 7, wherein half the value of the product of the sum of the maximum operating rate and the number of all N-channel transistors is used as the second and fourth load capacitances of the power supply model. Design method. 17. A first inverter circuit comprising a P-channel transistor and an N-channel transistor having a half of an average gate width with respect to an average power supply current of the whole semiconductor integrated circuit, and is connected between an output terminal thereof and a first power supply. The first average load capacitance, the second average load capacitance connected between the output terminal and the second power supply, and P which is half the average gate width dimension when the output terminal of the first inverter circuit is connected to the input terminal
A second inverter circuit including a channel transistor and an N-channel transistor; a third load capacitance connected between an output terminal of the second inverter circuit and a first power supply; and an output terminal of the second inverter circuit. And a fourth load capacitance connected between the second power supply and the basic power supply circuit.
The power supply current ratio, the number of all P-channel transistors and P
The half value of the product of the average gate width dimension of the channel transistor is defined as the dimension of each of the P-channel transistors of the first and second inverter circuits of the power supply model, and the average gate capacitance and output of the P-channel transistor and the first power supply The half of the product of the sum of the average wiring capacitance between the power supply current ratio and the number of all P-channel transistors is defined as the first and third load capacitances of the power supply model, and the power supply current ratio and the number of all N-channel transistors are used. And a half value of the product of the average gate width dimension of the N-channel transistor as the dimensions of the N-channel transistors of the first and second inverter circuits of the power supply model. The value of half of the product of the sum of the average wiring capacitance between the power supplies, the power supply current ratio, and the number of all N-channel transistors Second and fourth method for designing a power supply model EMI simulation for a semiconductor integrated circuit according to claim 7 wherein the load capacitance Dell. 18. A value obtained by connecting individual ON resistors in parallel for all P-channel transistors that are not switching at the same clock frequency or operating frequency from all circuit connection information of the semiconductor integrated circuit according to claim 8 and 13. Is set as the series resistance of the third equivalent internal capacitance, and half of the sum of the individual gate capacitances and the wiring capacitance between the output and the first power supply is set as the second equivalent internal capacitance. No ON for all N-channel transistors
A value twice as large as a value obtained by connecting the resistors in parallel is defined as a series resistance of the second equivalent internal capacitance, and a half of the sum of the individual gate capacitances and the wiring capacitance between the output and the second power supply is defined as a third equivalent internal capacitance. A method of designing a power supply model of a semiconductor integrated circuit for EMI simulation as a capacitance. 19. The average ON resistance according to claim 9, wherein all P-channel transistors that are not switching at the same clock frequency or operating frequency are the same as the number of P-channel transistors from all circuit connection information of the semiconductor integrated circuit. Is the series resistance of the third equivalent internal capacitance, and is half the number of P-channel transistors times the sum of the average gate capacitance of the P-channel transistors and the average wiring capacitance between the output and the first power supply. The value is defined as the second equivalent internal capacitance, and for all the non-operating N-channel transistors, twice the value of the parallel connection of the average ON resistance by the number of N-channel transistors is defined as the series resistance of the second equivalent internal capacitance. Sum of the average gate capacitance of the channel transistor and the average wiring capacitance between the output and the second power supply A method of designing a power supply model of a semiconductor integrated circuit for EMI simulation, in which a half of the number is set as a third equivalent internal capacitance. 20. The semiconductor device according to claim 10, wherein the number of all P-channel transistors and the total
The difference between the product of the number of channel transistors and the average operating rate is defined as the number of non-operating P-channel transistors, and twice the value obtained by connecting the average ON resistance for the number of non-operating P-channel transistors in parallel is the third equivalent internal capacitance. A semiconductor integrated circuit having a series resistance, a value equivalent to a half of the product of the sum of the average gate capacitance of the P-channel transistor and the average wiring capacitance between the output and the first power supply and the number of non-operating P-channel transistors, The difference between the product of the number of all N-channel transistors, the number of all N-channel transistors, and the average operation rate is defined as the number of non-operational N-channel transistors, and the average ON resistance for the number of non-operational N-channel transistors is connected in parallel. 2
Double the series resistance of the second equivalent internal capacitance, and calculate the third half of the product of the sum of the average gate capacitance of the N-channel transistor and the average wiring capacitance between the output and the second power supply and the number of non-operating N-channel transistors. A method of designing a power supply model of a semiconductor integrated circuit for EMI simulation with an equivalent internal capacitance. 21. The semiconductor device according to claim 11, wherein the number of all P-channel transistors and the total
The difference between the product of the number of channel transistors and the maximum operation rate is defined as the number of non-operating P-channel transistors, and twice the value obtained by connecting the average ON resistances for the number of non-operating P-channel transistors in parallel is the third equivalent internal capacitance. A semiconductor integrated circuit having a series resistance, a value equivalent to a half of the product of the sum of the average gate capacitance of the P-channel transistor and the average wiring capacitance between the output and the first power supply and the number of non-operating P-channel transistors, The difference between the product of the number of all N-channel transistors, the number of all N-channel transistors, and the maximum operating rate is defined as the number of non-operating N-channel transistors, and the average ON resistance for the number of non-operating N-channel transistors is connected in parallel. 2
Double the series resistance of the second equivalent internal capacitance, and calculate the third half of the product of the sum of the average gate capacitance of the N-channel transistor and the average wiring capacitance between the output and the second power supply and the number of non-operating N-channel transistors. A method of designing a power supply model of a semiconductor integrated circuit for EMI simulation with an equivalent internal capacitance. 22. The semiconductor device according to claim 12, wherein the number of all P-channel transistors and the total
The difference between the product of the number of channel transistors and the power supply current ratio is defined as the number of inactive P-channel transistors.
Double the value of the average ON resistance for the number of channel transistors connected in parallel as the series resistance of the third equivalent internal capacitance, and calculate the sum of the average gate capacitance of the P-channel transistor and the average wiring capacitance between the output and the first power supply. A half equivalent value of the product of the number of non-operating P-channel transistors is defined as a second equivalent internal capacitance, and the difference between the product of the number of all N-channel transistors, the number of all N-channel transistors, and the power supply current ratio of the semiconductor integrated circuit is calculated as The number of operating N-channel transistors, twice the value of the average ON resistance of the number of non-operating N-channel transistors connected in parallel, is defined as the series resistance of the second equivalent internal capacitance, and the average gate capacitance and output of the N-channel transistor and the second The half of the product of the average wiring capacitance between the power supplies and the number of non-operating N-channel transistors is set to a third equivalent internal capacitance. Method for designing the power model of the body an integrated circuit. 23. A design support system for designing a power supply model of a semiconductor integrated circuit for EMI simulation to which the design method according to claim 7 is applied. 24. An EM to which the power supply model of the semiconductor integrated circuit for EMI simulation according to claim 1 is applied.
I simulation device. 25. A recording medium recording a design program of a power supply model of a semiconductor integrated circuit for EMI simulation for a printed circuit board and a semiconductor integrated circuit, wherein the power supply model is a storage medium of the semiconductor integrated circuit to be subjected to the EMI simulation. A recording medium characterized by being designed based on all circuit connection information. 26. A total sum of individual gate width dimensions of all P-channel transistors that are switching at the same clock frequency or operating frequency from all circuit connection information of the semiconductor integrated circuit, And the sum of the gate capacity of each P-channel transistor and the wiring capacity between the output and the first power supply is taken as the first load capacity of the power supply model, and the sum of the individual gate width dimensions of all N-channel transistors is 26. The recording according to claim 25, wherein a dimension of an N-channel transistor of the power supply model is set, and a sum of a gate capacity of each N-channel transistor and a wiring capacity between an output and a second power supply is set as a second load capacitance of the power supply model. Medium. 27. The product of the number of P-channel transistors switching at the same clock frequency or operating frequency and the average gate width of the P-channel transistors is calculated from the total circuit connection information of the semiconductor integrated circuit by the P of the power supply model. The product of the average gate capacitance of the P-channel transistor, the sum of the average wiring capacitance between the output and the first power supply, and the number of P-channel transistors is defined as the first load capacitance of the power supply model. The product of the number of transistors and the average gate width of the N-channel transistor is defined as the dimension of the N-channel transistor of the power supply model. The sum of the average gate capacitance of the N-channel transistor, the output, and the average wiring capacitance between the second power supply and N-channel The product of the number of transistors and the number of transistors may be used as the second load capacity of the power supply model. 26. The recording medium according to claim 25. 28. The product of the average operating rate of the semiconductor integrated circuit, the number of all P-channel transistors, and the average gate width of the P-channel transistors is defined as the size of the P-channel transistors of the power supply model, and the average gate capacitance of the P-channel transistors is The product of the sum of the average wiring capacitance between the output and the first power supply, the average operation rate, and the number of all P-channel transistors is defined as the first load capacitance of the power supply model, and the average operation rate and the number of all N-channel transistors are used. And the average gate width dimension of the N-channel transistor as the dimension of the N-channel transistor of the power supply model, the sum of the average gate capacity of the N-channel transistor, the output and the average wiring capacity between the second power supply, the average operation rate, and the total 26. The recording medium according to claim 25, wherein a product of the number of N-channel transistors and the number of N-channel transistors is used as a second load capacitance of the power supply model. . 29. The product of the maximum operating rate of the semiconductor integrated circuit, the number of all P-channel transistors, and the average gate width of the P-channel transistors is defined as the size of the P-channel transistors of the power supply model, and the average gate capacitance of the P-channel transistors is The product of the sum of the average wiring capacitance between the output and the first power supply, the maximum operation rate, and the number of all P-channel transistors is defined as the first load capacitance of the power supply model, and the maximum operation rate and the number of all N-channel transistors are used. The product of the average gate width of the N-channel transistor and the average gate width of the N-channel transistor is defined as the dimension of the N-channel transistor of the power supply model. 26. The recording medium according to claim 25, wherein a product of the number of N-channel transistors and the number of N-channel transistors is used as a second load capacitance of the power supply model. . 30. An inverter circuit comprising a P-channel transistor and an N-channel transistor having an average gate width with respect to an average power supply current of the whole semiconductor integrated circuit, and a first average load connected between an output terminal thereof and a first power supply. The ratio of the average power supply current of one basic gate circuit composed of a capacitor and an output terminal and a second average load capacitance connected between the second power supply is defined as a power supply current ratio. The product of the number of all P-channel transistors and the average gate width of the P-channel transistors is defined as the dimension of the P-channel transistor of the power supply model, and the sum of the average gate capacitance of the P-channel transistors and the average wiring capacitance between the output and the first power supply The product of the power supply current ratio and the number of all P-channel transistors is defined as the first load capacitance of the power supply model. The product of the number of all N-channel transistors and the average gate width of the N-channel transistors is defined as the dimensions of the N-channel transistors in the power supply model, and the sum of the average gate capacitance of the N-channel transistors and the average wiring capacitance between the output and the second power supply. 8. The recording medium according to claim 7, wherein a product of the power supply current ratio and the number of all N-channel transistors is used as a second load capacitance of the power supply model. 31. For all P-channel transistors that are performing switching operation at the same clock frequency or operating frequency based on all circuit connection information of the semiconductor integrated circuit, a value that is a half of the sum of individual gate width dimensions of the power supply model is The dimensions of the respective P-channel transistors of the first and second inverter circuits, and the half of the sum of the gate capacitance of each P-channel transistor and the wiring capacitance between the output and the first power supply are defined as the first value of the power supply model. And a third load capacitance. For all N-channel transistors, a half of the sum of the individual gate widths is set as the size of each of the N-channel transistors of the first and second inverter circuits of the power supply model. The half value of the sum of the gate capacitance of the N-channel transistor and the wiring capacitance between the output and the second power supply is set to the value of the power supply model. 26. The recording medium according to claim 25, wherein the recording medium has a second and a fourth load capacity. 32. A value which is a half of the product of the number of P-channel transistors switching at the same clock frequency or operating frequency and the average gate width of the P-channel transistors from all circuit connection information of the semiconductor integrated circuit. The dimensions of the respective P-channel transistors of the first and second inverter circuits of the power supply model, and the sum of the average gate capacitance and output of the P-channel transistors and the average wiring capacitance between the first power supply and the number of P-channel transistors Half the value of the product is the first and third load capacitance of the power supply model, and half the value of the product of the number of N-channel transistors and the average gate width of the N-channel transistor is the first and second load capacitance of the power supply model. N of each of the inverter circuits
The half of the product of the average gate capacitance of the N-channel transistor and the sum of the average wiring capacitance between the output and the second power supply and the number of N-channel transistors is defined as the second and fourth power supply model. 26. The recording medium according to claim 25, wherein the load capacity is set to: 33. A value which is a half of a product of an average operation rate of the semiconductor integrated circuit, the number of all P-channel transistors, and an average gate width dimension of the P-channel transistors for each of the first and second inverter circuits of the power supply model And the half of the product of the sum of the average gate capacitance of the P-channel transistor, the output, and the average wiring capacitance between the first power supply, the average operating rate, and the number of all P-channel transistors, The first and second inverter circuits of the power supply model are defined as half of the product of the average operation rate, the number of all N-channel transistors, and the average gate width of the N-channel transistors. , The average gate capacitance of the N-channel transistor and the average wiring capacitance between the output and the second power supply. 26. The recording medium according to claim 25, wherein a half value of the product of the sum of the power supply model and the number of all N-channel transistors is used as the second and fourth load capacitances of the power supply model. 34. A value which is a half of a product of a maximum operation rate of the semiconductor integrated circuit, the number of all P-channel transistors, and an average gate width of the P-channel transistors, respectively, for each of the first and second inverter circuits of the power supply model And the half of the product of the sum of the average gate capacitance of the P-channel transistor, the output, and the average wiring capacitance between the output and the first power supply, the maximum operation rate, and the number of all the P-channel transistors. The first and second inverter circuits of the power supply model are defined as the first and third load capacitances of the model, and half the product of the maximum operation rate, the number of all N-channel transistors, and the average gate width of the N-channel transistors. , The average gate capacitance of the N-channel transistor and the average wiring capacitance between the output and the second power supply. 26. The recording medium according to claim 25, wherein half the value of the product of the sum of the maximum operating rate and the number of all N-channel transistors is used as the second and fourth load capacitances of the power supply model. 35. A first inverter circuit comprising a P-channel transistor and an N-channel transistor having half the average gate width dimension with respect to the average power supply current of the entire semiconductor integrated circuit, and connected between an output terminal thereof and the first power supply. The first average load capacitance, the second average load capacitance connected between the output terminal and the second power supply, and P which is half the average gate width dimension when the output terminal of the first inverter circuit is connected to the input terminal
A second inverter circuit including a channel transistor and an N-channel transistor; a third load capacitance connected between an output terminal of the second inverter circuit and a first power supply; and an output terminal of the second inverter circuit. And a fourth load capacitance connected between the second power supply and the basic power supply circuit.
The power supply current ratio, the number of all P-channel transistors and P
The half value of the product of the average gate width dimension of the channel transistor is defined as the dimension of each of the P-channel transistors of the first and second inverter circuits of the power supply model, and the average gate capacitance and output of the P-channel transistor and the first power supply The half of the product of the sum of the average wiring capacitance between the power supply current ratio and the number of all P-channel transistors is defined as the first and third load capacitances of the power supply model, and the power supply current ratio and the number of all N-channel transistors are used. And a half value of the product of the average gate width dimension of the N-channel transistor as the dimensions of the N-channel transistors of the first and second inverter circuits of the power supply model. The value of half of the product of the sum of the average wiring capacitance between the power supplies, the power supply current ratio, and the number of all N-channel transistors Second recording medium according to claim 25, wherein the fourth load capacity Dell. 36. A circuit according to claim 26, wherein, based on all circuit connection information of said semiconductor integrated circuit, a value obtained by connecting individual ON resistors in parallel for all P-channel transistors which are not switching at the same clock frequency or operating frequency. Is set as the series resistance of the third equivalent internal capacitance, and half of the sum of the individual gate capacitances and the wiring capacitance between the output and the first power supply is set as the second equivalent internal capacitance. No ON for all N-channel transistors
A value twice as large as a value obtained by connecting the resistors in parallel is defined as a series resistance of the second equivalent internal capacitance, and a half of the sum of the individual gate capacitances and the wiring capacitance between the output and the second power supply is defined as a third equivalent internal capacitance. A recording medium that has a capacity. 37. An average ON resistance according to the number of P-channel transistors of all P-channel transistors which are not performing a switching operation at the same clock frequency or operating frequency from all circuit connection information of the semiconductor integrated circuit. Is the series resistance of the third equivalent internal capacitance, and is half the number of P-channel transistors times the sum of the average gate capacitance of the P-channel transistors and the average wiring capacitance between the output and the first power supply. The value is defined as the second equivalent internal capacitance, and for all the non-operating N-channel transistors, twice the value of the parallel connection of the average ON resistance by the number of N-channel transistors is defined as the series resistance of the second equivalent internal capacitance. N-channel transistor having the sum of the average gate capacitance of the channel transistor and the average wiring capacitance between the output and the second power supply A recording medium in which a half of the number of times is set as a third equivalent internal capacity. 38. The semiconductor device according to claim 28, wherein the number of all P-channel transistors and the total
The difference between the product of the number of channel transistors and the average operation rate is defined as the number of non-operating P-channel transistors, and twice the value obtained by connecting the average ON resistance for the number of non-operating P-channel transistors in parallel is the third equivalent internal capacitance. A semiconductor integrated circuit, wherein a value equivalent to a half of the product of the sum of the average gate capacitance of the P-channel transistor and the average wiring capacitance between the output and the first power supply and the number of non-operating P-channel transistors is defined as a series resistance; The difference between the number of all N-channel transistors and the product of the number of all N-channel transistors and the average operating rate is defined as the number of non-operating N-channel transistors. 2
Double the series resistance of the second equivalent internal capacitance, and calculate the third half of the product of the sum of the average gate capacitance of the N-channel transistor and the average wiring capacitance between the output and the second power supply and the number of non-operating N-channel transistors. Recording medium with an equivalent internal capacity of 39. The semiconductor device according to claim 29, wherein the number of all P-channel transistors and the total
The difference between the product of the number of channel transistors and the maximum operation rate is defined as the number of non-operating P-channel transistors, and twice the value obtained by connecting the average ON resistances for the number of non-operating P-channel transistors in parallel is the third equivalent internal capacitance. A semiconductor integrated circuit having a series resistance, a value equivalent to a half of the product of the sum of the average gate capacitance of the P-channel transistor and the average wiring capacitance between the output and the first power supply and the number of non-operating P-channel transistors, The difference between the product of the number of all N-channel transistors, the number of all N-channel transistors, and the maximum operating rate is defined as the number of non-operating N-channel transistors, and the average ON resistance for the number of non-operating N-channel transistors is connected in parallel. 2
Double the series resistance of the second equivalent internal capacitance, and calculate the third half of the product of the sum of the average gate capacitance of the N-channel transistor and the average wiring capacitance between the output and the second power supply and the number of non-operating N-channel transistors. Recording medium with an equivalent internal capacity of 40. The semiconductor integrated circuit according to claim 30, wherein the number of all P-channel transistors and the total
The difference between the product of the number of channel transistors and the power supply current ratio is defined as the number of inactive P-channel transistors.
Double the value of the average ON resistance for the number of channel transistors connected in parallel as the series resistance of the third equivalent internal capacitance, and calculate the sum of the average gate capacitance of the P-channel transistor and the average wiring capacitance between the output and the first power supply. A half equivalent value of the product of the number of non-operating P-channel transistors is defined as a second equivalent internal capacitance, and the difference between the product of the number of all N-channel transistors, the number of all N-channel transistors, and the power supply current ratio of the semiconductor integrated circuit is calculated as The number of operating N-channel transistors, twice the value of the average ON resistance of the number of non-operating N-channel transistors connected in parallel, is defined as the series resistance of the second equivalent internal capacitance, and the average gate capacitance and output of the N-channel transistor and the second And a half of the product of the average wiring capacitance between the power supplies and the number of non-operating N-channel transistors as a third equivalent internal capacitance. 41. A power supply model of a semiconductor integrated circuit for a printed circuit board and a semiconductor integrated circuit, wherein the power supply model is connected to an inverter to which power is supplied and an output of the inverter and the power supply. A power supply model characterized by including a specified equivalent internal capacitance section. 42. A method of designing a power supply model of a semiconductor integrated circuit for a printed circuit board and a semiconductor integrated circuit, wherein the power supply model is designed based on all circuit connection information of the target semiconductor integrated circuit. A method for designing a power supply model of a semiconductor integrated circuit. 43. A recording medium recording a design program of a power supply model of a semiconductor integrated circuit for a printed circuit board and a semiconductor integrated circuit, wherein the power supply model is information on all circuit connections of the target semiconductor integrated circuit. Recording medium characterized by being designed based on.