US20190384869A1 - Integrated system of pdn implementation and digital co-synthesis - Google Patents
Integrated system of pdn implementation and digital co-synthesis Download PDFInfo
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- US20190384869A1 US20190384869A1 US16/551,421 US201916551421A US2019384869A1 US 20190384869 A1 US20190384869 A1 US 20190384869A1 US 201916551421 A US201916551421 A US 201916551421A US 2019384869 A1 US2019384869 A1 US 2019384869A1
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
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- G06F17/5022—
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- G06F17/5036—
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- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
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- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
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- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/06—Power analysis or power optimisation
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Definitions
- the present invention relates generally to integrated circuit design, and more particularly to integration of power delivery network design and digital logic design flows.
- Digital logic circuitry for integrated circuits are often designed using a number of design tools, with operation of the tools being arranged in a sequence, which may considered to provide a digital logic design flow.
- these design flows include specifying digital circuit operations, for example using a hardware description language (HDL) such as Verilog or VHDL, creating a register transfer level (RTL) description of the circuit based on the HDL, synthesizing the RTL description to a netlist, and using a place and route tool to determine placement of gates of the netlist and routing of signals between the gates.
- HDL hardware description language
- RTL register transfer level
- place and route tool to determine placement of gates of the netlist and routing of signals between the gates.
- various testing schemes are applied at each stage of the process, generally to determine if each stage is formally equivalent to a prior stage, and steps of the process may be repeated depending on the outcome of the tests.
- the digital logic design flow is generally effective at reducing costs for design of integrated circuitry, and for providing integrated circuit designs that meet functional requirements.
- PDN power distribution network
- on-chip voltage regulators and associated circuitry are generally specialized circuits that are specially handled in the design process, and not incorporated into the digital logic design flow.
- the PDN may be specially designed and specially placed, which may result in inconsistencies or undesired effects.
- Some embodiments in accordance with aspects of the invention provide for integration of power delivery network design into a digital logic design flow.
- Some embodiments in accordance with aspects of the invention provide a method useful in integrated circuit design, comprising: receiving, by a computer, parameters for a power delivery network (PDN); receiving, by the computer, a model of logic circuitry for an integrated circuit; simulating operation of a plurality of configurations of the PDN for the model of logic circuitry over a specified range of minimum voltages; generating a netlist representation of a selected PDN configuration; and processing the netlist representation of the selected PDN configuration along with a digital circuit design for the logic circuitry.
- PDN power delivery network
- FIG. 1 is a block diagram of an integrated circuit chip (IC).
- IC integrated circuit chip
- FIG. 2 shows a partial cut away side view of an IC.
- FIG. 3 is a flow diagram of a process useful in designing an integrated circuit, in accordance with aspects of the invention.
- FIG. 4 is a flow diagram of a process useful in designing an integrated circuit, in accordance with aspects of the invention.
- FIG. 5 is a flow diagram of a process useful in synthesizing digital circuit with power delivery network (PDN) configuration in accordance with aspects of the invention.
- PDN power delivery network
- FIG. 6 is a chart illustrating an effective increase in Vdd min.
- FIG. 7 is a chart showing a further embodiment of a process flow in accordance with aspects of the invention.
- FIG. 1 is a block diagram of an integrated circuit chip (IC) 111 .
- the IC includes a plurality of logic elements 113 a - c.
- the logic elements perform various digital logic functions, and may include processor circuitry or other circuitry for processing data or performing other functions.
- the IC also includes memory circuits 115 for storing data. It should be recognized, however, the logic elements themselves may include some circuits, for example flip-flops and other items, which themselves may be considered memory circuits at times, and the number and groupings of logic elements and/or memory elements may vary significantly from that which is explicitly shown in FIG. 1 .
- the IC also includes a plurality of embedded voltage regulators 117 a - c .
- Each of the voltage regulators regulates voltage provided to elements within corresponding power islands or domains 121 a - c , with each power island including some logic and/or memory elements.
- one of the power islands, power island 117 c is also shown as including an automatic transient control (ATC) circuit 119 .
- the ATC circuit reduces effects of transients in a power delivered by the voltage regulator 117 c to the logic element 113 c within power island 121 c.
- the transients may be most noticeable, and possibly have a greatest effect on proper circuit operation, when logic element 113 c transitions between a state in which the logic element is performing large amounts of processing and a state in which the logic element may be essentially powered off and performing little to no processing.
- the IC of FIG. 1 also includes a plurality of solder bumps 125 for providing transmission of signal into or out of the IC.
- many of the bumps are or will be coupled to data sources or sinks, and some are also coupled to power elements, for example one or more power sources, for example batteries, or other items, for example capacitors and/or inductors, which may be located off-chip.
- the voltage regulators, ATC circuits, and bumps utilized for power related purposes may all be considered part of a power delivery network (PDN) of the IC, which may also include on-chip capacitors (not explicitly shown in FIG. 1 ).
- PDN power delivery network
- the number of voltage regulators and ATC circuits provided, as well as their characteristics, may effect design (including layout) and operation of other elements of the IC.
- the number of bumps utilized may also effect design and operation of the other elements of the IC.
- FIG. 2 shows a partial cut away side view of an IC 211 having a logic element 213 , an ATC circuit 219 , and a plurality of bumps 225 a - d .
- FIG. 2 shows a partial cut away side view of an IC 211 having a logic element 213 , an ATC circuit 219 , and a plurality of bumps 225 a - d .
- FIG. 2 shows a partial cut away side view of an IC 211 having
- one voltage regulator 217 a may receive power through a single bump 225 b /via 231 a combination.
- a second voltage regulator 217 b may receive power through a parallel paths of a bump 225 c /via 231 b combination and a bump 225 d /via 231 c combination.
- characteristics of the voltage regulator may be changed, for example in allowing for more efficient reception of greater power.
- position in the IC of the voltage regulators and ATC circuits, and the PDN as whole in various embodiments, is largely, and in some embodiments entirely, determined by automated tools, for example a place and route tool.
- information regarding the voltage regulators, ATC circuits, and power related bumps is provided, as part of the design process, as a netlist (or other tool specific data structure), which, in conjunction with digital logic netlist(s) (or other tool specific data structures), is operated on by additional tools (including additional synthesis steps) in creation of the IC design.
- FIG. 3 is a flow diagram of a process useful in designing an integrated circuit, in accordance with aspects of the invention. In some embodiments the process of FIG. 3 is performed by one or more processors, for example of a personal computer, workstation, or server.
- the process receives parameters relating to a power delivery network (PDN).
- the parameters may include, in various embodiments some or all of voltage regulator error and efficiency parameters, ATC circuit error parameters, voltage regulator and ATC circuit area requirements, and voltage regulator and ATC bump requirements.
- the process receives parameters relating to bump physical properties (for example bump resistance and inductance), maximum bump density, on-die capacitor capacitance and area.
- the process receives a PDN configuration selection.
- the PDN configuration selection includes a number of bumps for the power delivery network, a number of voltage regulators for the power delivery network, and a number of capacitors for the power delivery network.
- the process generates a representation of a power delivery network for instantiation in a design of an IC.
- the representation is in a form of a netlist.
- the representation is in the form of a tool-specific data structure.
- the process processes the design of the IC, including the instantiated representation of the power delivery network. In some embodiments the process processes the design by performing a further synthesis of the design. In some embodiments the process processes the design by placing circuitry of the design in a layout, and determining routing of signals between elements of the circuitry.
- FIG. 4 is a flow diagram of a process useful in designing an integrated circuit, in accordance with aspects of the invention. In some embodiments the process of FIG. 4 is performed by one or more processors, for example of a personal computer, workstation, or server.
- the process receives power circuitry modular design parameters.
- the power circuitry modular design parameters include modular voltage regulator and ATC circuit designs, and parameters relating to voltage regulator error and efficiency, ATC circuit error, voltage regulator area, ATC circuit area, voltage regulator bump requirements, and ATC circuit bump requirements.
- the process receives power related parameters.
- the power related parameters include bump inductance and resistance, maximum bump density, on-die capacitor capacitance and area, a board IR drop budget, a package IR drop budget, an on-die IR drop budget, a maximum ramp current, a ramp time, and a nominal Vdd.
- the process receives an indication of a logic circuitry model.
- the indication of the logic circuitry model comprises an area and current model for the logic circuitry at a minimum Vdd and a target frequency.
- the indication of the logic circuitry is based on a synthesis sweep of a description of the logic circuitry at a target frequency.
- the process simulates a model of a configuration of a power delivery network.
- the model is based on the power circuitry modular design parameters and the power related parameters, and the simulation is over a range of Vdd minimum voltages.
- the model specifies a particular number of PDN bumps, number of voltage regulators and/or voltage regulator configurations, number of ATC circuits and/or ATC configurations, and number of on-die capacitors and/or capacitance of on-die capacitors.
- the process determines a nominal Vdd for the configuration and area and power efficiency for the configuration.
- the simulation for the configuration is performed over a range of possible Vdd minimums.
- the process determines a Vdd minimum for power supplied by the PDN.
- the process determines if there are more PDN configurations to simulate. If so, the process returns to block 417 and simulates a model of a further configuration of the PDN.
- a plurality of PDN configurations are simulated to determine a PDN configuration that is able to provide a maximum Vdd minimum for power supplied by the PDN.
- FIG. 6 illustrates a chart of Vdd and process speeds, with Vdd ranging from a minimum voltage 611 through a maximum voltage 613 , and process speed ranging from slow speed 615 to a fast speed 617 .
- timing closure is most difficult to reach for a design that is what may be termed a slow corner of the design, one at which power is low and process speeds are low.
- minimum Vdd may be raised to a higher voltage, for example a second minimum voltage 619 , designs are less likely to fall into what could be the slow corner, and more likely to reach timing closure.
- the process continues to block 421 .
- the process receives a selection of a PDN configuration.
- FIG. 5 is a flow diagram of a process useful in synthesizing digital circuit with power delivery network (PDN) configuration in accordance with aspects of the invention.
- the process is performed by a personal computer desktop or laptop equipped with logic synthesis tools.
- a voltage regulator (VR) and an automatic transient control (ATC) are designed in a modular fashion.
- the VR and ATC are functional components of the PDN with the VR acting as a switching voltage regulator in some embodiments.
- Designing the VR and ATC in a modular fashion is efficient to shorten design and development times. In addition, doing such would allow the VR and the ATC to be tested in a modular manner such that each module is isolated and tested separately.
- the VR and ATC are tested together in some embodiments.
- Designing of the VR and ATC may begin with abstract models.
- the VR and ATC abstract models are translated into synthesizable Register Transfer Level (RTL) models which represent high-level representations of the VR and ATC.
- RTL Register Transfer Level
- the RTL models are then translated into structural models which are logic descriptions of the VR and ATC.
- schematic block structures or hardware description languages such as VHDL and Verilog are used to create the RTL models.
- the structural models may be logic-gate-level or transistor-level descriptions of the VR and ATC.
- various design parameters are determined and captured.
- the design parameters include the following: voltage regulator error rate, voltage regulator efficiency, automatic transient control error rate, voltage regulator area, automatic transient control area, voltage regulator bump requirements, and automatic transient control bump requirements.
- the voltage regulator error rate for example, imposes a maximum tolerable output voltage error rate on the VR design.
- the voltage regulator efficiency for example, imposes a minimum output power-to-input power ratio on the VR design.
- the automatic transient control error rate for example, imposes a maximum tolerable output power error rate on the ATC design.
- the voltage regulator area and automatic transient control area for example, impose form factor design constraints on the VR and ATC respectively.
- the voltage regulator and the automatic transient control areas are generally rated per square millimeter.
- the voltage regulator bump requirements and automatic transient control requirements for example, impose design constraints on the voltage regulator bump and the automatic transient control bump respectively. Bump requirements may include material type, bump height (generally measured in microns), and selection of solder paste or ball. The process then continues to block 513 .
- user design inputs are received for various components of the PDN.
- the user inputs include the following: bump properties, maximum bump density, cost per bump as translated into equally priced silicon area, on-die metal capacitor capacitance and area, on-die gate capacitor capacitance and area, IR drop budgets, ramp current, ramp time, nominal power supply voltage (V DD nom ), PDN optimization search range and granularity, and voltage regulator efficiency target.
- Bump properties may include capacitance, inductance, and resistance levels of a bump or copper pillar.
- Maximum bump density in general is measured in microns.
- IR drop budgets refers to acceptable IR drops across several components such as board, package substrate, and die that do not affect timing and functionality of a design.
- additional user design inputs are determined for the PDN.
- the additional user inputs include area versus minimum power supply voltage (V DD min ) and current versus V DD min piecewise linear models for synthesized design from a synthesis sweep at a target frequency.
- area-V DD min and current-V DD min piecewise approximations may be plotted with several linear segments to indicate characteristic of the PDN.
- the area-V DD min and current-V DD min piecewise approximations may be plotted with a single linear segment with two data-points to indicate characteristic of the PDN.
- the process then continues to block 515 .
- the process runs simulation model over a user-specified range of V DD min to identify best-for-area, best-for-power, and a plurality of PDN configurations based on the captured design parameters of the VR and ATC and the user inputs from block 513 .
- Each of the plurality of PDN configurations includes number of bumps or copper pillars, embedded voltage regulator (EVR) configuration, ATC configuration, and on-die capacitors.
- Best-for-area for example, may be the least VR and ATC areas (generally rated per square millimeter) that generate an optimized PDN.
- Best-for-power for example, may be the least power consumption by the VR and ATC that generates an optimized PDN.
- the process then continues to block 517 .
- the process selects a V DD min and a desired PDN configuration based on the best-for-area and the best-for-power identified in block 515 .
- the desired PDN configuration includes number of bumps or copper pillars, EVR configuration, ATC configuration, and on-die capacitors.
- the V DD min for example may be selected from the user-specified range of V DD min in block 513 .
- the desired PDN configuration for example may be selected from one of the plurality of PDN configurations identified and generated in block 513 .
- the process thereafter proceeds to block 519 .
- the process generates a netlist or database representation of PDN components and interconnects based on the desired PDN configuration.
- the PDN components and interconnects include the EVR, ATC, and on-die capacitors.
- the netlist may be generated as a result of performing a synthesis process that synthesizes the PDN components and interconnects.
- the netlist is generally in a text file or American Standard Code for Information Interchange (ASCII) format that contains relevant information of structural models of the PDN components and interconnects.
- the information for example may include cells used, cell interconnections, high side voltage (e.g., V DD , V CC ), low side voltage (e.g., V SS , GND), and area used.
- the synthesis process in some embodiments converts the RTL models of the PDN components and related interconnect to structural models such as gate-level descriptions.
- the synthesis process may be performed by synthesis tools such as Cadence RTL Compiler and Synopsys Design Compiler.
- the process instantiates the PDN components and interconnects into a digital circuit design.
- the process may incorporate the netlist of the PDN components and interconnects into RTL models of the digital circuit design.
- the netlist of the PDN components and interconnects is instantiated into the digital circuit design by adding the netlist into model libraries of a synthesis tool prior to synthesizing the digital circuit design.
- the process synthesizes and implements the digital circuit design with the instantiated netlist of the PDN components and interconnects at the selected V DD min .
- Synthesizing the digital circuit design may generate another netlist that contains relevant information of structural models of the PDN components and interconnects and the digital circuit.
- the generated netlist may then be compiled by a personal computer (e.g., desktop or laptop) equipped with a simulation tool (e.g., Cadence, SPICE) to generate input and output waveforms of the digital circuit with the PDN components and interconnects.
- a simulation tool e.g., Cadence, SPICE
- FIG. 7 is a chart showing a further embodiment of a process flow in accordance with aspects of the invention.
- the process flow includes execution of simulations of PDN configurations for a large circuitry model in block 711 .
- the PDN configurations make use of voltage regulator (VR) and automatic transient control (ATC) module parameter inputs 713 , other PDN related parameter inputs 715 , and inputs providing for area and current information 717 for the logic circuitry model.
- VR voltage regulator
- ATC automatic transient control
- one of the PDN configurations is selected for use.
- a netlist or database representation of the selected PDN configuration is generated, and in block 723 the PDN configuration is instantiated into a design including a logic circuitry design.
- the design is synthesized and thereafter implemented.
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Abstract
Description
- This application claims the benefit of the filing date of U.S. Provisional Patent Application No. 62/171,979, filed on Jun. 5, 2015, the disclosure of which is incorporated by reference herein.
- The present invention relates generally to integrated circuit design, and more particularly to integration of power delivery network design and digital logic design flows.
- Digital logic circuitry for integrated circuits are often designed using a number of design tools, with operation of the tools being arranged in a sequence, which may considered to provide a digital logic design flow. Very often, these design flows include specifying digital circuit operations, for example using a hardware description language (HDL) such as Verilog or VHDL, creating a register transfer level (RTL) description of the circuit based on the HDL, synthesizing the RTL description to a netlist, and using a place and route tool to determine placement of gates of the netlist and routing of signals between the gates. In addition, generally various testing schemes are applied at each stage of the process, generally to determine if each stage is formally equivalent to a prior stage, and steps of the process may be repeated depending on the outcome of the tests.
- The digital logic design flow is generally effective at reducing costs for design of integrated circuitry, and for providing integrated circuit designs that meet functional requirements.
- Some portions of semiconductor ICs, however, are generally designed outside of the digital logic design flow. For example, power distribution network (PDN) circuitry, including on-chip voltage regulators and associated circuitry, are generally specialized circuits that are specially handled in the design process, and not incorporated into the digital logic design flow. Instead, the PDN may be specially designed and specially placed, which may result in inconsistencies or undesired effects.
- Some embodiments in accordance with aspects of the invention provide for integration of power delivery network design into a digital logic design flow.
- Some embodiments in accordance with aspects of the invention provide a method useful in integrated circuit design, comprising: receiving, by a computer, parameters for a power delivery network (PDN); receiving, by the computer, a model of logic circuitry for an integrated circuit; simulating operation of a plurality of configurations of the PDN for the model of logic circuitry over a specified range of minimum voltages; generating a netlist representation of a selected PDN configuration; and processing the netlist representation of the selected PDN configuration along with a digital circuit design for the logic circuitry.
- These and other aspects of the invention are more fully comprehended upon review of this disclosure.
-
FIG. 1 is a block diagram of an integrated circuit chip (IC). -
FIG. 2 shows a partial cut away side view of an IC. -
FIG. 3 is a flow diagram of a process useful in designing an integrated circuit, in accordance with aspects of the invention. -
FIG. 4 is a flow diagram of a process useful in designing an integrated circuit, in accordance with aspects of the invention. -
FIG. 5 is a flow diagram of a process useful in synthesizing digital circuit with power delivery network (PDN) configuration in accordance with aspects of the invention. -
FIG. 6 is a chart illustrating an effective increase in Vdd min. -
FIG. 7 is a chart showing a further embodiment of a process flow in accordance with aspects of the invention. -
FIG. 1 is a block diagram of an integrated circuit chip (IC) 111. The IC includes a plurality of logic elements 113 a-c. The logic elements perform various digital logic functions, and may include processor circuitry or other circuitry for processing data or performing other functions. The IC also includesmemory circuits 115 for storing data. It should be recognized, however, the logic elements themselves may include some circuits, for example flip-flops and other items, which themselves may be considered memory circuits at times, and the number and groupings of logic elements and/or memory elements may vary significantly from that which is explicitly shown inFIG. 1 . - The IC also includes a plurality of embedded voltage regulators 117 a-c. Each of the voltage regulators regulates voltage provided to elements within corresponding power islands or domains 121 a-c, with each power island including some logic and/or memory elements. In the IC of
FIG. 1 , one of the power islands,power island 117 c, is also shown as including an automatic transient control (ATC)circuit 119. The ATC circuit reduces effects of transients in a power delivered by thevoltage regulator 117 c to thelogic element 113 c withinpower island 121 c. The transients may be most noticeable, and possibly have a greatest effect on proper circuit operation, whenlogic element 113 c transitions between a state in which the logic element is performing large amounts of processing and a state in which the logic element may be essentially powered off and performing little to no processing. - The IC of
FIG. 1 also includes a plurality ofsolder bumps 125 for providing transmission of signal into or out of the IC. In general, many of the bumps are or will be coupled to data sources or sinks, and some are also coupled to power elements, for example one or more power sources, for example batteries, or other items, for example capacitors and/or inductors, which may be located off-chip. - The voltage regulators, ATC circuits, and bumps utilized for power related purposes may all be considered part of a power delivery network (PDN) of the IC, which may also include on-chip capacitors (not explicitly shown in
FIG. 1 ). The number of voltage regulators and ATC circuits provided, as well as their characteristics, may effect design (including layout) and operation of other elements of the IC. In addition, the number of bumps utilized may also effect design and operation of the other elements of the IC. For example,FIG. 2 shows a partial cut away side view of anIC 211 having alogic element 213, anATC circuit 219, and a plurality of bumps 225 a-d. In the IC ofFIG. 2 , it may be seen that onevoltage regulator 217 a may receive power through asingle bump 225 b/via 231 a combination. Asecond voltage regulator 217 b, however, may receive power through a parallel paths of abump 225 c/via 231 b combination and abump 225 d/via 231 c combination. By receiving power along two paths, instead of one, characteristics of the voltage regulator may be changed, for example in allowing for more efficient reception of greater power. - In the embodiment of
FIG. 1 , position in the IC of the voltage regulators and ATC circuits, and the PDN as whole in various embodiments, is largely, and in some embodiments entirely, determined by automated tools, for example a place and route tool. In various embodiments information regarding the voltage regulators, ATC circuits, and power related bumps is provided, as part of the design process, as a netlist (or other tool specific data structure), which, in conjunction with digital logic netlist(s) (or other tool specific data structures), is operated on by additional tools (including additional synthesis steps) in creation of the IC design. -
FIG. 3 is a flow diagram of a process useful in designing an integrated circuit, in accordance with aspects of the invention. In some embodiments the process ofFIG. 3 is performed by one or more processors, for example of a personal computer, workstation, or server. - In
block 311 the process receives parameters relating to a power delivery network (PDN). The parameters may include, in various embodiments some or all of voltage regulator error and efficiency parameters, ATC circuit error parameters, voltage regulator and ATC circuit area requirements, and voltage regulator and ATC bump requirements. In addition, in some embodiments the process receives parameters relating to bump physical properties (for example bump resistance and inductance), maximum bump density, on-die capacitor capacitance and area. - In
block 313 the process receives a PDN configuration selection. In some embodiments the PDN configuration selection includes a number of bumps for the power delivery network, a number of voltage regulators for the power delivery network, and a number of capacitors for the power delivery network. - In
block 315 the process generates a representation of a power delivery network for instantiation in a design of an IC. In some embodiments the representation is in a form of a netlist. In some embodiments the representation is in the form of a tool-specific data structure. - In
block 317 the process instantiates the representation of the power delivery network in the design of the IC. - In
block 319 the process processes the design of the IC, including the instantiated representation of the power delivery network. In some embodiments the process processes the design by performing a further synthesis of the design. In some embodiments the process processes the design by placing circuitry of the design in a layout, and determining routing of signals between elements of the circuitry. - The process thereafter returns.
-
FIG. 4 is a flow diagram of a process useful in designing an integrated circuit, in accordance with aspects of the invention. In some embodiments the process ofFIG. 4 is performed by one or more processors, for example of a personal computer, workstation, or server. - In
block 411 the process receives power circuitry modular design parameters. In some embodiments the power circuitry modular design parameters include modular voltage regulator and ATC circuit designs, and parameters relating to voltage regulator error and efficiency, ATC circuit error, voltage regulator area, ATC circuit area, voltage regulator bump requirements, and ATC circuit bump requirements. - In
block 413 the process receives power related parameters. In some embodiments the power related parameters include bump inductance and resistance, maximum bump density, on-die capacitor capacitance and area, a board IR drop budget, a package IR drop budget, an on-die IR drop budget, a maximum ramp current, a ramp time, and a nominal Vdd. - In
block 415 the process receives an indication of a logic circuitry model. In some embodiments the indication of the logic circuitry model comprises an area and current model for the logic circuitry at a minimum Vdd and a target frequency. In some embodiments the indication of the logic circuitry is based on a synthesis sweep of a description of the logic circuitry at a target frequency. - In
block 417 the process simulates a model of a configuration of a power delivery network. In many embodiments the model is based on the power circuitry modular design parameters and the power related parameters, and the simulation is over a range of Vdd minimum voltages. In some embodiments the model specifies a particular number of PDN bumps, number of voltage regulators and/or voltage regulator configurations, number of ATC circuits and/or ATC configurations, and number of on-die capacitors and/or capacitance of on-die capacitors. In some embodiments the process determines a nominal Vdd for the configuration and area and power efficiency for the configuration. In some embodiments the simulation for the configuration is performed over a range of possible Vdd minimums. In some embodiments the process determines a Vdd minimum for power supplied by the PDN. - In
block 419 the process determines if there are more PDN configurations to simulate. If so, the process returns to block 417 and simulates a model of a further configuration of the PDN. In some embodiments a plurality of PDN configurations are simulated to determine a PDN configuration that is able to provide a maximum Vdd minimum for power supplied by the PDN. For example,FIG. 6 illustrates a chart of Vdd and process speeds, with Vdd ranging from aminimum voltage 611 through amaximum voltage 613, and process speed ranging fromslow speed 615 to afast speed 617. Generally, timing closure is most difficult to reach for a design that is what may be termed a slow corner of the design, one at which power is low and process speeds are low. If, however, minimum Vdd may be raised to a higher voltage, for example a secondminimum voltage 619, designs are less likely to fall into what could be the slow corner, and more likely to reach timing closure. - If there are no more PDN configurations to simulate, the process continues to block 421. In
block 421 the process receives a selection of a PDN configuration. - The process thereafter returns.
-
FIG. 5 is a flow diagram of a process useful in synthesizing digital circuit with power delivery network (PDN) configuration in accordance with aspects of the invention. In some embodiments, the process is performed by a personal computer desktop or laptop equipped with logic synthesis tools. - At
block 511, a voltage regulator (VR) and an automatic transient control (ATC) are designed in a modular fashion. The VR and ATC are functional components of the PDN with the VR acting as a switching voltage regulator in some embodiments. Designing the VR and ATC in a modular fashion, for example, is efficient to shorten design and development times. In addition, doing such would allow the VR and the ATC to be tested in a modular manner such that each module is isolated and tested separately. The VR and ATC, however, are tested together in some embodiments. Designing of the VR and ATC, for example, may begin with abstract models. The VR and ATC abstract models are translated into synthesizable Register Transfer Level (RTL) models which represent high-level representations of the VR and ATC. The RTL models are then translated into structural models which are logic descriptions of the VR and ATC. In some embodiments, schematic block structures or hardware description languages such as VHDL and Verilog are used to create the RTL models. The structural models may be logic-gate-level or transistor-level descriptions of the VR and ATC. When designing the VR and the ATC, various design parameters are determined and captured. The design parameters include the following: voltage regulator error rate, voltage regulator efficiency, automatic transient control error rate, voltage regulator area, automatic transient control area, voltage regulator bump requirements, and automatic transient control bump requirements. The voltage regulator error rate, for example, imposes a maximum tolerable output voltage error rate on the VR design. The voltage regulator efficiency, for example, imposes a minimum output power-to-input power ratio on the VR design. The automatic transient control error rate, for example, imposes a maximum tolerable output power error rate on the ATC design. The voltage regulator area and automatic transient control area, for example, impose form factor design constraints on the VR and ATC respectively. The voltage regulator and the automatic transient control areas are generally rated per square millimeter. The voltage regulator bump requirements and automatic transient control requirements, for example, impose design constraints on the voltage regulator bump and the automatic transient control bump respectively. Bump requirements may include material type, bump height (generally measured in microns), and selection of solder paste or ball. The process then continues to block 513. - At
block 513, user design inputs are received for various components of the PDN. The user inputs include the following: bump properties, maximum bump density, cost per bump as translated into equally priced silicon area, on-die metal capacitor capacitance and area, on-die gate capacitor capacitance and area, IR drop budgets, ramp current, ramp time, nominal power supply voltage (VDDnom ), PDN optimization search range and granularity, and voltage regulator efficiency target. Bump properties, for example, may include capacitance, inductance, and resistance levels of a bump or copper pillar. Maximum bump density in general is measured in microns. IR drop budgets refers to acceptable IR drops across several components such as board, package substrate, and die that do not affect timing and functionality of a design. - In some embodiments, at
block 513, additional user design inputs are determined for the PDN. The additional user inputs include area versus minimum power supply voltage (VDDmin ) and current versus VDDmin piecewise linear models for synthesized design from a synthesis sweep at a target frequency. For example, area-VDDmin and current-VDDmin piecewise approximations may be plotted with several linear segments to indicate characteristic of the PDN. In some embodiments, the area-VDDmin and current-VDDmin piecewise approximations may be plotted with a single linear segment with two data-points to indicate characteristic of the PDN. The process then continues to block 515. - At
block 515, while not exceeding VDDnom and within required efficiencies, the process runs simulation model over a user-specified range of VDDmin to identify best-for-area, best-for-power, and a plurality of PDN configurations based on the captured design parameters of the VR and ATC and the user inputs fromblock 513. Each of the plurality of PDN configurations includes number of bumps or copper pillars, embedded voltage regulator (EVR) configuration, ATC configuration, and on-die capacitors. Best-for-area, for example, may be the least VR and ATC areas (generally rated per square millimeter) that generate an optimized PDN. Best-for-power, for example, may be the least power consumption by the VR and ATC that generates an optimized PDN. The process then continues to block 517. - At
block 517, the process selects a VDDmin and a desired PDN configuration based on the best-for-area and the best-for-power identified inblock 515. The desired PDN configuration includes number of bumps or copper pillars, EVR configuration, ATC configuration, and on-die capacitors. The VDDmin for example may be selected from the user-specified range of VDDmin inblock 513. The desired PDN configuration for example may be selected from one of the plurality of PDN configurations identified and generated inblock 513. The process thereafter proceeds to block 519. - At
block 519, the process generates a netlist or database representation of PDN components and interconnects based on the desired PDN configuration. In some embodiments, the PDN components and interconnects include the EVR, ATC, and on-die capacitors. The netlist, for example, may be generated as a result of performing a synthesis process that synthesizes the PDN components and interconnects. The netlist is generally in a text file or American Standard Code for Information Interchange (ASCII) format that contains relevant information of structural models of the PDN components and interconnects. The information for example may include cells used, cell interconnections, high side voltage (e.g., VDD, VCC), low side voltage (e.g., VSS, GND), and area used. In addition to generating the netlist, the synthesis process in some embodiments converts the RTL models of the PDN components and related interconnect to structural models such as gate-level descriptions. The synthesis process, for example, may be performed by synthesis tools such as Cadence RTL Compiler and Synopsys Design Compiler. - Also at
block 519, the process instantiates the PDN components and interconnects into a digital circuit design. The process, for example, may incorporate the netlist of the PDN components and interconnects into RTL models of the digital circuit design. In some embodiments, the netlist of the PDN components and interconnects is instantiated into the digital circuit design by adding the netlist into model libraries of a synthesis tool prior to synthesizing the digital circuit design. - Further in
block 519, the process synthesizes and implements the digital circuit design with the instantiated netlist of the PDN components and interconnects at the selected VDDmin . Synthesizing the digital circuit design, for example, may generate another netlist that contains relevant information of structural models of the PDN components and interconnects and the digital circuit. In some embodiments the generated netlist may then be compiled by a personal computer (e.g., desktop or laptop) equipped with a simulation tool (e.g., Cadence, SPICE) to generate input and output waveforms of the digital circuit with the PDN components and interconnects. -
FIG. 7 is a chart showing a further embodiment of a process flow in accordance with aspects of the invention. The process flow includes execution of simulations of PDN configurations for a large circuitry model inblock 711. The PDN configurations make use of voltage regulator (VR) and automatic transient control (ATC)module parameter inputs 713, other PDN relatedparameter inputs 715, and inputs providing for area andcurrent information 717 for the logic circuitry model. Inblock 719 one of the PDN configurations is selected for use. In block 721 a netlist or database representation of the selected PDN configuration is generated, and inblock 723 the PDN configuration is instantiated into a design including a logic circuitry design. Inblock 725 the design is synthesized and thereafter implemented. - Although the invention has been discussed with respect to various embodiments, it should be recognized that the invention comprises the novel and non-obvious claims supported by this disclosure.
Claims (8)
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US7051306B2 (en) | 2003-05-07 | 2006-05-23 | Mosaid Technologies Corporation | Managing power on integrated circuits using power islands |
US7000214B2 (en) * | 2003-11-19 | 2006-02-14 | International Business Machines Corporation | Method for designing an integrated circuit having multiple voltage domains |
US7984398B1 (en) * | 2004-07-19 | 2011-07-19 | Synopsys, Inc. | Automated multiple voltage/power state design process and chip description system |
US7353490B2 (en) * | 2004-10-29 | 2008-04-01 | Synopsys, Inc. | Power network synthesizer for an integrated circuit design |
US7802216B2 (en) | 2007-09-13 | 2010-09-21 | Rapid Bridge Llc | Area and power saving standard cell methodology |
CN101394127B (en) * | 2007-09-17 | 2010-06-23 | 鸿富锦精密工业(深圳)有限公司 | Voltage adjustment module design system and method |
CN100543757C (en) * | 2007-11-09 | 2009-09-23 | 北京航空航天大学 | High reliability digital integrated circuit design method |
US8499230B2 (en) | 2008-05-07 | 2013-07-30 | Lsi Corporation | Critical path monitor for an integrated circuit and method of operation thereof |
US8327302B2 (en) * | 2009-10-16 | 2012-12-04 | International Business Machines Corporation | Techniques for analysis of logic designs with transient logic |
US8539262B2 (en) * | 2010-12-09 | 2013-09-17 | Intel Corporation | Apparatus, method, and system for improved power delivery performance with a dynamic voltage pulse scheme |
US8286110B1 (en) * | 2010-12-27 | 2012-10-09 | Cadence Design Systems, Inc. | System and method for adapting electrical integrity analysis to parametrically integrated environment |
CN111630950B (en) * | 2011-12-29 | 2014-09-03 | 上海复旦微电子集团股份有限公司 | Integrated circuit design method based on double-vertical interlocking circuit and redundancy structure |
JP5910108B2 (en) | 2012-01-25 | 2016-04-27 | 株式会社ソシオネクスト | High-level synthesis apparatus, high-level synthesis method, high-level synthesis program, integrated circuit design method |
US9134777B2 (en) * | 2012-06-06 | 2015-09-15 | Qualcomm Incorporated | Bi-modal power delivery scheme for an integrated circuit comprising multiple functional blocks on a single die to achieve desired average throughput for the integrated circuit |
US9626474B2 (en) | 2013-11-08 | 2017-04-18 | Mentor Graphics Corporation | Expanded canonical forms of layout patterns |
US9305131B2 (en) * | 2013-12-03 | 2016-04-05 | Mediatek Inc. | Method for flip chip packaging co-design |
US9607122B2 (en) | 2014-01-30 | 2017-03-28 | Mentor Graphics Corporation | Timing driven clock tree synthesis |
US9305125B2 (en) | 2014-03-03 | 2016-04-05 | Freescale Semiconductor, Inc. | Integrated circuit design timing path verification tool |
US9218440B2 (en) | 2014-05-16 | 2015-12-22 | Freescale Semiconductor, Inc. | Timing verification of an integrated circuit |
US9515553B2 (en) * | 2014-06-16 | 2016-12-06 | Endura Technologies LLC | Transient power control |
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