JP5733054B2 - Semiconductor integrated circuit design apparatus and semiconductor integrated circuit design method - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit design apparatus and a semiconductor integrated circuit design method.

  In a semiconductor integrated circuit, the temperature between regions in a chip may differ depending on the arrangement position of various elements such as transistors. For large ones, the temperature difference between the regions in the chip may be about 100 ° C.

  Conventionally, in a semiconductor integrated circuit having a multilayer wiring structure, a dummy wiring film is provided in each wiring layer in order to dissipate heat of an interlayer insulating film having a low dielectric constant that is likely to accumulate heat, and each dummy wiring film is connected through a through hole. In other words, there was a technology that connected each other so that heat could be transferred to the upper wiring layer.

JP-A-6-302729 JP 2010-67842 A JP-A-10-199882

If the temperature difference within the chip is large, the semiconductor integrated circuit may not operate as designed.
This is because, for example, the characteristics of the elements (transistors, resistors or capacitors), the wiring resistance or the capacitance of the elements are locally different depending on the temperature difference, and the static characteristics of the elements and the timing of the signals are different from the simulation results. This is due to the above. Also, from the viewpoint of reliability, for example, EM (electromigration) and TDDB (insulation breakdown of the insulating film) are disadvantageous as the temperature increases, and the reliability is determined by the location where the temperature is high (the temperature is high). In some cases, the reliability is determined in part, and there is a possibility that a highly reliable semiconductor integrated circuit cannot be obtained.

  According to one aspect of the invention, a thermal analysis unit that performs thermal analysis from data of a semiconductor integrated circuit to be designed and calculates a temperature distribution, and a vector generation unit that generates a vector corresponding to the calculated temperature gradient of the temperature distribution And a dummy pattern generation unit that generates a dummy pattern according to the generated vector and adds the dummy pattern to the layout data of the semiconductor integrated circuit.

  According to the disclosed semiconductor integrated circuit design apparatus and semiconductor integrated circuit design method, it is possible to provide a highly reliable semiconductor integrated circuit with a small temperature difference in the chip.

It is a figure which shows an example of the design apparatus of this Embodiment. It is a flowchart which shows the operation example of a design apparatus. It is a figure which shows an example of a thermal analysis result. It is a figure which shows an example of the produced | generated vector. It is a figure which shows the example by which the several vector was produced | generated in one mesh area | region. It is a figure which shows the example which produces | generates a vector for every mesh area | region divided | segmented. It is a figure which shows the example of the expanded mesh area | region. It is a flowchart which shows an example of the production | generation method of a dummy pattern. It is a figure which shows the example of a layout which added the dummy pattern for planarization. It is a figure which shows the example of arrangement | positioning of the dummy pattern for planarization. It is a figure which shows the example of a connection of the dummy pattern for planarization. It is an example of the layout data containing a dummy pattern. It is a figure which shows the example of the thermal analysis result with respect to the completed layout data. It is a flowchart which shows the 2nd example of a dummy pattern production | generation process. It is a figure which shows the example of the dummy pattern produced | generated. It is a figure which shows the example of an interference part. It is a figure which shows the example of the layout data containing the dummy pattern from which the interference part was removed. It is a figure which shows the example of a production | generation of the dummy pattern for planarization. It is a figure which shows one structural example of the hardware of the computer used for this Embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram illustrating an example of a design apparatus according to the present embodiment.
The design apparatus 10 includes a thermal analysis unit 11, a vector generation unit 12, a dummy pattern generation unit 13, and a storage unit 14.

  The thermal analysis unit 11 performs thermal analysis from the data of the semiconductor integrated circuit to be designed, and calculates the temperature distribution. The thermal analysis is performed, for example, using circuit simulation data D1 such as layout data or a net list of a semiconductor integrated circuit to be designed. In the thermal analysis, physical properties of each part such as the thermal conductivity of silicon and the dielectric constant of the interlayer insulating film may be used. A commercially available thermal analysis simulation tool can be used for the thermal analysis.

The vector generation unit 12 generates a vector corresponding to the calculated temperature gradient of the temperature distribution.
The dummy pattern generation unit 13 generates a dummy pattern according to the generated vector, adds it to the layout data of the semiconductor integrated circuit, and obtains layout data D2 including the dummy pattern. The dummy pattern means a pattern that does not have a function such as an element or wiring of a semiconductor integrated circuit.

  The storage unit 14 stores circuit simulation data D1 such as layout data and a net list of the semiconductor integrated circuit to be designed. Further, the storage unit 14 stores the layout data D2 including the dummy pattern generated by the dummy pattern generation unit 13.

FIG. 2 is a flowchart illustrating an operation example of the design apparatus.
First, thermal analysis is performed in the thermal analysis unit 11 (step S1).
For example, based on the circuit simulation data D1, the thermal analysis unit 11 replaces all the circuits of the semiconductor integrated circuit with resistors and executes thermal analysis simulation. And the thermal analysis part 11 estimates Joule heat from those resistances, and the electric current which flows into a resistance, estimates heat_generation | fever amount, and produces temperature distribution from layout data and heat_generation | fever amount.

FIG. 3 is a diagram illustrating an example of a thermal analysis result.
FIG. 3 shows an example of the temperature distribution of the semiconductor integrated circuit obtained by thermal analysis. Regions 20, 21, 22, 23, and 24 indicate regions in a certain temperature range, and the temperature increases in the order of regions 20 to 24.

  Next, the vector generation unit 12 generates a vector (step S2). For example, the vector generation unit 12 divides the temperature distribution as shown in FIG. 3 into mesh regions each having a constant size, and generates a vector for each mesh region.

FIG. 4 is a diagram illustrating an example of the generated vector.
An arrow in FIG. 4 represents a vector. For example, the vector generation unit 12 generates a vector having a direction perpendicular to the temperature gradient of the temperature distribution in each mesh region. The magnitude of the vector is set according to the magnitude (steepness) of the temperature gradient in the mesh region. A larger vector is set for a mesh region having a larger temperature difference.

When a plurality of vectors are generated in one mesh region, for example, the vector generation unit 12 sets the largest vector as the vector of the mesh region.
FIG. 5 is a diagram illustrating an example in which a plurality of vectors are generated in one mesh region.

  Vectors 31 and 32 are generated in one mesh region 30. In such an example, the vector generation unit 12 sets the largest vector 31 as the vector of the mesh region 30.

  In addition, when a plurality of vectors are generated in one mesh region, the vector generation unit 12 divides the mesh region into a plurality of mesh regions, for example, and newly generates a vector for each divided mesh region. You may do it.

FIG. 6 is a diagram illustrating an example of generating a vector for each divided mesh region.
FIG. 6 shows mesh areas 35-1, 35-2, 35-3, and 35-4 obtained by dividing one mesh area into four. A vector is newly generated for each of the subdivided mesh regions 35-1 to 35-4. In the example of FIG. 6, a vector 36 is generated in the mesh area 35-1, a vector 37 is generated in the mesh area 35-2, and a vector 38 is generated in the mesh area 35-4.

  When the temperature gradient is not found in the mesh region, the vector generation unit 12 selects, for example, the largest one of the mesh region vectors adjacent to the mesh region, and the mesh region where the temperature gradient is not seen. It may be a vector.

  When no temperature gradient is found in the mesh area, the vector generation unit 12 expands the mesh area until it includes the mesh area where the vector is generated, and the vector is expanded to the mesh area. It may be a vector.

FIG. 7 is a diagram illustrating an example of an enlarged mesh region.
For example, as illustrated in FIG. 7, the vector generation unit 12 expands the mesh region 40 in which no temperature gradient is seen (merging adjacent mesh regions). When the size of the mesh region 41 is reached, the vector 42 is included. Therefore, the vector generation unit 12 newly defines the vector 42 as the vector 43 of the mesh region 41. In the example of FIG. 7, the vector 43 is obtained by enlarging the vector 42 in accordance with the size of the mesh region 41.

After the vector is generated as described above, a dummy pattern is generated (step S3). As a method for generating the dummy pattern, two examples will be described below.
(Dummy pattern generation method 1)
FIG. 8 is a flowchart illustrating an example of a dummy pattern generation method.

The dummy pattern generation unit 13 first generates a planarization dummy pattern for layout data (design data) such as a wiring pattern (step S10).
FIG. 9 is a diagram showing a layout example to which a planarizing dummy pattern is added.

  FIG. 9 shows an example in which a planarization dummy pattern 53 is generated with respect to layout data of a wiring layer having wiring patterns 50, 51, and 52 which are circuit patterns of a semiconductor integrated circuit.

  The planarizing dummy pattern 53 is arranged for the purpose of planarizing the layer by making the density in the layer uniform. For example, the dummy pattern generation unit 13 performs density analysis for each mesh region described above to check the insertion location of the planarization dummy pattern 53. As described above, a vector is set in each mesh region, and in the process described later, the flattening dummy pattern 53 is connected in accordance with the direction of the vector. The dummy pattern 53 is arranged. Further, since the vector is set in advance, the wiring density after the dummy pattern 53 is connected and the dummy pattern is generated can be predicted. Therefore, in the density analysis, the wiring density is also calculated. In consideration, the planarizing dummy pattern 53 is arranged.

FIG. 10 is a diagram illustrating an arrangement example of the dummy pattern for planarization.
For example, as shown in FIG. 10A, the flattening dummy pattern 53 is provided at regular intervals with an empty area interposed therebetween. By doing so, as shown in FIG. 10B, for the horizontal vector, a pattern connecting the horizontal flattening dummy pattern 53 is generated in the empty area, thereby causing the vector direction to be changed. A dummy pattern 53a-1 is obtained. Further, as shown in FIG. 10C, with respect to a vector in an oblique direction, a pattern that connects the flattening dummy pattern 53 in a staircase pattern is generated in the empty area, so that it follows the direction of the oblique vector. A dummy pattern 53a-2 is obtained.

  After the generation of the planarization dummy pattern, the dummy pattern generation unit 13 uses the vector generated in the process of step S2 and the layout to which the planarization dummy pattern is added, and performs the planarization dummy pattern along the vector. Are connected (step S11).

FIG. 11 is a diagram illustrating a connection example of the planarization dummy pattern.
As shown in FIGS. 10B and 10C, the dummy pattern 53a as shown in FIG. 11 is obtained by connecting the planarizing dummy pattern 53 along the vector.

  Here, as the vector size is larger, for example, a larger number of flattening dummy patterns 53 are connected to generate a longer dummy pattern 53a. Further, a plurality of dummy patterns 53a may be generated in the direction of the vector in one mesh area like the mesh area 55. Thereby, the temperature difference between the regions in the chip can be effectively reduced.

  In order to prevent the dummy pattern 53a from interfering when the circuit pattern (the wiring pattern 51 in FIG. 11) is manufactured, a predetermined distance can be maintained between the circuit pattern and the dummy pattern 53 for flattening. It is desirable to do.

Through the above processing, layout data including the dummy pattern 53a in a certain layer of the semiconductor integrated circuit to be designed is generated.
FIG. 12 is an example of layout data including a dummy pattern.

  The layout data includes a dummy pattern 53a generated by connecting some of the plurality of planarization dummy patterns 53 arranged between the wiring patterns 50 to 52 according to the vector direction.

  The dummy pattern generation unit 13 completes the layout data D2 by performing the processing of steps S10 and S11 as described above for each layer (wiring layer and bulk portion) of the semiconductor integrated circuit to be designed. In the bulk portion, the dummy pattern generation unit 13 treats the diffusion layer of the transistor, the polysilicon layer, and the like as the circuit pattern, and generates a dummy pattern by connecting the planarization dummy pattern so as not to interfere with the circuit pattern. In the bulk portion, when it is difficult to place a dummy pattern due to the spacing or layout of the polysilicon layers, the dummy pattern generation process may be applied to an empty area that is easy to place.

  Such layout data D2 becomes mask data. In a manufacturing process of a semiconductor integrated circuit, a mask is generated based on mask data by a mask manufacturing apparatus. Then, patterning using the generated mask is performed using an exposure apparatus or the like, and the above-described wiring patterns 50 to 52, the planarizing dummy pattern 53, and the dummy pattern 53a are actually manufactured.

  At that time, the planarizing dummy pattern 53 and the dummy pattern 53a are formed of a material capable of transferring heat. For example, it is formed of the same metal material (copper, aluminum, etc.) as the wiring patterns 50-52.

FIG. 13 is a diagram illustrating an example of a thermal analysis result for completed layout data.
FIG. 13 shows an example of the thermal analysis result when the layout data as shown in FIG. 12 is applied to a certain layer of the semiconductor integrated circuit having the temperature distribution as shown in FIG.

  The temperature increases in the order of the regions 60, 61, 62. Since the dummy pattern 53a as shown in FIG. 12 is generated according to a vector in a direction perpendicular to the temperature gradient, the temperature distribution in the chip is averaged. That is, the temperature difference between the regions in the chip can be reduced. As a result, the characteristic difference due to the temperature difference between the regions in the chip can be reduced.

  As a result, it is possible to provide a highly reliable semiconductor integrated circuit that can operate as designed while preventing the difference between the simulation result and the actual measurement. In addition, since the temperature distribution can be averaged and the high temperature portion can be reduced, the lifetime of the chip determined in the high temperature region can be extended. Further, in the above method, since the temperature distribution is averaged, it is not necessary to carry out a large-scale operation such as applying a different temperature to each region in the chip and performing circuit simulation.

  Further, by using the dummy pattern generation method described above, it is possible to generate a dummy pattern that averages the temperature distribution using the planarization dummy pattern used for planarization of the layers of the semiconductor integrated circuit. become.

Hereinafter, a second example of the dummy pattern generation method will be described.
(Dummy pattern generation method 2)
FIG. 14 is a flowchart illustrating a second example of dummy pattern generation processing.

The dummy pattern generation unit 13 generates a dummy pattern for each mesh region according to the vector generated as shown in FIG. 4 (step S20).
FIG. 15 is a diagram illustrating an example of a dummy pattern to be generated.

  In the second dummy pattern generation method, the dummy pattern generation unit 13 does not generate a dummy pattern according to a vector from the flattening dummy pattern, but directly generates a dummy pattern 70 as shown in FIG. 15 from the vector. Generate.

  For example, the dummy pattern generation unit 13 generates a dummy pattern along the direction of the generated vector. For example, the dummy pattern generation unit 13 may generate a plurality of dummy patterns in the vector direction in the same mesh region as the vector size increases. Further, as the vector size is larger, the dummy pattern may be generated thicker or a plurality of dummy patterns may be generated. Thereby, the temperature difference between the regions can be effectively reduced.

However, the length and width of the dummy pattern, the interval between the dummy patterns, and the interval with other layout patterns (such as wiring patterns) are in accordance with the design rules.
Next, the dummy pattern generation unit 13 inputs layout data of a circuit pattern such as a wiring pattern included in the circuit simulation data D1, and removes an interference portion of the dummy pattern with respect to the circuit pattern (step S21).

FIG. 16 is a diagram illustrating an example of an interference portion.
For example, a dummy pattern (for example, dummy pattern 70a) included in regions 50a, 51a, and 52a within a predetermined distance from each wiring pattern 50 to 52 serves as an interference portion.

  If the dummy pattern is too close to the circuit pattern such as the wiring patterns 50 to 52, the interference part is a part that may cause interference with each other during the exposure process, and the accuracy of the pattern may be impaired.

  Therefore, the dummy pattern generation unit 13 removes the interference portion by deleting the dummy patterns included in the regions 50a, 51a, and 52a, or shifting the dummy patterns so as to be out of the regions 50a, 51a, and 52a. The distances from which the regions 50a, 51a, and 52a are set apart from the wiring patterns 50 to 52 are set in consideration of, for example, the performance of the exposure apparatus to be used.

FIG. 17 is a diagram illustrating an example of layout data including a dummy pattern from which an interference portion is removed.
Here, an example in which the interference portion of the layout data shown in FIG. 16 is removed is shown. For example, the dummy pattern 70 b is obtained by removing a portion included in the region 52 a within a predetermined distance from the wiring pattern 52.

Thereafter, the dummy pattern generation unit 13 generates a planarization dummy pattern (step S22).
FIG. 18 is a diagram illustrating a generation example of a planarization dummy pattern.

  As described above, the planarization dummy pattern 80 is arranged for the purpose of planarizing the layer by making the density in the layer uniform. In the second example of the dummy pattern generation method, since the dummy pattern is generated first, the planarizing dummy pattern 80 is generated between the generated dummy patterns 70 and 70b and the wiring patterns 50 to 52. It arrange | positions so that the density in a layer may become uniform.

  The dummy pattern generation unit 13 completes the layout data D2 by performing the processes in steps S20 to S22 as described above for each layer (wiring layer and bulk part) of the semiconductor integrated circuit to be designed. In the bulk portion, the dummy pattern generation unit 13 treats the diffusion layer of the transistor, the polysilicon layer, and the like as the circuit pattern described above, and generates a dummy pattern according to the vector. In the bulk portion, when it is difficult to place a dummy pattern due to the spacing or layout of the polysilicon layer, the dummy pattern generation process may be executed for an empty area that is easy to place.

  The completed layout data D2 becomes mask data, and in the manufacturing process of the semiconductor integrated circuit, a mask is generated based on the mask data by the mask manufacturing apparatus. Then, patterning using the generated mask is performed, and the above-described wiring patterns 50 to 52, dummy patterns 70 and 70b, and planarization dummy pattern 80 are actually manufactured.

  As described above, the dummy patterns 70 and 70b and the planarizing dummy pattern 80 are formed of a material capable of transferring heat. For example, it is formed of the same metal material as the wiring patterns 50 to 52.

Even when the layout data as shown in FIG. 18 generated using the dummy pattern generation method as described above is applied, the temperature distribution as shown in FIG. 13 can be obtained and the same effect can be obtained.
In the second dummy pattern generation method, a dummy pattern along the calculated vector can be generated, so that the temperature distribution can be averaged more efficiently.

The design apparatus 10 shown in FIG. 1 can be executed by a computer as shown below.
FIG. 19 is a diagram illustrating a configuration example of computer hardware used in the present embodiment. The computer 100 is entirely controlled by a CPU (Central Processing Unit) 101. The CPU 101 is connected to a RAM (Random Access Memory) 102 and a plurality of peripheral devices via a bus 108, and realizes the functions of the thermal analysis unit 11, the vector generation unit 12, and the dummy pattern generation unit 13 illustrated in FIG. To do.

  The RAM 102 is used as a main storage device of the computer 100. The RAM 102 temporarily stores at least part of an OS (Operating System) program and application programs to be executed by the CPU 101. The RAM 102 stores various data used for processing by the CPU 101.

  Peripheral devices connected to the bus 108 include a hard disk drive (HDD) 103, a graphic processing device 104, an input interface 105, an optical drive device 106, and a communication interface 107.

  The HDD 103 magnetically writes and reads data to and from the built-in disk. The HDD 103 is used as a secondary storage device of the computer 100. The HDD 103 stores an OS program, application programs, and various data. Note that a semiconductor storage device such as a flash memory can also be used as the secondary storage device. The HDD 103 has the function of the storage unit 14 shown in FIG. 1, for example, and stores circuit simulation data D1, layout data including a dummy pattern, and the like. For example, the HDD 103 also stores a simulation tool for thermal analysis of the semiconductor integrated circuit.

  A monitor 104 a is connected to the graphic processing device 104. The graphic processing device 104 displays an image on the screen of the monitor 104a in accordance with a command from the CPU 101. Examples of the monitor 104a include a display device using a CRT (Cathode Ray Tube) and a liquid crystal display device.

  A keyboard 105 a and a mouse 105 b are connected to the input interface 105. The input interface 105 transmits signals sent from the keyboard 105a and the mouse 105b to the CPU 101. Note that the mouse 105b is an example of a pointing device, and other pointing devices can also be used. Examples of other pointing devices include a touch panel, a tablet, a touch pad, and a trackball.

  The optical drive device 106 reads data recorded on the optical disc 106a using laser light or the like. The optical disk 106a is a portable recording medium on which data is recorded so that it can be read by reflection of light. The optical disk 106a includes a DVD (Digital Versatile Disc), a DVD-RAM, a CD-ROM (Compact Disc Read Only Memory), a CD-R (Recordable) / RW (ReWritable), and the like.

  The communication interface 107 is connected to the network 107a. The communication interface 107 transmits / receives data to / from other computers or communication devices via the network 107a.

With the hardware configuration as described above, the processing functions of the present embodiment can be realized.
As described above, the processing functions of the present embodiment can be realized by a computer. In this case, a program describing the processing contents of the functions that the design apparatus 10 should have is provided. By executing the program on a computer, the above processing functions are realized on the computer. The program describing the processing contents can be recorded on a computer-readable recording medium. Examples of the computer-readable recording medium include a magnetic storage device, an optical disk, a magneto-optical recording medium, and a semiconductor memory. Examples of the magnetic storage device include a hard disk device (HDD), a flexible disk (FD), and a magnetic tape. Optical discs include DVD, DVD-RAM, CD-ROM / RW, and the like. Magneto-optical recording media include MO (Magneto-Optical disk).

  When distributing the program, for example, portable recording media such as a DVD and a CD-ROM in which the program is recorded are sold. It is also possible to store the program in a storage device of a server computer and transfer the program from the server computer to another computer via a network.

  The computer that executes the program stores, for example, the program recorded on the portable recording medium or the program transferred from the server computer in its own storage device. Then, the computer reads the program from its own storage device and executes processing according to the program. The computer can also read the program directly from the portable recording medium and execute processing according to the program. In addition, each time a program is transferred from a server computer connected via a network, the computer can sequentially execute processing according to the received program.

  In addition, at least a part of the above processing functions can be realized by an electronic circuit such as a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), or a PLD (Programmable Logic Device).

  As described above, one aspect of the semiconductor integrated circuit design apparatus and the semiconductor integrated circuit design method of the present invention has been described based on the embodiments. However, these are merely examples, and the present invention is not limited to the above description. .

The following additional notes are further disclosed with respect to the plurality of embodiments described above.
(Appendix 1) A thermal analysis unit that performs thermal analysis from data of a semiconductor integrated circuit to be designed and calculates a temperature distribution;
A vector generation unit that generates a vector according to the calculated temperature gradient of the temperature distribution;
Generating a dummy pattern according to the generated vector and adding the dummy pattern to the layout data of the semiconductor integrated circuit;
An apparatus for designing a semiconductor integrated circuit, comprising:

  (Additional remark 2) The said dummy pattern production | generation part produces | generates the said dummy pattern by connecting the several other dummy pattern for the planarization of the layer of the said semiconductor integrated circuit according to the said vector. The semiconductor integrated circuit design apparatus according to appendix 1.

  (Additional remark 3) The said dummy pattern production | generation part removes the part which interferes with the circuit pattern of the said semiconductor integrated circuit in the said dummy pattern produced | generated according to the said vector, The semiconductor integrated circuit of Additional remark 1 characterized by the above-mentioned. Design equipment.

  (Additional remark 4) The said dummy pattern production | generation part changes the number or thickness of the said dummy pattern according to the magnitude | size of the said vector, The semiconductor integrated circuit of any one of Additional remark 1 thru | or 3 characterized by the above-mentioned. Design equipment.

  (Additional remark 5) The said vector production | generation part divides | segments the said temperature distribution into the area | region for every fixed magnitude | size, and produces | generates the said vector from the temperature gradient in the said area | region, Any one of Additional remark 1 thru | or 4 characterized by the above-mentioned. For designing a semiconductor integrated circuit.

  (Supplementary note 6) The design of the semiconductor integrated circuit according to Supplementary note 5, wherein the vector generation unit, when a plurality of the vectors can be generated in one region, sets the largest vector as the vector of the region. apparatus.

  (Additional remark 7) When the said vector production | generation part can produce | generate the said several vector in one said area | region, it divides | segments the said area | region into several area | regions, and produces | generates the said vector for every divided area | region, It is characterized by the above-mentioned. The apparatus for designing a semiconductor integrated circuit according to appendix 5.

  (Additional remark 8) When the temperature gradient is not seen in the said area | region, the said vector production | generation part expands the said area | region until it includes the area | region where the said vector is produced | generated, and uses the said vector, the vector of the expanded area | region 8. The semiconductor integrated circuit design apparatus according to any one of appendices 5 to 7, wherein:

(Appendix 9) Thermal analysis is performed from the data of the semiconductor integrated circuit to be designed, the temperature distribution is calculated,
Generate a vector according to the calculated temperature gradient of the temperature distribution,
A method for designing a semiconductor integrated circuit, wherein a dummy pattern is generated according to the generated vector and added to layout data of the semiconductor integrated circuit.

(Appendix 10) Thermal analysis is performed from the data of the semiconductor integrated circuit to be designed, the temperature distribution is calculated,
Generate a vector according to the calculated temperature gradient of the temperature distribution,
A program for causing a computer to execute a process of generating a dummy pattern according to the generated vector and adding the dummy pattern to the layout data of the semiconductor integrated circuit.

DESCRIPTION OF SYMBOLS 10 Design apparatus 11 Thermal analysis part 12 Vector generation part 13 Dummy pattern generation part 14 Storage part D1 Circuit simulation data D2 Layout data (with dummy pattern)

Claims (5)

Thermal analysis from the data of the semiconductor integrated circuit to be designed to calculate the temperature distribution,
A vector generation unit that generates a vector according to the calculated temperature gradient of the temperature distribution;
Generating a dummy pattern according to the generated vector and adding the dummy pattern to the layout data of the semiconductor integrated circuit;
An apparatus for designing a semiconductor integrated circuit, comprising:   The dummy pattern generation unit generates the dummy pattern by connecting a plurality of other dummy patterns for planarizing a layer of the semiconductor integrated circuit according to the vector. 2. The semiconductor integrated circuit design apparatus according to 1.   The apparatus for designing a semiconductor integrated circuit according to claim 1, wherein the dummy pattern generation unit removes a portion of the dummy pattern generated according to the vector that interferes with a circuit pattern of the semiconductor integrated circuit.   4. The semiconductor integrated circuit design device according to claim 1, wherein the dummy pattern generation unit changes the number or the thickness of the dummy patterns according to the size of the vector. 5. The processor performs thermal analysis from the data of the semiconductor integrated circuit to be designed, calculates the temperature distribution,
The processor generates a vector corresponding to the calculated temperature gradient of the temperature distribution;
A design method of a semiconductor integrated circuit, wherein the processor generates a dummy pattern according to the generated vector and adds the dummy pattern to layout data of the semiconductor integrated circuit.

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