JP2000124320A - Method and device for verifying layout - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently and quickly verify the layout of an IC which is operated by a plurality of power supply voltages. SOLUTION: A method and device is provided with a breakdown voltage information addition means 41, that adds a power supply voltage value for operating a element to a pad part connected to the element, an element recognition/isoelectric tracking means 42 that allows layout data, where power voltage information is added to be subjected to the recognition of the element and isoelectric tracking for extracting the circuit information of the layout, and extracts the information of the breakdown voltage of an element part, a dummy layer generation means 43 that generates dummy layer information for each breakdown voltage according to the information of the breakdown voltage, a dummy layer information addition means 45 that adds dummy layer information to the layout data, DRC(design rule checking) execution means 34 and 35 that verify design rules, an error information addition means 38 that adds DRC error information to the layout data where the dummy layer data is added, and a display means 39 that combines the layout data, the dummy layer information, and the error information for displaying.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout verification method and a layout verification apparatus, and more particularly to a layout verification method and layout verification for designing an IC (simulated integrated circuit) in which elements operated by a plurality of different power supply voltages are mixed. Related to the device.

[0002]

2. Description of the Related Art FIG. 10 shows a chip layout of an IC in which elements operated by power supplies having different voltage values are mixed. In this IC 1, the element 10a operates at the power supply voltage Va, and the element 10b operates at the power supply voltage Vb (Va <V
b). In this case, element 10a has a withstand voltage corresponding to voltage Va, while element 10b
It is necessary to have a withstand voltage corresponding to b.

[0003] The reason is that, in order to increase the breakdown voltage, it is necessary to increase the dimensions of individual components (configuration regions) in the element, the distance between them, and the distance between the elements. If the element 10a operating at the voltage Va is designed with the same withstand voltage as the element 10b at the higher operating voltage Vb, the element 10a becomes unnecessarily large and the elements are arranged more than necessary. ,
If the element 10b having a higher operating voltage is designed to have the same dimensions as the element 10a having a lower operating voltage, the element 10b cannot obtain a sufficient withstand voltage. This is because it is not preferable.

In general, elements having different withstand voltages have the same polygon data shape and overlap, and are often different only in dimensions. For example, the elements 10a and 10b in FIG. 10 have the same shape, but have different withstand voltages, so that the widths Aw and Bw of the layer 1 in each of the elements 10a and 10b, and the distance between the layers 1 and 2 The minimum allowable value of the design rule of the manufacturing apparatus is different between As and Bs and between the inclusion distances Ae and Be between the layers 2 and 3.

In general, at the time of designing an IC, the dimensions of each element and the distance between elements, that is, I
Verify whether the layout of C is appropriate.

FIG. 11 shows a schematic configuration of a conventional IC design layout verification apparatus. This layout verification device
Storage unit 11 storing layout data, power supply voltage Va
A storage unit 12 storing design rules based on the withstand voltage for the power supply voltage Vb, a storage unit 13 storing design rules based on the withstand voltage for the power supply voltage Vb, and a geometric design rule whose layout based on the layout data satisfies the constraints of the manufacturing apparatus. DRC (design rules,
(Checking) means (hereinafter referred to as DRC executing means) 14 and 15, storage units 16 and 17 for storing DRC error information obtained as a result of verification by the DRC executing means 14 and 15, errors in layout data It comprises a means for adding information (hereinafter referred to as error information adding means) 18 and a display means 19 for displaying a layout in which layout data and error information are combined.

[0007] Each of the storage units 11, 12, 13, 16, 1
7 is provided in one or more storage devices. Also D
Although the RC executing means 14 and 15 are divided into two for convenience of explanation, they may be the same means.

In a conventional layout verification apparatus, when verifying the layout of an IC operated by a single power supply voltage, elements are determined based on the shape and overlap of polygon data, and the type of the element is determined. Then, the DRC execution means 14 (15) checks whether the layout data satisfies the geometric design rule. Then, the error information is added to the layout by the error information adding means 18, and the error information is displayed on the display means 19.

On the other hand, when the layout verification of an IC operating at a plurality of power supply voltages is performed by a conventional layout verification device, as described above, elements having different withstand voltages (for example, FIG.
Since the elements 10a and 10b) often have the same polygon data shape and overlap, it is not easy to identify elements having different withstand voltages and identify the withstand voltage of each element. Therefore, conventionally, when designing an IC that operates with a plurality of power supply voltages, that is, an IC in which a plurality of withstand voltages is set, the check value is changed for each withstand voltage for the same layout and the DR value is changed.
C is running.

[0010]

However, a check value for an element having a high withstand voltage, that is, an unnecessarily large check value for an element having a small withstand voltage and a distance between such elements which may be small in size, that is, more than necessary. An error occurs in a portion where a check is performed using a large check value. Then, as described above, whether the error is a pseudo error due to an excessively large check value or a real error is determined by checking the layout diagram displayed on the display unit 19 and the operating voltage of each element. It takes an enormous amount of time to confirm the layout verification result because the comparison of the dimensions indicated by the error with the design withstand voltage is performed at a glance while comparing it with the circuit diagram etc. There was a problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem. In verifying the layout of an IC that operates with a plurality of power supply voltages, the present invention efficiently checks a pseudo error caused by a difference in breakdown voltage. An object of the present invention is to provide a layout verification method that can complete the DRC result check in a shorter time than in the related art.

Further, according to the present invention, in an IC layout verification apparatus, when verifying the layout of an IC operating with a plurality of power supply voltages, a pseudo error generated due to a difference in breakdown voltage can be efficiently confirmed. D in less time than
It is another object of the present invention to obtain a layout verification device that can complete the result check of the RC.

[0013]

In order to achieve the above object, the present invention provides a method for verifying the layout of an integrated circuit in which elements operating at different voltages are mixed, based on the operating voltage of each element. And generating a dummy layer according to the operating voltage, and displaying the generated dummy layer in a manner superimposed on the layout diagram.

According to the present invention, a dummy layer corresponding to the withstand voltage of the element is superimposed and displayed on the layout diagram, so that a pseudo error generated at the time of design rule verification due to a difference in withstand voltage is efficiently confirmed. be able to.

In the present invention, in the step of generating the dummy layer, the dummy layer is connected to a power supply of a different voltage based on information of a voltage applied to a pad connected to the element and wiring information of the same potential. The method includes a step of extracting breakdown voltage information of the element and a step of generating a dummy layer for each breakdown voltage based on the breakdown voltage information.

According to the present invention, the withstand voltage information is extracted from the wiring information of the layout and the voltage information added to the pad portion, and a dummy layer for each withstand voltage is automatically generated based on the extracted withstand voltage information. Therefore, it is possible to easily visually confirm an error portion in which a value to be checked for a withstand voltage changes in an area surrounded by a dummy layer for each withstand voltage.

Alternatively, in the present invention, the step of generating a dummy layer includes the step of connecting elements or connections between elements to a layout to be verified based on a circuit diagram in which operating voltage information is added to symbols of the circuit diagram. A step of verifying correctness, a step of extracting withstand voltage information of the elements in the layout diagram based on the verification result and the operating voltage information added to the symbol, and a step of forming a dummy layer for each withstand voltage based on the withstand voltage information. Generating step.

According to the present invention, the withstand voltage information is extracted from the voltage information added to the element symbol, and a dummy layer for each withstand voltage is automatically generated based on the extracted withstand voltage information. In addition, it is possible to easily visually confirm an error portion in which a value to be checked for a withstand voltage changes in an area surrounded by a dummy layer for each withstand voltage.

In the present invention, a design rule that can change the check value depending on the breakdown voltage in the area surrounded by the dummy layer in the layout diagram is used, and the check value is assigned to the element or portion to be checked. Verification that the design rule is satisfied may be performed while changing according to the withstand voltage.

According to the present invention, after the dummy layer for each withstand voltage is arranged on the layout, the design rule that can change the check value depending on the withstand voltage in the area surrounded by the dummy layer is used to overlap the dummy layer. In the area, the check values such as the layer width, interval and inclusion distance are automatically changed according to the withstand voltage, and the verification is performed.
The occurrence of spurious errors is avoided.

According to another aspect of the present invention, there is provided a layout verifying apparatus for verifying a layout of an integrated circuit in which elements operating at different voltages are mixed, wherein each of the elements has an operating voltage based on the operating voltage of the element. There is provided a means for generating a dummy layer and a means for displaying the generated dummy layer so as to overlap the layout diagram.

According to the present invention, a dummy layer corresponding to the withstand voltage of the element is superimposed and displayed on the layout diagram, so that a pseudo error generated at the time of design rule verification due to a difference in withstand voltage is efficiently confirmed. be able to.

[0023]

Embodiments of a layout verification method and a layout verification apparatus according to the present invention will be described below in detail with reference to the drawings.

Embodiment 1 FIG. 1 is a block diagram illustrating a schematic configuration of a layout verification device according to a first embodiment of the present invention, and FIG. 2 is a layout diagram illustrating a part of a display example of a verification result by the layout verification device. The layout verification device includes a storage unit 31 storing layout data, a storage unit 32 storing design rules at a withstand voltage for a power supply voltage Va, a storage unit 33 storing a design rule at a withstand voltage for a power supply voltage Vb, and DRC execution means. 34,
35, storage units 36 and 37 for storing DRC error information obtained by executing DRC, error information adding means 38,
And display means 39.

Each of these storage units 31, 32, 33, 3
6, 37 and means 34, 35 are the same as the conventional storage units 11, 12, 13, 16, 17 and means 14, 15 shown in FIG. The error information adding means 38 and the display means 39 will be described later.

The layout verifying apparatus includes a withstand voltage information adding unit 41, an element recognizing and same potential tracking unit 42, a dummy layer generating unit 43, a storage unit 44 for storing withstand voltage-specific dummy layer information, and a dummy layer information adding unit 45. It has.

The withstand voltage information adding means 41 includes a pad portion (for example, the pad portions 21a and 21b of FIG. 2) connected to an element (for example, the devices 20a and 20b of FIG. 2) in the layout data.
b) has a function of adding a value of a power supply voltage (Va, Vb) for operating the element, for example, which serves as a basis for information on the breakdown voltage. Information on the power supply voltage for each element is input, for example, from a key input unit (not shown) connected to the layout verification device.

The element recognizing and equipotential tracking means 42 extracts the circuit information of the layout by performing element recognizing and equipotential tracking on the layout data to which the power supply voltage information is added, and extracts the potential from the pad portion. It has a function of extracting information on the breakdown voltage of the element section by tracking.

The dummy layer generating means 43 has a function of generating withstand voltage-specific dummy layer information from the extracted withstand voltage information. The generated dummy layer information is stored in the storage unit 4
4 is stored. The dummy layer information adding unit 45 has a function of adding the dummy layer information stored in the storage unit 44 to the layout data.

The error information adding means 38 has a function of adding DRC error information to layout data to which dummy layer information has been added. The display means 39 has a function of displaying a layout in which layout data, dummy layer information, and error information are combined.

Each of the storage units 31, 32, 33, 36, 3
7, 44 are provided in one or two or more storage devices.
When the number of power supply voltages having different magnitudes is three or more, a storage unit is provided for storing a design rule with a withstand voltage for each power supply voltage. Is provided. The DRC executing means includes:
The same means may be used without being divided for each power supply voltage.

Next, the operation of the layout verification apparatus will be described with reference to FIG. When verification of the layout is started and, for example, information on the voltages (power supply voltages Va and Vb) applied to the pad section is input via the key input section or the like (step S1), the withstand voltage information adding means 41 sets the pad section to the pad section. Then, information on the voltage applied thereto is added (step S2).

Next, the element recognition and potential tracking means 42
Perform element recognition and same potential tracking on the layout diagram,
Based on the information on the applied voltage added to the pad section and the wiring information on the same potential, the withstand voltage of the element connected to the power supply of each power supply voltage Va, Vb is determined, and the withstand voltage information is extracted (step S3).

Next, the dummy layer generating means 43 generates a dummy layer for each withstand voltage based on the extracted withstand voltage information (step S4). Dummy layer information adding means 45
Arranges the generated dummy layers for each withstand voltage on the layout (step S5). DRC execution means 34,
35 sequentially verifies whether the layout satisfies the design rule with respect to the power supply voltage Va and the power supply voltage Vb (steps S6 and S7), and outputs error information adding means 38.
Adds the DRC error information to the layout in which the dummy layers are arranged (step S8). Then, the display means 39 displays the layout to which the dummy layer information and the error information are added (step S9), and ends.

In FIG. 2 showing a display example, the dummy layers 22a and 22b are displayed so as to overlap the elements 20a and 20b, respectively. Dummy layers 22a, 22
b may be shown in a different pattern for each power supply voltage as shown in FIG. 2, or may be color-coded instead of the different pattern.

Then, the inspector performing the verification work visually checks the layout display shown in FIG. 2 and checks an error portion where the value to be checked for the withstand voltage changes in the area where the dummy layers for each withstand voltage overlap. .

According to the first embodiment, withstand voltage-specific information is extracted from the layout wiring information and the power supply voltage information added to the pad portion, and a withstand-voltage-specific dummy layer is automatically generated based on the information. Since it is superimposed and displayed on the layout diagram, an error portion where the value to be checked for the withstand voltage changes in the area surrounded by the dummy layer for each withstand voltage can be easily confirmed visually.

Therefore, when the inspector checks whether the error information of the layout verification result is a pseudo error or a real error, the dummy layer can determine the withstand voltage of the element only by looking at the displayed layout diagram. Therefore, there is no need to compare the circuit diagram with the withstand voltage information, and the time required for confirming the result of the layout verification can be reduced.

Embodiment 2 FIG. 4 is a block diagram showing a schematic configuration of a layout verification device according to a second embodiment of the present invention. FIG. 5 shows a part of a display example of a verification result by the layout verification device together with a corresponding circuit diagram. It is a layout diagram. The difference between the layout verification apparatus of the second embodiment and the first embodiment shown in FIG.
The difference is that a withstand voltage information adding unit 51, a storage unit 52 for storing circuit diagram data, and a circuit diagram / layout information comparing unit 53 are provided instead of the withstand voltage information adding unit 41 and the element recognition and same potential tracking unit 42. Other configurations and functions are the same as those of the first embodiment, and thus the same reference numerals are given and the description will be omitted.

The withstand voltage information adding means 51 causes the element symbol (for example, the transistor symbols 23a and 23b shown in the upper part of FIG. 5) in the circuit diagram data to operate, for example, the element as the basis of the withstand voltage information. To add the value of the power supply voltage (Va, Vb) for the purpose. Information on the power supply voltage for each element is input, for example, from a key input unit (not shown) connected to the layout verification device.

The circuit diagram / layout information comparison means 53
Based on the circuit diagram data and the layout data, an LVS (Layout Versus Schematic) for verifying whether or not the elements and the connection between the elements are correctly realized is executed, and the equivalent is obtained from the layout information obtained as a result. It has a function of extracting the information of the withstand voltage added to the element symbol on the simple circuit diagram.

Each of the storage units 31, 32, 33, 36, 3
7, 44, and 52 are provided in one or more storage devices. When the number of power supply voltages having different magnitudes is three or more, a storage unit is provided for storing a design rule with a withstand voltage for each power supply voltage. Is provided. The DRC executing means may be the same means without being divided for each power supply voltage.

Next, the operation of the layout verification apparatus will be described with reference to FIG. Verification of the layout is started. For example, the power supply voltages Va,
When the information on Vb is input via the key input unit or the like (step S11), the withstand voltage information adding means 51 adds information on the operating voltage (power supply voltage Va, Vb) of the element to each element symbol (step S11). S12).

When the circuit diagram data is stored in the storage unit 52 in advance, operating voltage information may be added to each symbol as element information. Next, the circuit diagram / layout information comparing means 53 executes LVS on the circuit diagram and the target layout, and determines the withstand voltage of the element on the layout diagram side from the result and the power supply voltage information added to the circuit diagram. Then, withstand voltage information is extracted (step S13).

Next, the dummy layer generating means 43 generates a dummy layer for each withstand voltage based on the extracted withstand voltage information (step S14). Dummy layer information adding means 4
5 arranges the generated dummy layer for each withstand voltage on the layout (step S15).

The DRC executing means 34 and 35 sequentially verify whether or not the layout satisfies the design rule with respect to the power supply voltage Va and the power supply voltage Vb (steps S16 and S17). Adds the DRC error information to the layout in which the dummy layers are arranged (step S18). And display means 39
Displays a layout to which dummy layer information and error information are added (step S19), and ends.

In FIG. 5 showing a display example, the dummy layers 22a and 22b are displayed so as to overlap the elements 20a and 20b, respectively. Note that what is actually displayed is the “layout diagram” portion on the lower side of FIG.
Is not displayed on the upper side of the "circuit diagram".

Then, the inspector who is performing the verification work visually checks the layout display shown in FIG. 5 and confirms an error portion where the value to be checked for the withstand voltage changes in the area where the dummy layers for each withstand voltage overlap. .

According to the second embodiment, breakdown voltage-specific information is extracted from the power supply voltage information added to the element symbol, and a breakdown-voltage-specific dummy layer is automatically generated based on the information. Because they are displayed in layers,
An error portion where a value to be checked for a withstand voltage changes in an area surrounded by a dummy layer for each withstand voltage can be easily confirmed visually.

Therefore, when the inspector checks whether the error information of the layout verification result is a pseudo error or a real error, the dummy layer can determine the withstand voltage of the element only by looking at the displayed layout diagram. Therefore, there is no need to compare the circuit diagram with the withstand voltage information, and the time required for confirming the result of the layout verification can be reduced.

Embodiment 3 FIG. FIG. 7 is a block diagram showing a schematic configuration of a layout verification device according to the third embodiment of the present invention. The layout verification apparatus according to the third embodiment includes a dummy layer generation unit 61, a storage unit 62 for storing withstand voltage-specific dummy layer information, and a dummy layer information addition unit 6.
3. A storage unit 64 storing layout data, a storage unit 65 storing a design rule capable of changing a check value depending on withstand voltage in an area surrounded by a dummy layer, a DRC execution unit 66, and a DRC error obtained by executing the DRC. A storage unit 67 for storing information, an error information adding unit 68, and a display unit 69 are provided.

The storage sections 64 and 67 are the same as the conventional storage sections 11 and 16 shown in FIG. 10, respectively, and the storage section 62 and the means 63 and 69 are the same as those shown in FIG. Storage unit 44 of Embodiment 1 and each unit 4
The description is omitted because it is the same as 5 and 39.

The dummy layer generating means 61 has a function of extracting the information of the breakdown voltage and generating the dummy layer information for each breakdown voltage from the information of the breakdown voltage.
Withstand voltage information adding means 41, element recognition, same potential tracking means 4
2 and the function of the dummy layer generating means 43.
Alternatively, the dummy layer generating means 61 has the functions of the withstand voltage information adding means 51, the circuit diagram / layout information comparing means 53, and the dummy layer generating means 43 of the second embodiment.

The DRC execution means 66 uses a design rule that can change the check value depending on the withstand voltage in the area surrounded by the dummy layer, and applies a check to the element or part to be checked according to the withstand voltage corresponding to the element or part. And has a function of executing DRC. Therefore, the pseudo error as described above does not occur.

The error information adding means 68 has a function of adding error information not including pseudo error information of the DRC to the layout data to which the dummy layer information has been added.

Each of the storage units 62, 65, 65, 67
It is provided in one or more storage devices.

Next, the operation of the layout verification apparatus will be described with reference to FIG. When the layout verification is started, the dummy layer generation unit 61 extracts the withstand voltage information of the element as in, for example, steps S1 to S4 of the first embodiment or steps S11 to S14 of the second embodiment, and based on the extracted information. Then, a dummy layer for each withstand voltage is generated (step S21). Dummy layer information adding means 63
Arranges the generated dummy layers for each withstand voltage on the layout (step S22).

The DRC executing means 66 uses a design rule which can change the check value depending on the breakdown voltage in the area surrounded by the dummy layer, and verifies whether the layout satisfies the design rule according to the breakdown voltage. (Step S
23). Then, the error information adding means 68 adds the error information of the DRC to the layout on which the dummy layer is arranged (step S24), displays it on the display means 69 (step S25), and ends.

According to the third embodiment, for example, after the dummy layers for each withstand voltage determined in the first or second embodiment are arranged on the layout, the withstand voltage in the area surrounded by the dummy layers is increased. The DRC is executed using a design rule that can change the check value, and in the area overlapping the dummy layer, the check values such as the layer width, the interval, and the inclusion distance are automatically changed according to the withstand voltage, and the verification is performed. No false error occurs. Therefore, errors in checking errors can be prevented, and errors can be accurately confirmed in a very short time. Also, since it is not necessary to execute the DRC for each different withstand voltage,
DRC execution time is reduced.

In the above, the present invention can be variously modified. For example, each storage unit may be a magnetic disk device such as a hard disk device or a magneto-optical disk device. Further, each means may be realized by software or hardware.

Further, according to the present invention, based on the arrangement information of the dummy layers for each withstand voltage determined as in the first or second embodiment, the separation width between the elements shown in FIG. The invention can also be applied to finding a layout portion having an insufficient withstand voltage at an interval between the layers. By doing so, it is possible to prevent a check error by automatically changing the check values of the layer width and the interval outside the area surrounded by the dummy layer without visually confirming, so that the DRC can be executed accurately. be able to.

[0062]

As described above, according to the layout verification method of the present invention, a dummy layer corresponding to the withstand voltage of an element is superimposed and displayed on a layout diagram. The pseudo error that occurs can be efficiently confirmed, and the result of layout verification can be completed in a shorter time than before.

According to the layout verification method of the present invention, withstand voltage information is extracted from the wiring information of the layout and the voltage information added to the pad portion, and a dummy layer for each withstand voltage is automatically generated based on the information. Since it is superimposed on the layout diagram, it is possible to easily visually confirm an error portion in which the value to be checked with respect to the withstand voltage changes in an area surrounded by the dummy layer for each withstand voltage, and to provide a pseudo error. And a real error can be quickly determined, and the time required to confirm the layout verification result can be reduced.

According to the layout verification method of the present invention, withstand voltage information is extracted from the voltage information added to the element symbols, and a dummy layer for each withstand voltage is automatically generated based on the extracted withstand voltage information. Since it is displayed in an overlapping manner, it is possible to easily visually confirm an error portion where a value to be checked with respect to a withstand voltage changes in an area surrounded by a dummy layer for each withstand voltage, and a pseudo error and a real error can be confirmed. Can be promptly determined, and the time required for confirming the layout verification result can be reduced.

Further, according to the layout verification method of the present invention, after a dummy layer for each withstand voltage is arranged on the layout, a design rule that can change the check value depending on the withstand voltage in an area surrounded by the dummy layer is used. Accordingly, in the area overlapping the dummy layer, the check values such as the layer width, the interval, and the inclusion distance are automatically changed according to the withstand voltage, and the verification is performed, so that a pseudo error does not occur. Therefore, errors in checking errors can be prevented, and errors can be accurately confirmed in a very short time.
Further, since it is not necessary to execute the verification of the design rule for each different withstand voltage, the verification time of the design rule is reduced.

According to the layout verifying apparatus of the present invention, a dummy layer corresponding to the withstand voltage of the element is superimposed and displayed on the layout diagram, so that a pseudo error generated at the time of design rule verification due to a difference in withstand voltage is confirmed. Can be performed efficiently, and the result of layout verification can be confirmed in a shorter time than before.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a layout verification device according to a first embodiment of the present invention.

FIG. 2 is a layout diagram illustrating a part of a display example of a layout verification result according to the first embodiment;

FIG. 3 is a flowchart illustrating an example of a layout verification procedure according to the first embodiment;

FIG. 4 is a block diagram illustrating a schematic configuration of a layout verification device according to a second embodiment of the present invention.

FIG. 5 is a layout diagram showing a part of a display example of a layout verification result according to the second embodiment.

FIG. 6 is a flowchart illustrating an example of a layout verification procedure according to the second embodiment;

FIG. 7 is a block diagram illustrating a schematic configuration of a layout verification device according to a third embodiment of the present invention.

FIG. 8 is a flowchart illustrating an example of a layout verification procedure according to the third embodiment;

FIG. 9 explains that, based on the determined dummy layer arrangement information for each withstand voltage, a layout portion having an insufficient withstand voltage can be found at an interval between layers with respect to an element-to-element separation width. FIG. 3 is a schematic diagram illustrating an IC chip layout.

FIG. 10 is a schematic diagram showing a chip layout of an IC in which elements operated by power supplies having different voltage values are mixed.

FIG. 11 is a block diagram showing a schematic configuration of a conventional IC design layout verification apparatus.

[Explanation of symbols]

Va, Vb power supply voltage, 20a, 20b element, 21
a, 21b pad section, 22a, 22b dummy layer, 23a, 23b symbol, 31, 64 storage section for storing layout data, 32 storage section for storing design rules based on withstand voltage for power supply voltage Va, 33 withstand voltage for power supply voltage Vb Storage unit that stores the design rules in
34, 35, 66 DRC executing means, 36, 37, 67
Storage section for storing DRC error information, 38, 68 error information adding means, 39, 69 display means, 41, 51
Withstand voltage information adding means, 42 element recognition, same potential tracking means, 43, 61 dummy layer generating means, 44, 62
Storage unit for storing breakdown voltage-specific dummy layer information, 45, 63
Dummy layer information adding means, 52 Storage section storing circuit diagram data, 53 Circuit diagram / layout information comparing section, 65 Storage section storing design rules capable of changing a check value depending on withstand voltage in an area surrounded by a dummy layer.

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Hiroyuki Takeno 2-3-2 Marunouchi, Chiyoda-ku, Tokyo F-term (reference) 5F038 BE09 CA18 DT10 DT19 EZ20 5F064 DD26 DD39 DD46 HH10 HH14

Claims (5)

[Claims] In performing a layout verification of an integrated circuit in which elements operating at different voltages are mixed, a step of generating a dummy layer corresponding to the operating voltage for each element based on the operating voltage of the element; Displaying the generated dummy layer in a manner superimposed on the layout diagram. 2. The step of generating the dummy layer includes: information on a voltage applied to a pad connected to an element;
A step of extracting withstand voltage information of elements connected to power supplies of different voltages based on wiring information of the same potential; and a step of generating a dummy layer for each withstand voltage based on the withstand voltage information. 2. The layout verification method according to claim 1, wherein: 3. The step of generating a dummy layer includes: verifying that elements or connections between elements are correct for a layout to be verified based on a circuit diagram in which operating voltage information is added to a symbol of the circuit diagram. A step of verifying, a step of extracting withstand voltage information of an element in a layout diagram based on the verification result and the operating voltage information added to the symbol, and a step of generating a dummy layer for each withstand voltage based on the withstand voltage information The layout verification method according to claim 1, further comprising: 4. A design rule that can change a check value according to a withstand voltage in an area surrounded by a dummy layer in a layout diagram, and for a device or a portion to be checked, the check value is set to a withstand voltage of the device or the portion. 4. The layout verification method according to claim 1, wherein the verification is performed while conforming to the design rule while changing the layout. 5. A layout verification apparatus for verifying a layout of an integrated circuit in which elements operating at different voltages are mixed, wherein a dummy layer corresponding to the operation voltage is provided for each element based on the operation voltage of the element. A layout verification device comprising: a generating unit; and a unit configured to display the generated dummy layer so as to overlap the layout diagram.