JP2012238144A - Layout verification device, layout verification method, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for layout verification, particularly DRC verification carried out following addition of a partial change to post-verification layout pattern data, of omitting time for DRC verification of a portion outside a verification target to shorten time for DRC verification such as an antenna ratio.SOLUTION: In DRC verification carried out following addition of a partial change to post-verification layout pattern data, a verification target portion of the DRC verification is identified from the changed portion by means of equipotential tracking. Specifically, a differential figure of pre- and post-change layout pattern data is extracted to extract a changed node from the differential figure. Further, equipotential numbers are added to the post-change layout pattern, and a verification target portion having the same equipotential number as the changed node is extracted with reference to the equipotential numbers. Further, the DRC verification of an antenna ratio is performed on the extracted verification target portion.

Description

  The present invention relates to layout verification of a semiconductor integrated circuit, and more particularly to verification when a layout change is partially performed.

  In recent years, with the miniaturization and enlargement of a semiconductor integrated circuit (LSI: Large Scale Integration), a large amount of layout pattern data is input for design rule check (DRC) verification.

  For this reason, the time required for DRC verification of LSIs has become longer, which has a large effect on cost and delivery time during product development, and the need to shorten the DRC verification time for the early market introduction of LSIs has increased. I came.

  In general, when an error or a change occurs after layout verification, it is necessary to repeat the process of correcting the layout and executing DRC verification again. This further increases the time required for DRC verification of the LSI. .

  In particular, in DRC verification, it is necessary to perform equipotential tracking for each element and wiring in DRC verification using equipotential tracking as compared to DRC verification such as width and interval. It takes time to run.

  As a related technique, Japanese Patent Laid-Open No. 2003-337843 discloses a layout verification method and verification program for a semiconductor integrated circuit. This related technology aims to shorten the time for re-DRC verification when a partial change is made to verified layout pattern data, and the minimum number of peripherals that may cause an error due to the change. Perform DRC verification only on the region.

FIG. 1 is a diagram illustrating a configuration of a layout verification apparatus that performs DRC verification of related technology.
In FIG. 1, layout pattern data of an integrated circuit to be changed is stored in a pre-change layout file 1. The layout pattern data stored in the pre-change layout file 1 is data that has been confirmed to have no error in layout verification. The designer uses the layout editor 2 to partially change or modify the layout pattern of the integrated circuit. The post-change layout file 3 stores layout pattern data obtained by partially changing or modifying the layout pattern data stored in the pre-change layout file 1. The DRC execution control unit 4 sets a verification target area in accordance with the DRC execution control program stored in the program memory 5, and executes DRC verification based on the check items and check dimensions stored in the DRC check item file 6. When an error is detected, error information is generated, and based on the error information, a DRC result file 7 such as an error report and an error flag displayed on the layout pattern is output.

  The operation of the related art layout verification apparatus in FIG. 1 will be described with reference to FIGS. 2 and 3 to 5. FIG. 2 is a flowchart showing the DRC verification method of the related art. 3 to 5 are diagrams schematically showing the processing results of the flowchart of FIG.

(1) Step S1
Next, the layout verification apparatus changes the layout pattern data before the change. FIG. 3 shows the layout pattern data after the change.

(2) Step S2
Next, the layout verification apparatus compares the layout pattern data before and after the change, and detects a mismatched portion as a changed area. The change area 21 in FIG. 3 is the change area detected in step S2.

(3) Step S3
Next, the layout verification apparatus sets a verification target area. Specifically, the outer shape of the change area 21 of FIG. 3 extracted in step S2 is expanded outward by a predetermined dimension to set the verification target area 22 of FIG.

(4) Step S4
Next, the layout verification apparatus executes DRC verification of the verification target area 22. If an error is detected by DRC, error information including the coordinates, check items, mask layer, etc. is generated for the error location.

(5) Step S5
Next, the layout verification apparatus outputs the DRC result file 7 of FIG. If there is an error, error information is output. For example, as error information, an error flag is displayed and output superimposed on the layout pattern data as shown in FIG.

(6) Step S6
Next, the layout verification apparatus determines whether there is a true error based on the error information. If it is determined that there is a true error, the process returns to step S1, and the error location is corrected and changed using the layout editor 2 in FIG. 1 according to the operation of the designer. The layout file 3 is overwritten, a new change area 23 is extracted in step S2, and the subsequent flow is executed. If it is determined in step S6 that there is no true error, the DRC verification is terminated.

  Usually, the ratio of the gate area to the area of the metal wiring connected from the gate is called an antenna ratio, and when the antenna ratio exceeds a predetermined value, it is regarded as an antenna error. When the area of the metal wiring becomes larger than the gate area, it becomes easy to receive electrical damage. When an antenna error occurs, gate destruction due to the antenna effect may occur. In the semiconductor manufacturing process of the plasma (or ion beam) process, charges are accumulated in wiring that is connected to the gate electrode and not to the diffusion layer, and if this charge exceeds a certain amount, the gate oxidation is caused by electrical stress. The film deteriorates and the characteristics of the device fluctuate.

  In the related technology described above, a region in which layout pattern data is changed is an area to be verified that is expanded in four directions by the maximum check dimension, but in DRC verification that requires equipotential tracking, the change location affects The range covers a wide range considering the connection information.

  Further, in the above related technology, in the DRC verification performed after a partial change is made to the verified layout pattern data, only the periphery of the changed portion can be confirmed, so that the verification target area is set to the entire area of the layout pattern data. Must be set.

  Therefore, the method of confirming only the periphery of the changed part as in the related technique described above is, in some DRC verification such as the area ratio (antenna ratio) of the gate electrode and the gate oxide film using equipotential tracking, Cannot be used.

  As described above, the related technique has a problem in that the DRC verification time cannot be shortened because all areas of the layout are to be verified in the DRC verification.

  Hereinafter, as an example of DRC verification, DRC verification of antenna ratio is taken as an example, and the problems of the related art will be described in detail with reference to FIGS.

  The DRC verification of the antenna ratio is verification in which the ratio of the gate area to the metal area connected to the gate is measured, and pass / fail with respect to the ratio defined in the design rule is determined.

  In step S3 of FIG. 2, a verification target area is set.

  Specifically, the verification target area 22 of FIG. 4 is set by enlarging the outer shape of the change area 21 of FIG. 3 extracted in step S2 by a predetermined dimension outward.

  When performing the DRC verification of the antenna ratio, there is a possibility that the metal connected to the gate exists outside the set verification target region 22 in order to obtain the area ratio of the gate and the metal connected to the gate. Alternatively, it is necessary to set the verification target region 22 in all regions of the layout pattern data in consideration of the presence of the metal connected to the gate.

  FIG. 6 is a diagram showing an example of a verification region in consideration of equipotential tracking when the changed portion is in the gate portion.

  In this case, in order to set a verification area as a verification area where the changed part is enlarged by a predetermined size, the area ratio between the gate and the wiring connected from the gate is measured in the antenna ratio check.

  When considering the verification target part of the antenna ratio check by paying attention to the gate part of the changed part, 12 is the polysilicon mask layer constituting the gate, 16 is the first metal mask layer, and the second metal mask. The layer 17, the third metal mask layer 18, and the fourth metal mask layer 19 are in a range that requires re-verification of the antenna ratio.

  Since the range affected by the changed portion is wide when considering the range of the metal connected to the gate, it is not possible to use a method for confirming only the periphery of the changed portion as in the related art.

  Therefore, the DRC verification of the antenna ratio needs to re-verify the entire layout pattern data even if the layout pattern data is partially changed, and the turnaround time (TAT: Turn Around Time) of the antenna ratio DRC cannot be reduced.

  Patent Document 2 (Japanese Patent Laid-Open No. 2007-335498) discloses a semiconductor integrated circuit design method and a semiconductor integrated circuit formed using the same. This related technology is characterized by a function of automatically correcting an error part from a verification result. However, the antenna ratio check verification location cannot be limited.

  Japanese Patent Laid-Open No. 2008-015898 discloses a layout verification method and a layout verification apparatus. In this related technology, the verification target part is limited from the circuit operation.

JP 2003-337843 A JP 2007-335498 A JP 2008-015898 A

  An object of the present invention is to perform a DRC verification performed after a partial change is made to verified layout pattern data in a layout verification of a semiconductor integrated circuit. It is to provide a layout verification method for specifying a verification target portion of DRC verification related to an area ratio (antenna ratio) of a gate oxide film.

  A layout verification apparatus according to the present invention includes a program memory that stores a program, and a DRC execution control unit that executes DRC verification according to the program. The DRC execution control unit identifies the verification target part of the DRC verification using equipotential tracking from the changed part of the verified layout pattern data partially changed, and performs DRC verification on the verification target part. I do.

  A layout verification method according to the present invention is a layout verification method of a semiconductor integrated circuit implemented by a computer, and uses DRC using equipotential tracking from a changed part of verified layout pattern data partially changed. This includes specifying a verification target location for verification and performing DRC verification on the verification target location.

  A program according to the present invention is a program for causing a computer to execute the processing in the layout verification method. The program according to the present invention can be stored in a storage device or a storage medium.

  In the layout verification of the semiconductor integrated circuit, the DRC verification time for a portion not to be verified can be omitted, so that the time for DRC verification such as the antenna ratio can be shortened.

It is a block diagram of the layout verification apparatus which performs DRC verification of related technology. It is a flowchart which shows the DRC verification method of related technology. FIG. 3 is a diagram schematically showing the processing result in step S2 of FIG. 2 superimposed on a layout pattern. FIG. 3 is a diagram schematically showing a processing result in step S3 of FIG. 2 superimposed on a layout pattern. FIG. 3 is a diagram schematically showing the processing result in step S5 of FIG. 2 superimposed on a layout pattern. It is the figure which showed the verification object area | region which considered equipotential tracking. It is a figure which shows the structure of the layout verification apparatus which concerns on this invention. It is a flowchart of the layout verification process which concerns on this invention. It is a figure before layout pattern correction. It is a figure after layout pattern correction. It is a flowchart which shows the detail of step S13 of FIG. It is a figure in case the deleted mask layer is a metal mask layer. It is a figure in case the deleted mask layer is a metal mask layer. It is a figure in case the deleted mask layer is a metal mask layer. It is a figure in case the deleted mask layer is a via mask layer. It is a figure in case the deleted mask layer is a via mask layer. It is a figure in case the deleted mask layer is a via mask layer. It is a figure which shows the example of the table | surface of equipotential tracking information. It is the figure which gave the equipotential number with respect to the layout pattern of FIG. 9B. It is a figure which shows the structure of the DRC execution control part of a layout verification apparatus.

<Embodiment>
Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 7 is a diagram showing the configuration of the layout verification apparatus according to the present invention.
The layout verification apparatus according to the present invention reads the pre-change layout file 31, the post-change layout file 32, and the DRC check item file 33, performs DRC verification, and then outputs the DRC result file 41.

  The pre-change layout file 31 stores the layout pattern data of the integrated circuit before the change is made. The layout pattern data stored in the pre-change layout file 31 is data that has been confirmed to have no error in the DRC verification.

  The post-change layout file 32 stores layout pattern data in which the layout pattern data stored in the pre-change layout file 31 is partially changed and modified.

  The DRC check item file 33 includes, in advance, mask layer definition information in the layout pattern data, information indicating a mask layer to be subjected to DRC verification, equipotential tracking information indicating a connection relationship between the mask layers, and DRC. Data relating to check items and check dimensions for verification is stored.

  The DRC result file 41 stores data relating to error information obtained as a result of performing DRC verification.

[Configuration of layout verification device]
The layout verification apparatus according to the present invention includes a DRC execution control unit 51 and a program memory 52.

  The DRC execution control unit 51 reads the pre-change layout file 31, the post-change layout file 32, and the DRC check item file 33 according to the program stored in the program memory 52, sets the verification target region, and sets the DRC check item file. Based on the check items and check dimensions stored in 33, DRC verification is executed.

  When an error is detected as a result of DRC verification, the DRC execution control unit 51 generates error information, an error report based on the error information, an error flag displayed on the layout pattern, and a DRC result of the antenna ratio A DRC result file 41 in which data related to the above is stored is output. For example, the DRC result file 41 output from the DRC execution control unit 51 includes the gate coordinates where the antenna ratio error is detected and the antenna ratio of the error gate.

  The program memory 52 stores a program for performing the layout verification process shown in FIG. 8 and a DRC execution control program.

[Layout verification processing]
With reference to FIG. 8, the layout verification processing in the present invention will be described.

(1) Step S11
First, the designer or the layout verification apparatus changes the layout pattern data. When the designer makes a change, the designer changes the layout pattern data using the layout editor. When the layout verification device changes, the layout verification device automatically changes the layout pattern data according to the program. Here, the layout pattern data obtained by partially changing / modifying the layout pattern data stored in the pre-change layout file 31 is stored in the post-change layout file 32. The layout verification apparatus reads the pre-change layout file 31 and the post-change layout file 32.

(2) Step S12
Next, the layout verification apparatus compares the layout pattern data before and after the change, and extracts a difference graphic. Specifically, the layout verification apparatus reads the layout pattern data stored in the layout file 31 before change and the layout pattern data stored in the layout file 32 after change, and displays the mismatched portion of both layout pattern data as a difference graphic. Extract as Details of the “extraction of difference graphic” will be described later.

(3) Step S13
Next, the layout verification apparatus performs change node extraction processing based on the extracted difference graphic. Details of the “change node extraction process” will be described later.

(4) Step S14
Next, the layout verification apparatus in FIG. 8 assigns equipotential numbers to the extracted change nodes (changed layout pattern data). The details of “give equipotential numbers” will be described later.

(5) Step S15
Next, the layout verification apparatus performs equipotential tracking based on the extracted difference graphic, and extracts a verification target portion having the same equipotential number as the extracted change node. Details of “extraction of verification target portion” will be described later.

(6) Step S16
Next, the layout verification apparatus performs DRC verification of the antenna ratio only for the verification target portion extracted in step S15. Details of “antenna ratio DRC verification” will be described later.

(7) Step S17
Next, the layout verification apparatus outputs the result of the DRC verification determined in step S16 to the DRC result file 41.

(8) Step S18
Next, the layout verification apparatus determines whether there is an error based on the result of the DRC verification. If there is an error as a result of the DRC verification (“yes” in step S16), the process proceeds to layout pattern data change in step S11. If there is no error as a result of the DRC verification (“no” in step S16), the process ends.

[Extract difference figure]
The details of the differential graphic extraction will be described below.

  FIG. 9A is a diagram showing layout pattern data before change stored in the layout file 31 before change in FIG. FIG. 9B is a diagram showing changed layout pattern data stored in the changed layout file 32 of FIG.

9A and 9B, D1 is the layout pattern data of the mask layer of the field. D2 is the layout pattern data of the mask layer of polysilicon. D3 is the layout pattern data of the contact mask layer. D4 is the layout pattern data of the mask layer of the first metal. D5 is the layout pattern data of the mask layer of the first via (Via). D6 is the layout pattern data of the mask layer of the second metal. D7 is the layout pattern data of the mask layer of the second via. D8 is the layout pattern data of the mask layer of the third metal. D9 is the layout pattern data of the mask layer of the third via. D10 is the layout pattern data of the mask layer of the fourth metal.
These are defined in the DRC check item file 33 in advance.

  D1 corresponds to a diffusion layer, and D2 corresponds to a gate electrode.

  From the difference between the layout pattern data before the change shown in FIG. 9A and the layout pattern data after the change shown in FIG. 9B, the layout verification apparatus performs the third via mask layer D9 and the fourth metal mask layer shown in FIG. 9B. D10 is extracted as a difference graphic.

[Change node extraction processing]
With reference to FIG. 10, the details of the change node extraction process shown in step S13 of FIG. 8 will be described.

(1) Step S131
First, the layout verification apparatus determines whether the difference graphic is a graphic of the mask layer subject to DRC verification of the antenna ratio. For example, if the differential figure is any one of a field mask layer, a polysilicon mask layer, a contact mask layer, a metal mask layer, and a via mask layer, the figure is determined to be a figure of an antenna ratio verification target mask layer. If the mask layer of the difference graphic is not a mask layer subject to DRC verification of the antenna ratio (“no” in step S131), the change node extraction is not performed and the “change node extraction process” is terminated, and the step of FIG. Proceed to S14. On the other hand, when the mask layer of the difference graphic is a mask layer subject to DRC verification of the antenna ratio (“yes” in step S131), the process proceeds to step S132.

(2) Step S132
Next, the layout verification apparatus compares the difference graphic with the layout pattern data after change, and whether the difference graphic is a figure added to the layout pattern data before change or a figure deleted from the layout pattern data before change. Make a decision. That is, the layout verification apparatus determines whether the mask layer of the difference graphic is the target mask layer added to the layout pattern data before change or the target mask layer deleted from the layout pattern data before change. In the case of a graphic with a difference graphic added, the layout verification apparatus proceeds to step S133. On the other hand, if the difference graphic is a deleted graphic, the process proceeds to step S134.

(3) Step S133
In the case of a graphic to which a differential graphic is added, the layout verification apparatus sets the differential graphic as a change node. Therefore, the third via mask layer D9 and the fourth metal mask, which are the differential graphic extracted in step S12 of FIG. Set layer D10 as the change node. That is, the layout verification apparatus sets the added target mask layer itself as a change node.

(4) Step S134
The layout verification apparatus determines the type of the target mask layer in the case of a graphic from which the differential graphic is deleted. Here, if the deleted target mask layer is a wiring layer (a field mask layer, a polysilicon mask layer, or a metal mask layer), the layout verification apparatus proceeds to step S135. If the deleted target mask layer is a via contact layer (via mask layer or contact mask layer), the process proceeds to step S136.

(5) Step S135
When the deleted target mask layer is a wiring layer, the layout verification apparatus sets a graphic that touches the differential graphic as a change node. That is, the layout verification apparatus sets a mask layer in contact with the deleted target mask layer as a change node.

(6) Step S136
In the case where the deleted target mask layer is a via mask layer or a contact mask layer, the layout verification apparatus sets a lower layer graphic of the differential graphic as a change node. That is, the layout verification apparatus sets a mask layer (a mask layer below the deleted target mask layer) below the deleted target mask layer in the stacking direction as a change node.

[When the deleted mask layer is a metal mask layer]
With reference to FIG. 11A to FIG. 11C, the case where the deleted mask layer is a metal mask layer in step S <b> 134 will be described.

  11A to 11C, E1 is the layout pattern data of the mask layer of the field. E2 is the layout pattern data of the mask layer of polysilicon. E3 is the layout pattern data of the contact mask layer. E4 is the layout pattern data of the mask layer of the first metal. E5 is the layout pattern data of the mask layer of the first via. E6-1 and E6-2 are layout pattern data of the mask layer of the second metal. E7 is the layout pattern data of the mask layer of the second via. E8 is the layout pattern data of the mask layer of the third metal. These are defined in the DRC check item file 33 in advance.

  FIG. 11A shows layout pattern data before change. FIG. 11B shows the layout pattern data after the change. FIG. 11C is a diagram in which the difference graphic of FIG. 11A and FIG. 11B is added to FIG. 11B.

  In the layout pattern data of the second metal mask layer, E10 in FIG. 11C, which is the difference between E6-1 in FIG. 11A and E6-2 in FIG. 11B, is the difference graphic extracted in step S12 in FIG.

  E10 in FIG. 11C is the difference graphic extracted in step S12 in FIG. 8, and since the target layer is a wiring layer (second metal mask layer), the layout verification apparatus changes the graphic in contact with the difference graphic E10 to a change node. And

  In the case of FIG. 11C, the layout verification apparatus extracts the second metal mask layer E6-2 in contact with the difference graphic E10 (the deleted target mask layer) as a change node.

[When the deleted mask layer is a via mask layer]
A case where the deleted mask layer is a via mask layer in step S134 will be described with reference to FIGS. 12A to 12C.

  12A to 12C, F1 is the layout pattern data of the mask layer of the field. F2 is the layout pattern data of the mask layer of polysilicon. F3 is the layout pattern data of the contact mask layer. F4 is the layout pattern data of the mask layer of the first metal. F5 is the layout pattern data of the mask layer of the first via. F6 is the layout pattern data of the mask layer of the second metal. F7 is the layout pattern data of the mask layer of the second via. F8 is the layout pattern data of the mask layer of the third metal. These are defined in the DRC check item file 33 in advance.

  FIG. 12A shows layout pattern data before change. FIG. 12B shows the layout pattern data after the change. FIG. 12C is a diagram in which the difference graphic of FIG. 12A and FIG. 12B is added to FIG. 12B.

  In FIG. 12A, F7 and F8 exist, but in FIG. 12B, F7 and F8 do not exist. That is, F7 and F8 are deleted. In FIG. 12C, the figures of F10 and F11 corresponding to F7 and F8 that do not exist in FIG. 12B are added so as to be recognized as deleted figures.

  F10 and F11 in FIG. 12C are the difference graphics extracted in step S12 in FIG.

  The difference graphic F10 and the difference graphic F11 in FIG. 12C are the difference graphic extracted in step S12 in FIG. 8, and focusing on the difference graphic F10, the target layer is a via mask layer. A figure of the mask layer below the stacking direction is set as a change node.

  In the case of FIG. 12C, the layout verification apparatus extracts, as a change node, the second metal mask layer F6, which is a lower layer graphic of the difference graphic F10, which is the deleted second via mask layer graphic.

  The layout verification apparatus can specify a wiring layer which is a lower layer of the contact mask layer and the via mask layer from the equipotential tracking information.

[Equipotential tracking information]
An example of equipotential tracking information will be described with reference to FIG.

  The row “connection-n” in FIG. 13 indicates that the mask layer in the wiring layer (lower layer) column and the mask layer in the wiring layer (upper layer) column are connected via the mask layer in the connection layer column. .

  For example, the row “connection-1” indicates that the mask layer (lower layer) of the field and the mask layer (upper layer) of the first metal are connected via the mask layer of the contact.

  Similarly, the row “connection-2” indicates that the polysilicon mask layer (lower layer) and the first metal mask layer (upper layer) are connected via the contact mask layer.

  Similarly, the row “connection-3” indicates that the first metal mask layer (lower layer) and the second metal mask layer (upper layer) are connected via the first via mask layer.

  Similarly, the row “connection-4” indicates that the mask layer (lower layer) of the second metal and the mask layer (upper layer) of the third metal are connected via the mask layer of the second via.

  Similarly, the row “connection-5” indicates that the third metal mask layer (lower layer) and the fourth metal mask layer (upper layer) are connected via the third via mask layer.

[Give equipotential number]
The details of giving equipotential numbers will be described below.

  The layout verification apparatus refers to the equipotential tracking information of FIG. 13 prepared in advance in the DRC check item file 33 and assigns equipotential numbers to each figure including the difference figure.

  FIG. 14 is a diagram in which equipotential numbers are assigned to the layout pattern of FIG. 9B.

  In FIG. 14, “eq1”, “eq2”, and “eq3” indicate equipotential numbers of the respective figures, and indicate that the figures indicated by “eq1” have the same equipotential number (equal potential). Yes. The equipotential numbers “eq1”, “eq2”, and “eq3” have different electrical potential numbers because they have no electrical connection.

[Extraction of verification target part]
Hereinafter, extraction of the verification target portion will be described.

  The layout verification apparatus sets a location that constitutes a channel with a polysilicon mask layer having the same equipotential number as the change node extracted in step S13 as a verification target location. Here, the gate part (verification object gate) used as the object of DRC verification of the antenna ratio is assumed as an example of the verification object part.

  In the case of the layout pattern data in FIG. 9B, the change nodes extracted in step S13 are the third via mask layer D9 and the fourth metal mask layer D10.

  The layout verification apparatus refers to the equipotential number given in step S14, and assigns a channel to the polysilicon mask layer D2 having the same potential as the change node (the third via mask layer D9 and the fourth metal mask layer D10). Since there is a portion to be configured, this polysilicon mask layer D2 is extracted as a verification target gate.

[DRC verification of antenna ratio]
Details of the DRC verification of the antenna ratio will be described below. Here, DRC verification will be described when a change is made to add a mask layer of the third via and a mask layer of the fourth metal.

  Assuming that the antenna ratio is defined as “(total sum of metal areas connected to gate to be verified) / (gate area to be verified)”, in the case of the layout pattern data of FIG. Is the gate to be verified, and the equipotential number “eq1” is the target in FIG. 14 and is obtained by “(D4 area + D6 area + D8 area + D10 area) / (D2 area)”. it can.

  In the layout verification apparatus, the value of “(Area of D4 + Area of D6 + Area of D8 + Area of D10) / (Area of the portion constituting the channel with D2)” is the file 33 of the DRC check item in FIG. When the reference value indicated by is exceeded, a DRC error is determined.

[Configuration of DRC execution control unit]
A configuration example of the DRC execution control unit 51 will be described with reference to FIG.

  In order to realize the layout verification processing shown in FIG. 8, the DRC execution control unit 51 includes a difference graphic extraction unit 511, a change node extraction unit 512, an equipotential number assignment unit 513, a verification target extraction unit 514, and DRC execution. Unit 515 and DRC result output unit 516.

  The difference graphic extraction unit 511 performs a difference graphic extraction process shown in step S12 of FIG.

  The change node extraction unit 512 performs a change node extraction process shown in step S13 of FIG.

  The equipotential number assigning unit 513 performs an equipotential number assigning process shown in step S14 of FIG.

  The verification target extraction unit 514 performs a verification target extraction process shown in step S15 of FIG.

  The DRC execution unit 515 performs a DRC verification process shown in step S16 of FIG.

  The DRC result output unit 516 performs a DRC result file output process shown in step S17 of FIG.

[Hardware example]
As an example of the layout verification apparatus according to the present invention, a computer such as a PC (personal computer), an appliance, a thin client server, a workstation, a mainframe, and a supercomputer is assumed.

  Examples of the DRC execution control unit 51 include a CPU (Central Processing Unit), a network processor (NP: Network Processor), a microprocessor (microprocessor), a microcontroller, or a semiconductor integrated circuit (IC: Integrated Circuit) having a dedicated function. Etc. are considered.

  As an example of the program memory 52, a semiconductor storage device such as a RAM (Random Access Memory), a ROM (Read Only Memory), an EEPROM (Electrically Erasable and Programmable Read Only Memory) or a flash memory, an HDD (HoldSold) An auxiliary storage device such as State Drive), a removable disk such as a DVD (Digital Versatile Disk), a storage medium such as an SD memory card (Secure Digital memory card), or the like is conceivable. Further, a buffer or a register may be used. Alternatively, DAS (Direct Attached Storage), FC-SAN (Fibre Channel-Storage Area Network), NAS (Network Attached Storage), IP-SAN (IP-Storage Area), etc. may be used.

  The difference graphic extraction unit 511, the change node extraction unit 512, the equipotential number assigning unit 513, the verification target extraction unit 514, the DRC execution unit 515, and the DRC result output unit 516 are a module, a component, or a dedicated unit. It may be a device or an activation (calling) program thereof.

  However, actually, it is not limited to these examples.

<Summary>
As described above, in the present invention, the layout pattern data before and after the change are compared, the change node is determined from the difference graphic, the equipotential number is assigned to the layout pattern after the change, and the assigned equipotential number is referenced. A figure having the same equipotential number as the change node extracted in this manner is set as a verification target location.

  Specifically, in the change node extraction process, the layout pattern data before and after the change are compared, and the change node is determined from the difference graphic. Further, an equipotential number is assigned to the layout pattern after the change in the equipotential number assigning process. Further, referring to the equipotential number assigned in the equipotential number assigning process, a figure having the same equipotential number as the change node extracted in the change node extraction process is set as a verification target location.

  As a result, it is possible to specify a location to be verified by changing the layout pattern data, track and specify the location, and perform DRC verification.

  According to the present invention, even in a part of DRC verification such as an antenna ratio performed after a partial change is made to verified layout pattern data, it is possible to specify the changed portion, so that the verification target area is designated as layout pattern data. Therefore, the DRC verification time can be shortened.

  For example, assuming that 1 million transistors exist on a semiconductor integrated circuit, the number of transistors to be subjected to antenna ratio check will be compared between normal DRC verification and DRC verification according to the present invention.

  In normal DRC verification, it is necessary to perform an antenna ratio check for all transistors (all 1 million transistors) regardless of the scale of the correction part.

  On the other hand, in the DRC verification according to the present invention, it is only necessary to perform the antenna ratio check only for the gate of the changed portion affected by the layout change.

  When there is only one gate at the change location affected by the layout change, the calculation amount is proportional to the number of gates. Therefore, the calculation time of DRC verification in the present invention is 1/1 million of the calculation time of normal DRC verification. It becomes. That is, an effect of shortening the calculation time can be obtained.

<Appendix>
Part or all of the above-described embodiments can be described as in the following supplementary notes. However, actually, it is not limited to the following description examples.

(Appendix 1)
In a DRC verification system that is performed after a partial change has been made to verified layout pattern data in layout verification of a semiconductor integrated circuit,
Means for extracting a difference graphic of the layout pattern data before and after the change and extracting a change node from the difference graphic;
Means for assigning an equipotential number to the layout pattern data after change and extracting a verification target portion having the same equipotential number as the change node with reference to the equipotential number;
A DRC verification system comprising: means for performing DRC verification of an antenna ratio on a pre-extracted location to be verified.

(Appendix 2)
In a method for laying out a semiconductor integrated circuit, a DRC verification method performed after a partial change is made to verified layout pattern data,
Extracting a difference graphic of layout pattern data before and after the change and extracting a change node from the difference graphic; and
Assigning an equipotential number to the layout pattern data after the change and extracting the verification target portion having the same equipotential number as the change node with reference to the equipotential number;
And a step of performing DRC verification of the antenna ratio on the pre-extracted location to be verified.

(Appendix 3)
The layout verification method according to attachment 2, wherein
The step of extracting change nodes from the difference graphic is as follows:
In the case of a figure to which the layout pattern data after the change is added, a step of setting the difference figure as a change node;
In the case of a figure from which the layout pattern data after the change is deleted and the target layer is a wiring layer, a figure that touches the difference figure is set as a change node;
In the case of a figure from which the layout pattern data after the change has been deleted and the target layer is a via contact layer (either via layer or contact layer), the figure of the mask layer below the difference figure is used as the change node A layout verification method comprising:

<Remarks>
As mentioned above, although embodiment of this invention was explained in full detail, actually, it is not restricted to said embodiment, Even if there is a change of the range which does not deviate from the summary of this invention, it is included in this invention.

31 ... Layout file before change 32 ... Layout file after change 33 ... DRC check item file 41 ... DRC result file 51 ... DRC execution control unit 511 ... Difference graphic extraction unit 512 ... Change node extraction unit 513 ... Equipotential number assignment unit 514 ... Verification target extraction unit 515... DRC execution unit 516... DRC result output unit 52.

Claims (9)

Program memory storing the program,
A DRC execution control unit for executing DRC verification according to the program,
The DRC execution control unit identifies a verification target part of DRC verification using equipotential tracking from a changed part of verified layout pattern data partially changed, and performs DRC verification on the verification target part. A layout verification device. The layout verification apparatus according to claim 1,
The DRC execution control unit
A differential graphic extraction unit that extracts a differential graphic of layout pattern data before and after the change;
A change node extraction unit for extracting a change node from the difference graphic;
An equipotential number assigning section for assigning an equipotential number to the layout pattern data after the change;
A verification target extraction unit that extracts a verification target gate having the same equipotential number as the change node with reference to the equipotential number;
A layout verification apparatus comprising: a DRC execution unit that performs DRC verification of an antenna ratio for the extracted verification target gate. The layout verification apparatus according to claim 2,
The change node extraction unit includes:
Means for determining whether the differential graphic is a graphic of a target mask layer for DRC verification of antenna ratio;
When the difference graphic is a graphic of the target mask layer, the target mask layer is a mask layer added to the layout pattern data before change or a mask layer deleted from the layout pattern data before change Means for determining whether or not
When the target mask layer is an added mask layer, means for setting the target mask layer as a change node;
Means for determining the type of the deleted mask layer when the target mask layer is a deleted mask layer;
When the deleted mask layer is a wiring layer, a means for setting the mask layer in contact with the target mask layer as a change node;
And a means for using a mask layer under the target mask layer as a change node when the deleted mask layer is a via contact layer. A method for verifying the layout of a semiconductor integrated circuit implemented by a computer,
Identifying the verification target part of DRC verification using equipotential tracking from the changed part of the verified layout pattern data partially changed;
Performing a DRC verification on the verification target portion. The layout verification method according to claim 4,
Extracting the difference graphic of the layout pattern data before and after the change,
Extracting a change node from the difference graphic;
Assigning an equipotential number to the changed layout pattern data;
Extracting a verification target gate having the same equipotential number as the change node with reference to the equipotential number;
A layout verification method further comprising: performing DRC verification of antenna ratio on the extracted gate to be verified. The layout verification method according to claim 5,
Determining whether the differential graphic is a graphic of a target mask layer for DRC verification of antenna ratio;
When the difference graphic is a graphic of the target mask layer, the target mask layer is a mask layer added to the layout pattern data before change or a mask layer deleted from the layout pattern data before change Determining whether or not
When the target mask layer is an added mask layer, the target mask layer is a change node;
When the target mask layer is a deleted mask layer, determining the type of the deleted mask layer;
When the deleted mask layer is a wiring layer, a mask layer in contact with the target mask layer is a change node;
A layout verification method further comprising: when the deleted mask layer is a via contact layer, a mask layer below the target mask layer as a change node. Identifying a verification target location of DRC verification using equipotential tracking from a changed location of verified layout pattern data partially changed;
A program for causing a computer to execute a step of performing DRC verification on the verification target portion. The program according to claim 7,
A step of extracting a difference graphic of layout pattern data before and after the change;
Extracting a change node from the difference graphic;
Assigning an equipotential number to the layout pattern data after the change;
Extracting a verification target gate having the same equipotential number as the change node with reference to the equipotential number;
A program for causing a computer to further execute a step of performing DRC verification of an antenna ratio on the extracted verification target gate. The program according to claim 8, wherein
Determining whether the differential graphic is a graphic of a target mask layer for DRC verification of antenna ratio;
When the difference graphic is a graphic of the target mask layer, the target mask layer is a mask layer added to the layout pattern data before change or a mask layer deleted from the layout pattern data before change Determining whether or not
When the target mask layer is an added mask layer, the target mask layer as a change node;
When the target mask layer is a deleted mask layer, determining the type of the deleted mask layer;
When the deleted mask layer is a wiring layer, the mask layer in contact with the target mask layer is a change node;
When the deleted mask layer is a via contact layer, a program for causing a computer to further execute a step of setting a mask layer below the target mask layer as a change node.

Images