JP3917342B2 - Test program generator for logic verification - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a test program generation apparatus for logic verification in hardware design.
[0002]
In order to provide highly competitive LSI hardware consisting of multiple modules that make up an information processing system to the market, design highly reliable, low cost / performance, early requested ones It is necessary to satisfy the demands such as. Therefore, it is required to increase the design scale and shorten the design period.
[0003]
To achieve this, it is necessary to perform highly reliable logic verification in a short period of time, and logic simulation is generally used as a logic verification method for hardware design.
[0004]
Accordingly, it is desired to create a highly reliable logic verification test program in hardware design in a short period of time.
[0005]
[Prior art]
FIG. 14 is an explanatory diagram of the prior art.
[0006]
When creating a large-scale LSI chip including a plurality of CPUs such as a server system, a memory, a data transfer controller, and a high-speed interface with the outside, the LSI designer 81 first writes the specification 80 The LSI is logically designed so as to satisfy the required functions and performance for the specified LSI. The request function in this case includes, for example, what kind of output message the user wants to generate in response to inputting a message. In the case of an LSI that requires a large-scale or complex function, it is common for a plurality of designers to individually design by determining the range that each designer is responsible for. When design data 82 is obtained by collecting LSI design circuits designed by a plurality of designers, it is passed to a verifier 83.
[0007]
The verifier 83 creates a plurality of verification items 830 for verifying whether the design data 82 satisfies the functions and performances required by the specifications. Next, a simulator 831 that simulates a circuit function corresponding to each verification item 830 is created, and a test program 832 that is executed by the simulator 831 is created. At this time, an expected value 833 obtained as a result of the test by the test program 832 in the simulator 831 is created. The LSI circuit thus designed is tested by the simulator 831 using the test program 832 for the LSI circuit designed by the simulator, and the result obtained is compared with the expected value 833. If it does not match, it is determined that there is a logical error in the designed circuit. It is possible to detect which part has an error by the operation of determination by the simulator 831. If no error determination occurs, it can be confirmed that the design is correct. In many cases, the design work by the designer and the verification by the verifier are actually performed in parallel.
[0008]
As described above, in the conventional technology, the specification of the entire system is described in the specification, but the interface specification between modules may be unclear. Therefore, in order to create a test program that is fully aware of the interface specifications, it was necessary to guess the interface from the specifications and to clarify the interface specifications by asking the designer through an interview.
[0009]
In addition, the verifier extracts a part (verification item) that is likely to cause a design error from the specification based on past know-how and manually creates a test program, and a systematic procedure for creating the test program. Is not established.
[0010]
[Problems to be solved by the invention]
As described above, in the conventional technology, it is difficult to create a test program that is fully aware of the interface specifications if the interface specifications between modules are unclear.
[0011]
In addition, as the scale of the system increases, there is a problem that the proportion of the man-hours for generating the system verification test program is increasing with respect to the total system design man-hours.
[0012]
Recently, module verification has been proposed in which the specifications to be satisfied by the entire system are divided for each module. At that time, a high-quality test program for module verification is created for specifications with unclear interface specifications. Difficult to do.
[0013]
An object of the present invention is to provide a logic verification test program generation apparatus capable of systematically generating a test program for performing module verification by clarifying interface specifications.
[0014]
[Means for Solving the Problems]
FIG. 1 shows the principle configuration of the present invention. In the figure, 10 is a description creation means for each module constituting the LSI chip system to be designed, 11 is a block diagram creation means, 12 is a sequence diagram creation means, 13 is a sequence diagram overlay verification means, and 14 is a test program generation. Means, 20 to 23 are storage units, 20 is a storage unit for storing module descriptions, 21 is a storage unit for storing block diagrams, 22 is a storage unit for storing sequence diagrams, and 23 is for storing test programs. It is a storage unit.
[0015]
In the present invention, a plurality of sequences generated in the entire LSI chip system is described in a formal form (an expression format using an illustration) so that the meaning can be immediately understood even by a person other than the designer and verified. Systematic extraction of the input / output of the target module enables the creation of a test pattern for verifying the LSI chip.
[0016]
The module description creating means 10 creates a module description using a hardware description language and stores the internal operation of each module and the input / output description of each module previously described in a natural language. Stored. Next, the block diagram creating means 11 creates a block diagram defining the entire system, the module and the connection status between the modules, and stores the module description in the storage unit 21. Subsequently, a plurality of sequence diagrams representing a series of messages (sequences) transferred between the modules in the hardware shown in the block diagram by the sequence diagram creation means 12 are created between the modules and stored in the storage unit 22. . A process of superimposing the sequence diagrams between the plurality of modules obtained in this way by the operation of the sequence diagram overlay verification means 13 is performed. If there is a contradiction in this superposition, it can be seen that the sequence is wrong and a design error can be found. After the check and correction by the sequence diagram overlay verification unit 13, the test program generation unit 14 generates a test program for the module of interest and stores it in the storage unit 23. In this way, the number of steps for generating the test program can be reduced, and verification focusing on the module to be verified becomes possible.
[0017]
FIG. 2 shows a second principle configuration of the present invention. In the figure, 10 to 14 are the same as those in FIG. The difference from FIG. 1 is that a module dividing means 15 and a storage unit 24 for storing the divided submodules are provided.
[0018]
In FIG. 2, the operations from 10 to 13 are the same as those in FIG. 1 described above, and each sequence diagram between a plurality of modules is superposed by the operation of the sequence diagram superposition verification means 13. The module to be verified in the sequence is divided into sub-modules by the module dividing means 15 according to the principle and stored in the storage unit 24. Next, the input / output to the divided submodule is extracted, and the test program for submodule verification divided by the test program generation means 14 is generated and stored in the storage unit 23.
[0019]
A test program focusing on the module to be verified divided according to the second principle configuration can be systematically generated.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
The present invention can be realized by software of the information processing apparatus, and FIG. 3 is a processing flow of the first embodiment.
[0021]
First, based on the design specifications of the LSI to be designed, an input describing the internal operation of each module and the input / output of each module is performed using a hardware description language (HDL) (FIG. 3). S1). Next, a block diagram showing the connection status between the entire system and the modules in the system is created from the above description (S2 in FIG. 3).
[0022]
Next, in the processing of FIG. 3, a sequence that flows through the entire system is created using a message delivered between modules (S3 in FIG. 3). The details of this process are composed of the following three steps S30 to S32. That is, the sequence length is specified by a random number (S30 in FIG. 3), the module where the sequence starts is specified by a random number (S31), and the output message and the next state of the module are uniquely determined by the input message and the current state of the module. (S32).
[0023]
Thereafter, the sequence diagrams are superimposed (S4 in FIG. 3). The details of this process are composed of three steps S40 to S42. That is, attention is paid to a part where the module state changes without depending on the input message in a certain sequence (S40 in FIG. 3). Subsequently, a sequence in which the noted state change occurs in another sequence is found (S41), and the previous two sequences are connected to generate a new sequence in which a plurality of sequences flow in parallel (S42). .
[0024]
Next, a test program focusing on the module to be verified when the sequences are overlaid is generated (S5 in FIG. 3).
[0025]
FIG. 4 shows an example of a block diagram of a target LSI according to the first embodiment. This block diagram is created by S2 in FIG. 3, and in this example, it is composed of module A, module B, module C, and module D, and the input / output relationship of each module is accompanied by an arrow connecting the modules. The internal operation of the module is omitted.
[0026]
FIG. 5 shows an example of a series of messages (sequence) exchanged between modules. The example of the block diagram of FIG. 4 is generated by S3 (S30 to S32) of FIG. First, the sequence length is 8 (specified by a random number), the module starting with the sequence is module B (specified by a random number), and the output message and the next state of the module are uniquely determined according to the input message and the current state of the module. . For example, in the module B, the output message q2 and the next state s1 of the module are uniquely determined by the input message q1 and the current state s1 of the module.
[0027]
6 to 8 are other sequence diagrams (No. 1) to (No. 3) in which the state of interest changes state, and FIGS. 9 to 11 are superimposed sequence diagrams (No. 1) to (No. 3). is there.
[0028]
An example of superposition of sequence diagrams (corresponding to S4 in FIG. 3) will be described with reference to FIGS. In the sequence diagram shown in FIG. 5, attention is paid to a portion where the state is changed irrespective of the input message (corresponding to S40 in FIG. 3). In the example of FIG. 5, attention is given to the portions represented as A1, B1, and C1.
[0029]
A1: A part where the state of module B changes from s0 to s1 B1: A part where the state of module B changes from s1 to s2 C1: A part where the state of module C changes from s2 to S0 Next, in A1, B1 and C1 When a sequence diagram in which state transitions are described is found (corresponding to S41 in FIG. 3), in this example, FIGS. 6 to 8 can be found as follows.
[0030]
A1: State transition from s0 to s1 is described in A2 in FIG. 6 and A3 in FIG.
[0031]
B1: State transition from s0 to s2 is described in B2 in FIG. 6, B3 in FIG. 7, and B4 in FIG.
[0032]
C1: State transition from s2 to s0 is described in C4 of FIG.
[0033]
A plurality of sequence diagrams (FIGS. 6 to 8) are overlapped to create a new sequence diagram (corresponding to S42 in FIG. 3). That is,
The sequence diagram of FIG. 9 is obtained by associating the attention points A1 and A2, B1 and B2, and superimposing FIGS.
[0034]
The sequence diagram of FIG. 10 is obtained by associating the attention points A1 and A3, B1 and B3, and superimposing FIGS.
[0035]
The sequence diagram of FIG. 11 is obtained by associating the points of interest B1 and B4, C1 and C4, and superimposing FIGS. However, in FIG. 8, only the part surrounded by the dotted line can be overlapped.
[0036]
Next, FIG. 12 is a processing flow of the second embodiment.
[0037]
The processing flow of the second embodiment is the same processing from steps S1 to S4 of the processing flow of the first embodiment, and a description thereof will be omitted. Subsequent to the process of superimposing sequence diagrams (S4 in FIG. 12), paying attention to the submodule to be verified, only the input / output of this submodule is extracted (S5 in FIG. 12). Thereafter, the extracted test program for submodule verification is generated (S6 in FIG. 12).
[0038]
FIG. 13 is an example of a sequence diagram according to the second embodiment.
[0039]
Through the processing up to S4 in FIG. 13, a sequence diagram in which a plurality of sequence diagrams as shown in the examples in FIGS. 9 to 11 are overlapped as in the first embodiment is generated. In the sequence diagram shown in FIG. 9, when the module to be verified is the module B, only the input / output in the module B is extracted, and the sequence diagram shown in FIG. . A test program focusing on this module B is created.
[0040]
【The invention's effect】
According to the present invention, it is possible to generate a test program for verifying a system configuration by representing a system configuration in a block diagram, a sequence generated in the system in a sequence diagram, and systematically superimposing a plurality of sequences. it can. In addition, it is possible to systematically generate a test program for logic simulation focusing on the module to be verified.
[0041]
Furthermore, the generation cost of the logic simulation test program can be reduced, and design errors can be detected early.
[Brief description of the drawings]
FIG. 1 is a diagram showing a first principle configuration of the present invention.
FIG. 2 is a diagram showing a second principle configuration of the present invention.
FIG. 3 is a diagram illustrating a processing flow according to the first embodiment.
FIG. 4 is a diagram illustrating an example of a block diagram of a target LSI according to the first embodiment;
FIG. 5 is a diagram illustrating an example of a series of messages exchanged between modules.
FIG. 6 is another sequence diagram (part 1) in which a state of interest changes state.
FIG. 7 is another sequence diagram (part 2) in which a state of interest changes state.
FIG. 8 is another sequence diagram (part 3) in which a state of interest changes state.
FIG. 9 is a sequence diagram (No. 1) superimposed.
FIG. 10 is a sequence diagram (No. 2) superimposed.
FIG. 11 is a sequence diagram (No. 3) superimposed.
FIG. 12 is a diagram illustrating a processing flow according to the second embodiment.
FIG. 13 is a diagram illustrating an example of a sequence diagram according to the second embodiment.
FIG. 14 is an explanatory diagram of the prior art.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Description creation means 11 of each module Block diagram creation means 12 Sequence diagram creation means 13 Sequence diagram overlay verification means 14 Test program generation means 20 Storage section 21 storing module descriptions Storage section 22 storing block diagrams Each sequence diagram Storage unit 23 for storing test unit Storage unit for storing test program

Claims (2)

In a test program generation device for LSI logic verification,
Create a block diagram that defines the connection between the entire system and the module based on the description of the internal operation and input / output of each module that constitutes the LSI system to be designed in the hardware description language Means,
A sequence diagram generating means for generating a sequence diagram representing a series of messages to pass each for between the modules shown in block diagram created by the block diagram preparation means,
A sequence diagram overlay verification means for generating a new sequence in which a plurality of sequences are connected by overlapping a plurality of sequence diagrams corresponding to each module created by the sequence diagram creation means, and performing verification;
Test program generation means for generating a test program for the module verified by the sequence diagram overlay verification means ;
A test program generating device for logic verification, comprising: In claim 1,
A module dividing means for generating a sub-module by dividing a module to be verified corresponding to an input / output with respect to a sequence obtained by superimposing the sequence diagrams by the sequence diagram overlay verification means;
The test program generating apparatus for logic verification, wherein the test program generating means generates a test program for each module divided by the module dividing means .

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