CN1298047C - Validity verification of bipolar integrated circuit design and electric network consistency comparison method - Google Patents
Validity verification of bipolar integrated circuit design and electric network consistency comparison method Download PDFInfo
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Abstract
The present invention relates to an effective verification method for a double-pole IC design and a comparison method for electric-network consistence, wherein the effective verification method for a double-pole IC comprises a logic level, a circuit level and a territory level; the comparison method for electric-network consistence provides a method for using multiple patterns in an applied pattern theory and is combined with the implement methods of the characteristics of electronic theory patterns in the double-pole IC; the consistence of the electric network of an extracted circuit of the comparison verification method of the double-pole IC and the original circuit is distinguished; because of the complexity and the diversity of the element variety in manufacturing of the double-pole IC design, the design is easy to cause errors, and the correctness of the IC design can be ensured by the comparison verification method and the comparison method for electric-network consistence. The present invention has the advantages of strictness and versatility.
Description
(1) technical field
The present invention relates to method of designing integrated circuit, a kind of effective verification technique named to " comparatively validate method " that refers in particular in the bipolar integrated circuit design is implemented, and the effective checking and the electric network consistency comparative approach of a kind of bipolar integrated circuit design that is implemented of the electric network consistency comparative approach of bipolar integrated circuit.
(2) background technology
Development of integrated circuits is advanced along deep-submicron and sub-micro direction on the one hand, advances along the direction of digital-to-analogue mixed signal again on the other hand.In the case, bipolar integrated circuit receives bigger concern.In the design of bipolar integrated circuit, verification technique and method seem more and more important.This be because: the checking link be to impel the important assurance that designs successfully, the technology of bipolar integrated circuit than MOS integrated circuit complexity many, and the kind of the primary element of formation bipolar integrated circuit is also various than the MOS integrated circuit, the easier appearance of mistake in the design, avoiding the main method that design error takes place is to take strict checking means.Therefore, the validation problem in the design process, for bipolar integrated circuit, even more important than the MOS integrated circuit.
It is generally acknowledged, a complete Integrated Circuit CAD system must comprise a multiple functional verification system, obtained reliable layout data with the design of guaranteeing integrated circuit before plate-making and flow, these data are through definite check, and its electrical property is right-on.The verification system that called function is complete should comprise drc-, circuit extraction, and extracted and functional block are extracted.Simultaneously, for the circuit that extracts, need make breadboardin; For the logic that extracts, need do logic simulation.Here in fact said checking is meant contents such as identification, inspection, check.
The electric network consistency relatively is the result according to domain and circuit diagram extraction, the circuit and the intrinsic circuit that are extracted are carried out consistency process relatively, to check designed circuit whether to be consistent with former design standard circuit at aspects such as parameter, topological structure and interconnection, obviously, this is the prerequisite that guarantees the design correctness.Industry is thought: the electric network consistency in the bipolar integrated circuit design compares, and its enforcement is more much more difficult than the electric network consistency of MOS integrated circuit.
The present invention only relates to the validation problem of bipolar integrated circuit.A kind of effective verification method, it is accomplished in the present invention that we are referred to as " comparatively validate method ".This comparatively validate method is specially adapted to bipolar integrated circuit.
The relevant patent of this class prior art has:
(1) patent of Texas ,Usa instrument company (U.S. De Kesa phase state): VLSI static random access memory (Chinese patent publication number 1043587, application number 89103683.0);
(2) patent of Matsushita industry strain formula branch (Osaka, Japan): semiconductor integrated circuit layout design method (Chinese patent publication number 1102508, application number 94106710.6).
Above prior art only relates to problems such as the relevant verification technique of MOS integrated circuit and graphics process thereof, do not relate to the bipolar integrated circuit design in relevant validation problem and the bipolar integrated circuit electric network consistency in designing relatively wait problem.
In view of above situation, obtain the applicant before the achievement of present comparatively validate method, the applicant had once proposed a kind of verification method of just putting that is called, and as shown in Figure 1, the verification method block diagram of Fig. 1 for just putting comprises:
(1) graphics edition carries out necessary processing to the original layout data that will verify; (2) layout data forms normalized layout data on the basis of above-mentioned graphics edition; (3) Design Rule Checking is carried out the drc-of domain according to above-mentioned layout data, is actually the checking of carrying out the domain level; (4) circuit extraction to the extraction of domain/circuit, that is, is extracted circuit meshwork list from above-mentioned layout data; (5) breadboardin to the circuit of the extraction gained of domain/circuit, is analyzed and function is checked from circuit grade, and this is the checking of carrying out circuit stages; (6) extracted is that circuit diagram and logic diagram are extracted, that is, and and extraction logic figure from foregoing circuit net table; (7) logic simulation to the logic diagram of circuit diagram and logic diagram extraction gained, is analyzed and the function check from logical level, and this is the checking of carrying out logic level.
Said integrated circuit checking link is that the object that is verified is directly carried out one-side checking, these three other information of level of logic diagram to liking treated layout data, being extracted the circuit diagram of gained and being extracted gained.If deviation or mistake in the process of obtaining above-mentioned three class information, occur, then will influence the correctness of checking.In real work, if the scale of integrated circuit is less, above-mentioned deviation or mistake may not occur, but in the current very lagre scale integrated circuit (VLSIC) stage, because scale is big, data are many, and this type of deviation is unavoidable.
(3) summary of the invention
In view of above situation, the objective of the invention is on the basis of the applicant's the first verification method of putting, to have proposed a kind of effective checking and electric network consistency comparative approach of bipolar integrated circuit design.Comparatively validate method of the present invention is that identifying object and former design object are compared in each link, be exactly, being extracted gained circuit diagram, logic diagram and intrinsic circuit diagram, logic diagram, compare one to one, on the basis of compare OK, carry out the checking of each link, like this, just can obtain accurate, effectively checking.
The object of the present invention is achieved like this:
A kind of effective checking and electric network consistency comparative approach of bipolar integrated circuit design, it comprises: the circuit and the intrinsic circuit of the method for effective checking of bipolar integrated circuit design and the extraction gained in effectively verifying carry out electric network consistency method relatively;
(1) the comparatively validate method of described bipolar integrated circuit comprises:
S
1Step: the functional description of the bipolar integrated circuit that is designed, this is the starting point of bipolar integrated circuit design, is the functional description of chip, with this foundation as design, its functional description is from user's requirement;
S
2Step: the system design of the bipolar integrated circuit that is designed, functional description is configured to a system, finish the functional requirement of chip by this system;
S
3Step: the logical design of the bipolar integrated circuit that is designed, this is the first step that integrated circuit enters substantive design, in this design phase, the user must operate by logic the functional requirement of chip and realize that logical design claims logic synthesis again;
S
4Step: the logic simulation of the bipolar integrated circuit that is designed, logic simulation are that the check of logic analysis and logic function is carried out in the logical design that the above-mentioned design phase finishes, to confirm the correctness of logical design;
S
5Step: the circuit design of the bipolar integrated circuit that is designed, circuit design is the intermediate link from logical design to layout design, its objective is to determine circuit element and interconnected relationship thereof, and circuit design claims circuit synthesis again, when describing a plurality of circuit, circuit is with regard to the general term electric network;
S
6Step: the breadboardin of the bipolar integrated circuit that is designed, breadboardin are the checks of the electric network of above-mentioned design being carried out circuit analysis and circuit function, to confirm the correctness of circuit design;
S
7Step: the layout design of the bipolar integrated circuit that is designed, layout design are the final tache in the integrated circuit (IC) design, and be most important, and logical design, circuit design and layout design are three important steps in the entire chip design;
S
8Step: the layout data of the bipolar integrated circuit that is designed, layout data are the data formats of the result of above-mentioned layout design being compiled regularization, from layout data, just enter the stage of " comparatively validate method " of the present invention;
Following S
9Step begins, and changes checking over to from design:
S
9Step: the Design Rule Checking of the bipolar integrated circuit that is verified, Design Rule Checking, this is the first step that the result to layout design effectively verifies;
S
10Step: the circuit extraction of the bipolar integrated circuit that is verified, circuit extraction claim domain and circuit diagram to extract again, wish that the circuit and the intrinsic circuit that extract gained have consistency, for this reason, and be to S
10Step and S
5Step is carried out the electric network consistency relatively;
S
11Step: the breadboardin of the bipolar integrated circuit that is verified, the breadboardin here are that the circuit that domain and circuit diagram extract gained is carried out the simulation of circuit stages, belong to the checking category, then, and be to S
11Step and S
6Step is carried out circuit characteristic relatively, and this is the characteristics of comparatively validate method of the present invention;
S
12Step: the extracted of the bipolar integrated circuit that is verified, extracted claim circuit diagram and logic diagram to extract again, wish to extract the logical network of gained, that is, the logical network of gained has consistency in logic level circuit and the former logical design, for this reason, and be to S
12Step and S
3Step is carried out the logical network consistency relatively;
S
13Step: the logic simulation of the bipolar integrated circuit that is verified, the logic simulation here are that the logical network of circuit diagram and logic diagram extraction gained is carried out the simulation of logic level, belong to the checking category, then, and be to S
13Step and S
4Step is carried out logic behaviour relatively, and this is the characteristics of comparatively validate method of the present invention;
S
14Step: the functional block of the bipolar integrated circuit that is verified is extracted, and it is that logic function block higher level on the extracted basis extracts that functional block is extracted;
S
15Step: the graphics edition that layout data is handled;
(2) method of described electric network consistency comparison comprises:
V
1Step: the net table information input of circuit that is extracted and former design standard circuit, this is to carry out electric network consistency first step relatively, be the net table information input native system circuit diagram that is extracted out in domain in the comparatively validate method of above-mentioned bipolar integrated circuit and the circuit diagram extraction and former design standard circuit, these information are bases of the whole workflows of the present invention;
V
2Step: the formation of incidence matrices to be compared and primary standard incidence matrices, according to net table information, form two polynary figure and incidence matrices thereof respectively, Here it is: the polynary figure and the incidence matrices thereof of the polynary figure of the circuit that is extracted out and incidence matrices thereof and former design standard circuit, claim that the former is an incidence matrices to be compared, the latter is the standard association matrix;
V
3Step: can two incidence matrices are implemented line ordering and division, be to investigate it develop towards the consistency direction to above-mentioned two incidence matrices enforcement ordering and division;
V
4Step: whether more above-mentioned two incidence matrices have consistency, if do not have consistency, then print error message, if having consistency, then to next V
5Step;
V
5Step: again two incidence matrices are implemented the row, column exchange, investigate whether it consistent;
V
6Step: more above-mentioned V
2Whether two incidence matrices that form in the step are consistent, if inconsistent, then print error message, if consistent, then finished the electric network consistency relatively;
V
7Step: comparative result has reached consistent, confirms the electric network consistency;
V
8Step: at above-mentioned V
2Under two inconsistent situations of incidence matrices that form in the step, that is, under the more inconsistent situation of electric network, print error message.
Effect of the present invention:
1) tightness: electric network consistency of the present invention relatively is to be based upon on the strict topological basis, the inventor has used the theory of polynary figure in the graph theory, the node of polynary figure and the element of two isomorphic graphs of net have creatively been conceived, in the algorithm implementation process, creatively proposed the tax power method of each element among the polynary figure again, made the isomorphism that is verified circuit and former design standard circuit relatively become complete possibility;
(2) versatility: electric network consistency of the present invention relatively, owing to be based upon on the tight theoretical foundation, it is applicable to various types of integrated circuits, above-mentioned tight theoretical foundation, all bipolar integrated circuits and polytype MOS integrated circuit have been contained, the integrated circuit that comprises NMOS, PMOS and CMOS technology, because say in principle, bipolar integrated circuit is complicated than the MOS integrated circuit.Polynary figure and topological isomorphism method both be applicable to bipolar integrated circuit, were applicable to the MOS integrated circuit again.
For further specifying above-mentioned purpose of the present invention, design feature and effect, the present invention is described in detail below with reference to accompanying drawing.
(4) description of drawings
Fig. 1 is the first verification method block diagram of putting of prior art;
Fig. 2 is the comparatively validate method general diagram of bipolar integrated circuit of the present invention;
Fig. 3 is the embodiment of a polynary figure;
Fig. 4 is the incidence matrices of polynary figure among Fig. 3;
The electric network consistency block diagram relatively that Fig. 5 proposes for the present invention.
(5) embodiment
Technology contents of the present invention has two parts: first is the effective verification method in the bipolar integrated circuit design; Second portion is the electric network consistency comparative approach in the bipolar integrated circuit design.
Effective verification method in the first in the bipolar integrated circuit design is the general steps to integrated circuit verification method, the step of " verification method relatively " that this proposes on above-mentioned prior art " verification method of just putting " basis.Electric network consistency comparative approach in the second portion in the bipolar integrated circuit design is the verification step at the checking of the circuit stages in first link, because the circuit stages checking is the intermediate link in the whole verification step, play a part to form a connecting link, the accuracy that guarantees this link is to improve the key point of whole verification technique.
Above-mentioned two-part content is described in detail in detail below with reference to the accompanying drawings.
First: the effective verification method in the bipolar integrated circuit design.
The technology of this part can be made into a large-scale instrument, is called bipolar integrated circuit comparatively validate device.
So-called comparatively validate is realized effective checking with method relatively exactly, and its general diagram as shown in Figure 2.
Fig. 2 is the comparatively validate method general diagram of bipolar integrated circuit of the present invention
The comparatively validate method of bipolar integrated circuit comprises:
S
1Step: the functional description of the bipolar integrated circuit that is designed, this is the starting point of bipolar integrated circuit design, is the functional description of chip, with this foundation as design, its functional description is from user's requirement;
S
2Step: the system design of the bipolar integrated circuit that is designed, functional description is configured to a system, finish the functional requirement of chip by this system;
S
3Step: the logical design of the bipolar integrated circuit that is designed, this is the first step that integrated circuit enters substantive design, in this design phase, the user must operate by logic the functional requirement of chip and realize.Logical design claims logic synthesis again;
S
4Step: the logic simulation of the bipolar integrated circuit that is designed, logic simulation are that the check of logic analysis and logic function is carried out in the logical design that the above-mentioned design phase finishes, to confirm the correctness of logical design;
S
5Step: the circuit design of the bipolar integrated circuit that is designed, circuit design is the intermediate link from logical design to layout design, its objective is to determine circuit element and interconnected relationship thereof, and circuit design claims circuit synthesis again, when describing a plurality of circuit, circuit is with regard to the general term electric network;
S
6Step: the breadboardin of the bipolar integrated circuit that is designed, breadboardin are the checks of the electric network of above-mentioned design being carried out circuit analysis and circuit function, to confirm the correctness of circuit design;
S
7Step: the layout design of the bipolar integrated circuit that is designed, layout design are the final tache in the integrated circuit (IC) design, and be most important, and logical design, circuit design and layout design are three important steps in the entire chip design;
S
8Step: the layout data of the bipolar integrated circuit that is designed, layout data are the data formats of the result of above-mentioned layout design being compiled regularization, from layout data, just enter the stage of " comparatively validate method " of the present invention;
(following S
9Step begins, and changes checking over to from design)
S
9Step: the Design Rule Checking of the bipolar integrated circuit that is verified, Design Rule Checking, this is the first step that the result to layout design effectively verifies;
S
10Step: the circuit extraction of the bipolar integrated circuit that is verified, circuit extraction claim domain and circuit diagram to extract again, wish that the circuit and the intrinsic circuit that extract gained have consistency, for this reason, and be to S
10Step and S
5Step is carried out the electric network consistency relatively;
S
11Step: the breadboardin of the bipolar integrated circuit that is verified, the breadboardin here are that the circuit that domain and circuit diagram extract gained is carried out the simulation of circuit stages, belong to the checking category, then, and be to S
11Step and S
6Step is carried out circuit characteristic relatively, and this is the characteristics of comparatively validate method of the present invention;
S
12Step: the extracted of the bipolar integrated circuit that is verified, extracted claim circuit diagram and logic diagram to extract again, wish to extract the logical network of gained, that is, the logical network of gained has consistency in logic level circuit and the former logical design, for this reason, and be to S
12Step and S
3Step is carried out the logical network consistency relatively;
S
13Step: the logic simulation of the bipolar integrated circuit that is verified, the logic simulation here are that the logical network of circuit diagram and logic diagram extraction gained is carried out the simulation of logic level, belong to the checking category, then, and be to S
13Step and S
4Step is carried out logic behaviour relatively, and this is the characteristics of comparatively validate method of the present invention;
S
14Step: the functional block of the bipolar integrated circuit that is verified is extracted, and it is that logic function block higher level on the extracted basis extracts that functional block is extracted;
S
15Step: the graphics edition that layout data is handled.
The main feature of above-mentioned " comparatively validate method ":
(1) reliability: comparatively validate method of the present invention is that logical link result in the design process and the logical link in the proof procedure are carried out equity relatively, this relatively is reciprocity, balanced, practical, thereby be reliable, equally, circuit link result in the design process and the circuit link in the proof procedure are carried out equity relatively, and this more also is reciprocity, balanced, practical, thereby also be reliable.
(2) reasonability and tightness: comparatively validate method of the present invention compares three levels (domain level, circuit stages, logic level) in three levels (domain level, circuit stages, logic level) in the design process and the proof procedure one by one.The comparison consistency of three levels of every acquisition just can be confirmed overall consistency, and this has just guaranteed the reasonability of this verification method.Simultaneously, as long as there is a level can not accomplish the consistency of comparison, just can veto the correctness of design, this has fully shown tightness of the present invention.
Second portion: the electric network consistency comparative approach in the bipolar integrated circuit design:
Bipolar integrated circuit identification is to determine whether the electrical property that is designed domain has reached the designing requirement that original users provides with the final purpose of checking.The electrical schematic diagram that extracts from domain has only through further check and check, could determine its correctness.In the circuit stages scope, this further check and check comprise conforming checking of electric network and comparison.The present invention proposes a kind of method that how the electric network consistency of bipolar integrated circuit is directly compared.
By the circuit that layout extraction obtains, the consistency comparison of it and primary circuit can sum up in the point that on algorithm the homoorganicity of figure in the graph theory differentiates algorithm.In theory, it is np problem that the homoorganicity of figure is differentiated algorithm, is difficult to realize.But the polynary figure in real work in the application drawing of the present invention opinion is theoretical and in conjunction with the characteristics of electrical schematic diagram in the bipolar integrated circuit, makes to be extracted circuit and to be achieved with the differentiation of primary circuit figure consistency.
The matrix M of a m * n is if having relation one to one, its element m with a polynary figure G
IjSatisfy:
Claim that then M is the incidence matrices of this polynary figure G, this incidence matrices is the electric network consistency mathematical tool relatively that the applicant is used as bipolar integrated circuit initiatively, net of each line display of matrix, and a node is shown in each tabulation.
Fig. 3 has provided the embodiment of a polynary figure, and Fig. 4 is the incidence matrices of this polynary figure.
If (A, R) (A exists between R) and shines upon α one to one, β, and satisfy α (A)=A, β (R)=R, then G and G isomorphic graphs each other with G=for two polynary figure G=.
If incidence matrices M and the M of two polynary figure G and G after the exchange through the row of limited number of time and row, can satisfy M=M, G and G isomorphic graphs each other then.
Above-mentioned polynary figure and isomorphic graphs are the electric network consistency mathematical tools relatively that the applicant is used as bipolar integrated circuit initiatively.
If circuit diagram, or perhaps electric network figure can the abstract form that becomes polynary figure, just can be differentiated whether isomorphism of two circuit diagrams by means of incidence matrices, are isomorphisms as if two β electric network figure, and then two electric networks just have identical topological structure.So, the consistency of electric network is differentiated the homoorganicity that problem just can be converted into their corresponding polynary figure and is differentiated problem.
Referring to Fig. 5, the electric network consistency block diagram relatively that Fig. 5 proposes for the present invention.
The method of electric network consistency comparison comprises:
V
1Step: the net table information input of circuit that is extracted and former design standard circuit, this is to carry out electric network consistency first step relatively, be the net table information input native system circuit diagram that is extracted out in domain in the comparatively validate method of above-mentioned bipolar integrated circuit and the circuit diagram extraction and former design standard circuit, these information are bases of the whole workflows of the present invention;
V
2Step: the formation of incidence matrices to be compared and primary standard incidence matrices, according to net table information, form two polynary figure and incidence matrices thereof respectively, Here it is: the polynary figure and the incidence matrices thereof of the polynary figure of the circuit that is extracted out and incidence matrices thereof and former design standard circuit, claim that the former is an incidence matrices to be compared, the latter is the standard association matrix;
V
3Step: can two incidence matrices are implemented line ordering and division, be to investigate it develop towards the consistency direction to above-mentioned two incidence matrices enforcement ordering and division;
V
4Step: whether more above-mentioned two incidence matrices have consistency, if do not have consistency, then print error message, if having consistency, then to next V
5Step;
V
5Step: again two incidence matrices are implemented the row, column exchange, investigate whether it consistent;
V
6Step: more above-mentioned V
2Whether two incidence matrices that form in the step are consistent, if inconsistent, then print error message, if consistent, then finished the electric network consistency relatively;
V
7Step: comparative result has reached consistent, confirms the electric network consistency;
V
8Step: at above-mentioned V
2Under two inconsistent situations of incidence matrices that form in the step, that is, under the more inconsistent situation of electric network, print error message.
Those of ordinary skill in the art will be appreciated that, above embodiment is used for illustrating the present invention, and be not to be used as limitation of the invention, as long as in connotation scope of the present invention, all will drop in the scope of claims of the present invention variation, the modification of the above embodiment.
Claims (3)
1, a kind of effective checking and electric network consistency comparative approach of bipolar integrated circuit design, its feature comprises: the circuit and the intrinsic circuit of the method for effective checking of bipolar integrated circuit design and the extraction gained in effectively verifying carry out electric network consistency method relatively;
(1) the comparatively validate method of described bipolar integrated circuit comprises:
S
1Step: the functional description of the bipolar integrated circuit that is designed, this is the starting point of bipolar integrated circuit design, is the functional description of chip, with this foundation as design, its functional description is from user's requirement;
S
2Step: the system design of the bipolar integrated circuit that is designed, functional description is configured to a system, finish the functional requirement of chip by this system;
S
3Step: the logical design of the bipolar integrated circuit that is designed, this is the first step that integrated circuit enters substantive design, in this design phase, the user must operate by logic the functional requirement of chip and realize that logical design claims logic synthesis again;
S
4Step: the logic simulation of the bipolar integrated circuit that is designed, logic simulation are that the check of logic analysis and logic function is carried out in the logical design that the above-mentioned design phase finishes, to confirm the correctness of logical design;
S
5Step: the circuit design of the bipolar integrated circuit that is designed, circuit design is the intermediate link from logical design to layout design, its objective is to determine circuit element and interconnected relationship thereof, and circuit design claims circuit synthesis again, when describing a plurality of circuit, circuit is with regard to the general term electric network;
S
6Step: the breadboardin of the bipolar integrated circuit that is designed, breadboardin are the checks of the electric network of above-mentioned design being carried out circuit analysis and circuit function, to confirm the correctness of circuit design;
S
7Step: the layout design of the bipolar integrated circuit that is designed, layout design are the final tache in the integrated circuit (IC) design, and be most important, and logical design, circuit design and layout design are three important steps in the entire chip design;
S
8Step: the layout data of the bipolar integrated circuit that is designed, layout data are the data formats of the result of above-mentioned layout design being compiled regularization, from layout data, just enter the stage of " comparatively validate method " of the present invention;
Following S
9Step begins, and changes checking over to from design:
S
9Step: the Design Rule Checking of the bipolar integrated circuit that is verified, Design Rule Checking, this is the first step that the result to layout design effectively verifies;
S
10Step: the circuit extraction of the bipolar integrated circuit that is verified, circuit extraction claim domain and circuit diagram to extract again, wish that the circuit and the intrinsic circuit that extract gained have consistency, for this reason, and be to S
10Step and S
5Step is carried out the electric network consistency relatively;
S
11Step: the breadboardin of the bipolar integrated circuit that is verified, the breadboardin here are that the circuit that domain and circuit diagram extract gained is carried out the simulation of circuit stages, belong to the checking category, then, and be to S
11Step and S
6Step is carried out circuit characteristic relatively, and this is the characteristics of comparatively validate method of the present invention;
S
12Step: the extracted of the bipolar integrated circuit that is verified, extracted claim circuit diagram and logic diagram to extract again, wish to extract the logical network of gained, that is, the logical network of gained has consistency in logic level circuit and the former logical design, for this reason, and be to S
12Step and S
3Step is carried out the logical network consistency relatively;
S
13Step: the logic simulation of the bipolar integrated circuit that is verified, the logic simulation here are that the logical network of circuit diagram and logic diagram extraction gained is carried out the simulation of logic level, belong to the checking category, then, and be to S
13Step and S
4Step is carried out logic behaviour relatively, and this is the characteristics of comparatively validate method of the present invention;
S
14Step: the functional block of the bipolar integrated circuit that is verified is extracted, and it is that logic function block higher level on the extracted basis extracts that functional block is extracted;
S
15Step: the graphics edition that layout data is handled;
(2) method of described electric network consistency comparison comprises:
V
1Step: the net table information input of circuit that is extracted and former design standard circuit, this is to carry out electric network consistency first step relatively, be the net table information input native system circuit diagram that is extracted out in domain in the comparatively validate method of above-mentioned bipolar integrated circuit and the circuit diagram extraction and former design standard circuit, these information are bases of the whole workflows of the present invention;
V
2Step: the formation of incidence matrices to be compared and primary standard incidence matrices, according to net table information, form two polynary figure and incidence matrices thereof respectively, Here it is: the polynary figure and the incidence matrices thereof of the polynary figure of the circuit that is extracted out and incidence matrices thereof and former design standard circuit, claim that the former is an incidence matrices to be compared, the latter is the standard association matrix;
V
3Step: can two incidence matrices are implemented line ordering and division, be to investigate it develop towards the consistency direction to above-mentioned two incidence matrices enforcement ordering and division;
V
4Step: whether more above-mentioned two incidence matrices have consistency, if do not have consistency, then print error message, if having consistency, then to next V
5Step;
V
5Step: more above-mentioned two incidence matrices are implemented the row, column exchange, investigate whether it consistent;
V
6Step: more above-mentioned V
2Whether two incidence matrices that form in the step are consistent, if inconsistent, then print error message, if consistent, then finished the electric network consistency relatively;
V
7Step: comparative result has reached consistent, confirms the electric network consistency;
V
8Step: at above-mentioned V
2Under two inconsistent situations of incidence matrices that form in the step, that is, under the more inconsistent situation of electric network, print error message.
2, the effective checking and the electric network consistency comparative approach of bipolar integrated circuit design as claimed in claim 1 is characterized in that described incidence matrices is:
The matrix M of a m * n is if having relation one to one, its element m with a polynary figure G
IjSatisfy:
Claim that then M is the incidence matrices of this polynary figure G, net of each line display of matrix, a node is shown in each tabulation.
3, the effective checking and the electric network consistency comparative approach of bipolar integrated circuit design as claimed in claim 1 is characterized in that described two polynary figure, are made as: G=(A, R) with G=(A, R), between exist and shine upon α one to one, β, and satisfy α (A)=A, β (R)=R, then G and G isomorphic graphs each other, incidence matrices M and the M of two polynary figure G and G, after the exchange through the row of limited number of time and row, can satisfy M=M, then G and G isomorphic graphs each other.
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| CNB031154832A CN1298047C (en) | 2003-02-21 | 2003-02-21 | Validity verification of bipolar integrated circuit design and electric network consistency comparison method |
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| CN102314523B (en) * | 2010-06-30 | 2012-09-26 | 中国科学院微电子研究所 | Method for accelerating analysis and optimization of physical layout of integrated circuit |
| CN102508981B (en) * | 2011-11-25 | 2014-06-18 | 中国科学院微电子研究所 | Method and device for accelerating CMP simulation |
| SG11201708469PA (en) * | 2015-05-13 | 2017-11-29 | Mitsubishi Electric Corp | Control logic diagram analysis device and control logic diagram analysis method |
| CN109444651B (en) * | 2018-12-29 | 2021-02-02 | 云南电网有限责任公司电力科学研究院 | Monitoring method and system for secondary circuit |
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| JP2000124320A (en) * | 1998-10-14 | 2000-04-28 | Mitsubishi Electric Corp | Method and device for verifying layout |
| US6321186B1 (en) * | 1999-05-03 | 2001-11-20 | Motorola, Inc. | Method and apparatus for integrated circuit design verification |
| CN1347149A (en) * | 2000-09-29 | 2002-05-01 | 株式会社鼎新 | Compound integrated circuit design verification method |
| JP2002358342A (en) * | 2001-05-31 | 2002-12-13 | Matsushita Electric Ind Co Ltd | Apparatus for circuit verification |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000124320A (en) * | 1998-10-14 | 2000-04-28 | Mitsubishi Electric Corp | Method and device for verifying layout |
| US6321186B1 (en) * | 1999-05-03 | 2001-11-20 | Motorola, Inc. | Method and apparatus for integrated circuit design verification |
| CN1347149A (en) * | 2000-09-29 | 2002-05-01 | 株式会社鼎新 | Compound integrated circuit design verification method |
| JP2002358342A (en) * | 2001-05-31 | 2002-12-13 | Matsushita Electric Ind Co Ltd | Apparatus for circuit verification |
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