JP2017162429A - Information processing device and method, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the man-hour for correction processing in comparison with a prior art in a verification process of a layout verification rule, thereby improving the efficiency of correcting the rule.SOLUTION: An information processing device that verifies a layout verification rule which is used in verifying the layout of a semiconductor integrated circuit includes: comparison means that compares a layout verification pattern, which is used in verifying the layout verification design rule, with the layout verification rule and generates comparison information including differences that are results of the comparison; and correction means that corrects, if the differences are obtained, the layout verification rule on the basis of the comparison information. The comparison information is, for example, information on a mismatch between the wiring width of a layout verification test pattern and the wiring width prescribed in the layout verification design rule.SELECTED DRAWING: Figure 3

Description

  The present invention relates to an information processing apparatus and method for correcting a layout verification rule of a semiconductor integrated circuit such as an LSI or an IC, and a program.

  In designing a semiconductor integrated circuit, a layout verification process is performed to check whether a layout called a mask pattern satisfies a design rule defined by a manufacturing process. The layout verification process is performed by inputting a layout verification design rule file in which design rules and commands of the tool are described in a layout verification tool (DRC (Design Rule Check) tool). Hereinafter, the design rule for layout verification is referred to as “DRC rule”. The DRC rule file is referred to as a “DRC rule file”.

  That is, if the DRC rule file contains an error, accurate layout verification cannot be performed, and a layout that does not satisfy the design rule is created, resulting in a reduction in the design quality of the semiconductor circuit. Since the DRC rule file is manually created or may be manually modified after being automatically created by a tool or the like, it often contains errors. For this reason, it is already known that it is necessary to check whether the DRC rule file itself is correctly created using a test pattern for verification (see, for example, Patent Document 1).

  In the layout verification step, the LVS rule in which the command of the tool is described is input to a layout verification tool (LVS (Layout Versus Schematic) tool) (see, for example, Non-Patent Document 2). That is, if an error is included in the LVS rule, accurate layout verification cannot be performed, so that a layout that does not satisfy the circuit information is created, and the design quality of the semiconductor circuit is degraded. In order to accurately create an LVS rule, it is already known to create a LVS rule while checking the content of the rule using a device layout pattern for verification. Hereinafter, the device layout rule for layout verification is referred to as “LVS rule”. An LVS rule file is referred to as an “LVS rule file”.

  However, in the verification of the DRC rule file using the conventional test pattern, the layout verification is performed, and it is determined whether the obtained verification result is appropriate by comparing with the design rule, and the DRC rule file is manually determined from the result. There is a problem that a great deal of labor is required. Also, there was a similar problem with the modification of the LVS rule file.

  An object of the present invention is to provide an information processing apparatus that solves the above-described problems and can reduce the number of man-hours for correction processing in the layout verification rule verification process as compared with the prior art and can improve the correction efficiency of the rules. It is to provide.

An information processing apparatus according to the present invention is an information processing apparatus that verifies a layout verification rule used when verifying a layout of a semiconductor integrated circuit.
Comparing means for comparing a layout verification pattern used when verifying the layout verification rule with the layout verification rule, and generating comparison information including a difference as a comparison result. .

  According to the information processing apparatus of the present invention, in the verification process of the layout verification rule, the number of correction processes can be reduced as compared with the prior art, and the correction efficiency of the rule can be increased.

It is a block diagram which shows the structure of the information processing system containing the information processing apparatus 1 which is the rule file correction apparatus for layout verification concerning one Embodiment of this invention. It is a flowchart which shows the judgment execution process of the rule comparison correction process performed by the information processing apparatus 1 of FIG. It is a flowchart which shows the DRC rule comparison correction process (S2, S5) performed by the DRC rule comparison correction process part 10 of the information processing apparatus 1 of FIG. It is a flowchart which shows the DRC rule correction subroutine process (S13) which is a subroutine of FIG. It is a top view which shows the structural example 1 of the test pattern used in the DRC rule comparison correction process of FIG. It is a top view which shows the structural example 2 of the test pattern used in the DRC rule comparison correction process of FIG. It is a top view which shows the structural example 3 of the test pattern used in the DRC rule comparison correction process of FIG. It is a figure which shows the structural example of the DRC rule file 12 stored in the memory | storage device 4 of FIG. It is a figure which shows the structural example of the comparison information file 14 stored in the memory | storage device 4 of FIG. It is a figure which shows the specific example of the DRC rule file 12 stored in the memory | storage device 4 of FIG. It is a figure which shows the specific example of the comparison information file 14 stored in the memory | storage device 4 of FIG. It is a figure which shows the specific example of the DRC rule file after correction 13 stored in the memory | storage device 4 of FIG. It is a figure which shows the comparison information file 14 stored in the memory | storage device 4 of FIG. 3 is a flowchart showing LVS rule comparison / correction processing (S3, S7) executed by an LVS rule comparison / correction processing unit 50 of the information processing apparatus 1 of FIG. It is a flowchart which shows the LVS rule correction subroutine process (S33) which is a subroutine of FIG. FIG. 3 is a plan view illustrating a configuration example of a device layout pattern stored in a device layout pattern file 51 of the storage device 4 in FIG. 1. It is a figure which shows the specific example of the LVS rule file 52 stored in the memory | storage device 4 of FIG. It is a figure which shows the specific example of the LVS rule file 52 stored in the memory | storage device 4 of FIG. It is a figure which shows the specific example of the LVS rule file 52 stored in the memory | storage device 4 of FIG. It is a figure which shows the specific example of the comparison process (S41) performed by the information processing apparatus 1 of FIG. It is a figure which shows the specific example of the LVS rule file 52 stored in the memory | storage device 4 of FIG. FIG. 7 is a plan view showing a specific example of a device layout pattern stored in a device layout pattern file 51 of the storage device 4 of FIG. 1. FIG. 7 is a plan view showing a specific example of a device layout pattern stored in a device layout pattern file 51 of the storage device 4 of FIG. 1. It is a figure which shows the specific example of the LVS rule file 52 before the correction | amendment stored in the memory | storage device 4 of FIG. It is a figure which shows the specific example of the LVS rule file 53 after correction | amendment stored in the memory | storage device 4 of FIG. It is a figure which shows the specific example of the LVS rule file 52 before the correction | amendment stored in the memory | storage device 4 of FIG. It is a figure which shows the specific example of the LVS rule file 53 after correction | amendment stored in the memory | storage device 4 of FIG. It is a figure which shows the specific example of the comparison process (S41A) which concerns on the modification 1 performed by the information processing apparatus 1 of FIG. It is a figure which shows the specific example of the LVS rule file 53A after correction | amendment corrected by the correction process after the comparison process (S41A) of FIG. It is a figure which shows the specific example of the comparison process (S41B) which concerns on the modification 2 performed by the information processing apparatus 1 of FIG. It is a figure which shows the specific example of the LVS rule file 53B after correction | amendment corrected by the correction process after the comparison process (S41B) of FIG.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.

  FIG. 1 is a block diagram showing a configuration of an information processing system including an information processing apparatus 1 which is a layout verification rule file correction apparatus according to an embodiment of the present invention. The information processing apparatus 1 according to the present embodiment is provided for verifying a layout verification design rule (DRC rule) and a layout verification device layout rule (LVS rule) used when verifying the layout of a semiconductor integrated circuit. Is done. The information processing apparatus 1 includes a DRC rule comparison / correction processing unit 10 that compares a layout verification design rule with a layout verification test pattern corresponding to the design rule, and corrects a DRC rule file based on the comparison result. The information processing apparatus 1 includes an LVS rule comparison / correction processing unit 50 that compares a layout verification device layout rule with a layout verification device layout pattern corresponding to the device layout rule and corrects an LVS rule file based on the comparison result. . Here, the layout verification design rule (DRC rule) and the layout verification device layout rule (LVS rule) are collectively referred to as “layout verification rule”. The layout verification test pattern and the layout verification device layout pattern are collectively referred to as a “layout verification pattern”.

  The information processing system in FIG. 1 inputs an information processing apparatus 1 including a DRC rule comparison / correction processing unit 10 and an LVS rule comparison / correction processing unit 50, a keyboard 2 for inputting a predetermined data file and a command, a command, and the like. A mouse 3, a storage device 4, and a display device 5 are provided. Here, the information processing apparatus 1 is a computer such as a digital computer.

  The DRC rule comparison / correction processing unit 10 of the information processing apparatus 1 performs a DRC rule comparison / correction process (DRC rule of FIG. 4) based on input from the keyboard 2 and mouse 3, data stored in the storage device 4, and the like. (Including correction subroutine processing). Then, the DRC rule comparison / correction processing unit 10 displays the corrected DRC rule, which is the processing result, on the display device 5 and writes it in the storage device 4. Further, the LVS rule comparison / correction processing unit 50 of the information processing device 1 performs the LVS rule comparison / correction processing (FIG. 11) of FIG. (Including LVS rule correction subroutine processing). Then, the LVS rule comparison / correction processing unit 50 displays the corrected LVS rule as the processing result on the display device 5 and writes it in the storage device 4.

  The keyboard 2 inputs commands and the like for DRC rule comparison / correction processing. The mouse 3 is used as a command input auxiliary means for DRC rule comparison / correction processing when an instruction is given using a GUI (Graphical User Interface) for input or display. Here, not only the mouse 3 but also a pointing device such as a tablet or a trackball may be used.

  The storage device 4 includes a test pattern file 11, a DRC rule file 12, a modified DRC rule file 13, and a comparison information file 14. The storage device 4 includes a device layout pattern file 51, an LVS rule file 52, a modified LVS rule file 53, and a comparison information file 54. The display device 5 displays an execution state and a result file in response to an input from the keyboard 2 or the mouse 3.

  FIG. 2 is a flowchart showing the determination execution process of the rule comparison correction process executed by the information processing apparatus 1 of FIG.

  In step S1 of FIG. 2, it is determined whether or not both the DRC rule comparison / correction process and the LVS rule comparison / correction process are executed. If YES, the process proceeds to step S2, while if NO, the process proceeds to step S4. . In step S2, a DRC rule comparison / correction process is executed. In step S3, an LVS rule comparison / correction process is executed, and the determination execution process ends. In step S4, it is determined whether or not only the DRC rule comparison / correction process is executed. If YES, the process proceeds to step S5. If NO, the process proceeds to step S6. In step S5, the DRC rule comparison / correction process is executed, and the determination execution process ends. In step S6, it is determined whether or not only the LVS rule comparison / correction process is executed. If YES, the process proceeds to step S7. If NO, the determination execution process is terminated. In step S7, the LVS rule comparison / correction process is executed, and the determination execution process ends.

  Next, the operation of the DRC rule comparison / correction processing unit 10 of FIG. 1 will be described with reference to the flowchart of FIG.

  FIG. 3 is a flowchart showing DRC rule comparison / correction processing (S2, S5) executed by the DRC rule comparison / correction processing unit 10 of the information processing apparatus 1 of FIG. The DRC rule comparison / correction process of FIG. 3 and the DRC rule correction subroutine process of FIG. 4 are provided in the form of a program executed by the DRC rule comparison / correction processing unit 10 of the information processing apparatus 1 of FIG. Note that the test pattern and the DRC rule are stored in advance in the test pattern file 11 and the DRC rule file 12 in the storage device 4, respectively. Here, the test pattern in the test pattern file 11 stores a pattern laid out exactly so as to match the value specified by the design rule. By inputting these pieces of information to the DRC rule comparison / correction processing unit 10, if there is an error in the DRC rule file 12, a post-correction DRC rule file 13 whose part has been corrected is generated and output.

  In step S11 of FIG. 3, a test pattern is read from the test pattern file 11 in the storage device 4, and a DRC rule is read from the DRC rule file 12 in the storage device 4 in step S12. Next, in step S13, the DRC rule is corrected based on the test pattern, and a corrected DRC rule is generated. Further, in step S14, the corrected DRC rule in the storage device 4 is written in the corrected DRC rule file 13 and displayed on the display device 5, and the DRC rule comparison / correction process is terminated. Return to the main routine.

  FIG. 4 is a flowchart showing a DRC rule correction subroutine process (S13) which is the subroutine of FIG.

  In step S21 in FIG. 4, the value set in the test pattern is compared with the value specified in the DRC rule. The values set in the test pattern are, for example, the pattern name of the test pattern, the minimum width and the minimum interval of the metal wiring. The values defined by the DRC rule are the minimum width and minimum interval of the metal wiring corresponding to the pattern name of the test pattern. In step S22, based on the comparison result, it is determined whether or not there is a difference (a difference including a difference or mismatch between the test pattern and the DRC rule). In step S22, based on the comparison result, it is determined whether or not there is a difference (a difference including a difference or mismatch between the test pattern and the DRC rule). If YES in step S22, the process proceeds to step S23. If NO, the process returns to the original main routine. In step S 23, a comparison information file including comparison information is generated based on the comparison result and written to the comparison information file 14 in the storage device 4. Next, in step S24, after correcting the DRC rule based on the comparison information in the comparison information file 14, the process returns to the original main routine.

  5A to 5C are plan views showing configuration examples 1 to 3 of test patterns used in the DRC rule comparison and correction process of FIG.

  FIG. 5A shows a test pattern for a design rule in which the distance d1 between the outer edges of a pattern including two squares 21 and 22 must satisfy a predetermined value or more. Here, the two quadrilaterals 21 and 22 are layout layers, for example, polysilicon layers, which are patterns for checking the interval between adjacent polysilicons.

  FIG. 5B shows a test pattern for a design rule that includes an outer quadrangle 23 and an inner quadrangle 24 in the outer quadrangle 23, and the edge interval d2 of different layers must satisfy a predetermined value or more. Here, the inner square 24 is, for example, a first via layer, the outer square 23 is, for example, a first metal layer, and the margin that the first metal includes the first via. It is a pattern to check.

  FIG. 5C shows a pattern including one square 25, which is a test pattern for a design rule in which the interval d3 between the inner edges of the pattern must satisfy a predetermined value or more. Here, the rectangle 25 is a layer on the layout, for example, a first metal layer, and has a pattern for checking the width of the first metal.

  Each test pattern in FIGS. 5A to 5C is laid out with the same value as the value of the design rule. For example, when the interval between the outer edges of the pattern is defined as 0.1 μm or more according to the design rule, the interval d1 in FIG. 5A is laid out with the same 0.1 μm.

  FIG. 6 is a diagram showing a configuration example of the DRC rule file 12 stored in the storage device 4 of FIG. The DRC rule in the DRC rule file 12 needs to be described according to the input format of each layout verification tool to be used. The description content includes a comment sentence for the check content, an arithmetic process for each layer graphic, Consists of check values.

  The first to third lines of the DRC rule in FIG. 6 describe the rule of the minimum interval of the first metal, and the content is to check when it is less than 0.1 μm. Moreover, the 5th to 7th lines in FIG. 6 describe the rule for the minimum width of the first metal, and the content is to check when it is less than 0.1 μm.

  FIG. 7 is a diagram showing a configuration example of the comparison information file 14 stored in the storage device 4 of FIG. The comparison information in the comparison information file 14 in FIG. 7 indicates the comparison result between the test pattern and the DRC rule with respect to the first metal minimum interval. The first line of the comparison information describes DRC rule verification items. The second line of the comparison information is the interval between the first metals extracted from the corresponding test pattern, and is 0.1 μm here. The third line of the comparison information is a setting value of the corresponding rule described in the DRC rule, and is 0.11 μm here.

  FIG. 8A is a diagram showing a specific example of the DRC rule file 12 stored in the storage device 4 of FIG. FIG. 8B is a diagram showing a specific example of the comparison information file 14 stored in the storage device 4 of FIG. 8C is a diagram showing a specific example of the modified DRC rule file 13 stored in the storage device 4 of FIG.

  FIG. 8A is a DRC rule showing restrictions on the minimum width of the first metal in the DRC rule file 12 before correction. FIG. 8B shows comparison information in the comparison information file 14, from which a value (0.1 μm) in the test pattern and a set value in the DRC rule can be read. FIG. 8C is a modified DRC rule in the modified DRC rule file 13, and based on the comparison information of FIG. 8B, the setting value (0.11 μm) in FIG. 8A is modified to 0.1 μm to be originally set. Has been.

  FIG. 9 is a diagram showing a configuration example of the comparison information file 14 stored in the storage device 4 of FIG. The second to fifth lines of the comparison information in FIG. 9 show a list of patterns laid out in the test pattern, and the eighth to tenth lines of the comparison information are set in the DRC rule file 12. A list of constraints is shown.

  Further, the comparison process in step S21 of FIG. 4 will be described in detail.

  In the comparison process, a stricter comparison process than that of a normal DRC verification process is performed. In normal DRC verification processing, it is checked whether the layout to be verified satisfies the conditions described in the design rule, that is, the DRC rule file. For example, taking a design rule relating to the minimum wiring width as an example, it is assumed that the set value in the DRC rule is 0.1 μm or more. On the other hand, if the layout is a wiring having a width of 0.09 μm, it is checked as a DRC error. However, if the layout is 0.12 μm, the DRC rule is satisfied and no DRC error occurs. That is, in this case, the establishment of the inequality relationship is used as a reference for comparison.

  However, in the comparison process (S21) according to the present embodiment, a value that should be originally set in the DRC rule is extracted from the test pattern, and an equal sign relationship between the value and the value actually set in the DRC rule The establishment of sex is used as a reference for comparison (whether they match or do not match). In this regard, taking the above-described minimum wiring width as an example, it is assumed that the set value in the DRC rule is erroneously 0.09 μm even though the constraint in the design rule is 0.1 μm or more. When the test pattern wiring width is 0.1 μm, the relationship 0.09 μm <0.1 μm is established, but in order to detect the wrong setting value 0.09 μm in the DRC rule, It is necessary to confirm sex.

  Next, the dimensions of the test pattern layout which is input data in the comparison process (S21) will be described. The embodiment according to the present invention is a process for checking whether information (for example, a restriction on the wiring width) regarding the design rule extracted from the test pattern is correctly set in the DRC rule. For this reason, the test pattern must match the upper limit value and lower limit value specified by the design rule. This will be explained by the design rule regarding the wiring width. In general, there are design rules that define the maximum and minimum values for the wiring width, and two conditions corresponding to the DRC rules are set. It is assumed that the wiring width design rule is 0.1 μm or more and 10 μm or less. At this time, the test pattern for verifying the setting value of the DRC rule in which these two conditions are described is a test pattern written with a wiring width of 0.1 μm and a test pattern written with a wiring width of 10 μm. Prepare the type. Thus, by preparing a test pattern that matches the upper limit value and lower limit value of the design rule, the DRC rule file is verified in accordance with the design rule in the comparison process (S21).

  Next, the DRC rule file subroutine correction process (S13; S21 to S24) of FIG. 4 will be described in detail. If there is a difference in the difference presence / absence determination process (S22), for example, comparison information shown as an example in FIG. 7 is obtained. FIG. 7 shows a case where the DRC rule set value is 0.11 μm while the minimum width of the first metal in the test pattern is 0.1 μm. That is, the set value of the DRC rule is deviated from the original value of 0.1 μm. In order to correct this part, the process proceeds to the DRC rule comparison / correction process (S24) based on the comparison information, and the DRC rule comparison / correction processing unit 10 corrects the set value of the corresponding DRC rule. Specific examples of this correction processing are shown in FIGS. 8A to 8C.

  FIG. 8A is a constraint on the minimum width of the first metal in the DRC rule before correction, and the value is set to 0.11 μm. FIG. 8B shows comparison information. From this, it can be seen that there is a difference between the value (0.1 μm) in the test pattern and the set value (0.11 μm) in the DRC rule. FIG. 8C is a post-correction DRC rule generated by the DRC rule file correction process (S24). Based on the comparison information of FIG. 8B, the set value (0.11 μm) of FIG. It is corrected to 1 μm.

  Further, a description of the comparison information in the comparison information file 14 will be added. In the description of the comparison process (S21) so far, the case where the test pattern and the number of constraint conditions set in the DRC rule correspond one-to-one has been described. In contrast, when this correspondence is not achieved, that is, when there is a test pattern but there is no constraint condition of the corresponding DRC rule, a constraint condition is set in the DRC rule but there is no corresponding test pattern. The case comparison information will be described. In this case, information indicating that there is no constraint condition of the corresponding DRC rule or no corresponding test pattern is output to the comparison information.

  In FIG. 9 showing a specific example of the comparison information, the second to fifth lines in FIG. 9 show a list of patterns laid out as test patterns. Here, it can be seen that the test patterns are related to the minimum wiring width of each of the first, second, third, and fourth metals. Further, the 8th to 10th lines in FIG. 9 show a list of constraint conditions set by the DRC rule. Here, it is a constraint on the minimum wiring width of each of the first, second, and fourth metals. In this case, it can be seen that the constraint on the minimum wiring width of the third metal is not set in the DRC rule. That is, the comprehensiveness of the constraint conditions of the test pattern and the DRC rule can be confirmed from the comparison information obtained by the comparison process (S21).

  In the above embodiment, the information is information on the mismatch between the minimum wiring width of the layout verification test pattern and the minimum wiring width defined by the layout verification design rule. The present invention is not limited to this, and the comparison information may be information on a mismatch between the number of layout verification test patterns and the number of design rules defined by the layout verification design rules. Further, the comparison information may be information on a mismatch between the wiring width or wiring interval of the layout verification test pattern and the wiring width or wiring interval defined by the layout verification design rule.

  Next, the operation of the LVS rule comparison / correction processing unit 50 of FIG. 1 will be described with reference to the flowchart of FIG.

  FIG. 10 is a flowchart showing LVS rule comparison / correction processing (S3, S7) executed by the LVS rule comparison / correction processing unit 50 of the information processing apparatus 1 of FIG. FIG. 11 is a flowchart showing an LVS rule correction subroutine process (S33) which is a subroutine of FIG. The LVS rule comparison / correction process of FIG. 10 and the LVS rule correction subroutine process of FIG. 11 are provided in the form of a program executed by the LVS rule comparison / correction processing unit 50 of the information processing apparatus 1 of FIG. The device layout pattern and the LVS rule are stored in advance in the device layout pattern file 51 and the LVS rule file 52 in the storage device 4, respectively. Here, the device layout pattern in the device layout pattern file 51 stores a pattern laid out exactly so as to match the value specified by the LVS rule. By inputting these pieces of information to the LVS rule comparison / correction processing unit 50, if there is an error in the LVS rule file 52, a corrected LVS rule file 53 in which the location has been corrected is generated and output.

  In step S31 of FIG. 10, the device layout pattern is read from the device layout pattern file 51 in the storage device 4, and the LVS rule is read from the LVS rule file 52 in the storage device 4 in step S32. Next, in step S33, the LVS rule is corrected based on the device layout pattern, and the corrected LVS rule is generated. Further, in step S34, the corrected LVS rule in the storage device 4 is written in the corrected LVS rule file 53 and displayed on the display device 5, and the LVS rule comparison / correction process is terminated. Return to the main routine.

  In step S41 of FIG. 11, the value set in the device layout pattern is compared with the value specified in the LVS rule. The value set in the device layout pattern is the layer configuration of each device such as transistor diffusion layer, polysilicon, N + implant, P + implant, contact, resistor element, capacitor element, etc. Including. The value defined by the LVS rule is, for example, a device definition including a device name in the device layout pattern and information on a layer configuration corresponding to the device name, and the LVS rule is expressed by a logical expression. In step S42, based on the comparison result, it is determined whether there is a difference (difference including a difference or mismatch between the device layout pattern and the LVS rule). In step S42, based on the comparison result, it is determined whether there is a difference (difference including a difference or mismatch between the device layout pattern and the LVS rule). If YES in step S42, the process proceeds to step S43. If NO, the process returns to the original main routine. In step S43, a comparison information file including comparison information is generated based on the comparison result and written to the comparison information file 54 in the storage device 4. Next, in step S44, the LVS rule is corrected based on the comparison information in the comparison information file 54, and then the process returns to the original main routine.

  FIG. 12 is a plan view showing a configuration example of the device layout pattern stored in the device layout pattern file 51 of the storage device 4 of FIG. In FIG. 12, DIFF, PO, NIMP, PIMP, and CONT are basic layers of a transistor diffusion layer, polysilicon, N + implant, P + implant, and contact, respectively. A MOS field effect transistor (hereinafter referred to as a MOS transistor) having a device name “N_MOS_A” is set as a region where the diffusion layer DIFF, the N + implant NIMP, and the polysilicon PO overlap. Further, it is assumed that this device layout pattern is drawn with the minimum necessary layers for configuring the corresponding device. Before executing the LVS rule comparison / correction process, a device layout pattern file 51 including layer configuration information corresponding to a device name written in text in the device layout pattern is stored in the storage device 4 when the device layout pattern is input. .

  FIG. 13 is a diagram showing a specific example of the LVS rule file 52 stored in the storage device 4 of FIG. That is, FIG. 13 shows an example of the device definition in the LVS rule. In general, the LVS rule needs to be described according to the input format corresponding to the LVS tool to be used. However, in essence, regarding the device definition, a layer configuration corresponding to each device is set by a logical expression, and this is related to the device type and the device name. In the first to fourth lines of FIG. 13, the LVS rule is set as follows.

(1) The base layer INT_X including the diffusion layer DIFF and the N + implant NIMP in the form of a logical product is set.
(2) An intermediate layer INT_Y including the basic layer INT_X and the polysilicon PO in the form of a logical product is set.
(3) A MOS transistor device STR_A is defined from the intermediate layer INT_Y.
(4) The device STR_A is set as a layer configuration of the device name “N_MOS_A”.

  Here, “DEFINE_DEVICE” on the fourth line in FIG. 13 means an LVS rule command for device definition, NMOS indicates a device type, and in this example indicates an N-type MOS transistor. In this example, the layer “STR_A” corresponding to the device name “N_MOS_A” is a logical product of the diffusion layer DIFF, the N + implant NIMP, and the polysilicon PO. Before executing the LVS rule comparison / correction process, the LVS rule file 52 including the device name and layer configuration information is stored in the storage device 4 when the LVS rule is input.

  In the LVS rule comparison and correction process, the layer configuration of each device obtained from the device layout pattern in the device layout pattern file 51 is compared with the layer configuration obtained from the device definition of the LVS rule in the LVS rule file 52. In the example of FIGS. 12 and 13, the overlap of the diffusion layer DIFF, the N + implant NIMP, and the polysilicon PO, which are layer configurations obtained from the device layout pattern, matches the following layer configuration. The layer configuration is a layer configuration including a logical product of a diffusion layer DIFF, an N + implant NIMP, and polysilicon PO obtained from the device definition of the LVS rule. In this case, the LVS rule comparison / correction processing unit 50 outputs “no difference” as the comparison result.

  Next, in the LVS rule comparison / correction process, a case where the comparison result is “with difference” will be described below with reference to FIGS. 14A and 14B. 14A and 14B are diagrams showing specific examples of the LVS rule file 52 stored in the storage device 4 of FIG.

  Here, FIG. 14A shows an example when the device definition in the LVS rule is incorrect. Comparing the LVS rule of FIG. 14A with the device definition of the LVS rule of FIG. 13, it can be seen that the logical product related to the polysilicon PO of the intermediate layer INT_Y is missing in the second row of FIG. 14A. That is, the device “N_MOS_A” is defined in the layer “STR_A” having no polysilicon PO layer. In this case, the LVS rule in FIG. 14A does not match the logical product of the diffusion layer DIFF, the N + implant NIMP, and the polysilicon PO, which is the layer configuration obtained from the device layout pattern. Accordingly, the LVS rule comparison / correction processing unit 50 outputs “with difference” as the comparison result.

  In the LVS rule comparison / correction process, another case in which “there is a difference” as a comparison result will be described below. FIG. 14B shows an example when the device definition in the LVS rule is incorrect. Compared with the device definition of the LVS rule in FIG. 13, in the third line of FIG. 14B, it can be seen that P + implant PIMP is logically ANDed with respect to the intermediate layer INT_Y as the definition of the device “STR_A”. That is, the device “N_MOS_A” is defined in the layer “STR_A” where the N + implant NIMP and the P + implant PIMP overlap. In this case, the layer “STR_A” does not coincide with the logical product of the diffusion layer DIFF, the N + implant NIMP, and the polysilicon PO, which is a layer configuration obtained from the device layout pattern. Therefore, the LVS rule comparison / correction processing unit 50 outputs “with difference” as the comparison result.

  FIG. 15 is a diagram showing a specific example of the comparison process (S41) executed by the information processing apparatus 1 of FIG. FIG. 15 shows a specific example of the comparison information file 54 of FIG.

  In FIG. 15, a device layout pattern file 51 stores layout patterns of four types of devices corresponding to device names “N_MOS_A”, “N_MOS_B”, “N_MOS_C”, and “N_MOS_D”. On the other hand, in the LVS rule file 52, device definitions corresponding to these four types of devices are written. The LVS rule comparison / correction processing unit 50 compares the layer configurations of the respective devices set by these two data, and outputs the result as a comparison information file 54. In this example, the device configurations “N_MOS_A” and “N_MOS_B” match the layer configuration and “MATCHED” is output, but the device names “N_MOS_C” and “N_MOS_D” do not match the layer configuration There is a result. The content of the mismatch is that, for the device name “N_MOS_C”, the layer of polysilicon PO is not defined in the corresponding LVS rule. Further, regarding the device name “N_MOS_D”, the layer of P + implant PIMP is excessively defined in the LVS rule and output as comparison information. From this comparison information, the developer of the LVS rule can easily grasp which device layer configuration of the LVS rule has an error.

  Further, the comparison process (S41) for the device layout pattern when “logical negation” is included in the device definition layer configuration will be described below.

  FIG. 16 is a diagram showing a specific example of the LVS rule file 52 stored in the storage device 4 of FIG. Here, FIG. 16 is an example in which “logic negation” is included in the layer configuration in the device definition of the LVS rule. When comparing the device definition of FIG. 16 with the device definition of FIG. 13, it can be seen that “not LAY_A” is added as a logical expression for the layer “STR_A” in the third row of FIG. That is, the layer “INT_Y” that does not overlap with the layer “LAY_A” has the layer configuration of the device name “N_MOS_A”. In the case of such a device definition, the device layout pattern shown in FIG. 12 alone is not sufficient, and the LVS rule file 52 cannot be verified by the comparison process (S41). This is because the device layout pattern shown in FIG. 12 does not specify the layer “LAY_A”. A configuration example of a device layout pattern in the case of a device having such a device definition is shown in FIGS. 17A and 17B.

  17A and 17B are plan views showing specific examples of device layout patterns stored in the device layout pattern file 51 of the storage device 4 of FIG. Here, FIG. 17A shows a device layout pattern of the same device name “N_MOS_A” as FIG. 12, and the minimum layer components necessary for device recognition, that is, diffusion layer DIFF, N + implant NIMP, and polysilicon PO Is drawn. FIG. 17B shows the layer “LAY_A” superimposed on FIG. 17A. In the comparison process (S41), both the device layout patterns are read, and it is checked whether the difference layer is included in the device definition of the LVS rule as a logical negation. This check process will be described below using a specific example.

  When reading the data of the device layout pattern file 51, it is read from FIG. 17A drawn with the minimum necessary layers constituting the device “N_MOS_A” that the layer structure is an overlap of the diffusion layer DIFF, the N + implant NIMP, and the polysilicon PO. . Next, the layer configuration of the device layout pattern written as “NOT” (logical negation command) and text in FIG. 17B, that is, the diffusion layer DIFF, N + implant NIMP, P + implant PO, and layer “LAY_A” are read. Hereinafter, as shown in FIG. 17B, the device layout pattern written as “NOT” is referred to as “NOT device layout pattern”.

  Next, when the difference between the layer configuration of FIG. 17A and the layer configuration of FIG. 17B is taken, the difference result is layer “LAY_A”, and the logical negation, that is, the process of “not LAY_A” is Check if it is included in the definition. In the example of FIG. 16, FIG. 17A and FIG. 17B, the layer “LAY_A” obtained from the device layout pattern of FIG. 17A and FIG. 17B is certainly the logic in the third line of the device definition of the LVS rule of FIG. It is defined as negation “not LAY_A”. In this case, the LVS rule comparison / correction processing unit 50 outputs “no difference” as the comparison result. In this example, the logical negation layer is only “LAY_A”, but there may be a plurality of layers. In that case, a plurality of device layout patterns in which the respective logical negation layers are superimposed are prepared as “NOT device layout patterns”. Alternatively, one device layout pattern in which all related logical negation layers are superimposed may be prepared as a “NOT device layout pattern”.

Furthermore, the LVS rule correction process (S44) by the LVS rule comparison / correction processing unit 50 will be described using a specific example. When there is a difference in the difference presence / absence determination process (S42), comparison information including difference information as shown as an example in FIG. 15 is obtained. As described above, this comparison information includes the following two cases.
(1) The device definition of the device name “N_MOS_C” is “unmatched” because the polysilicon PO layer is undefined.
(2) A case where the device definition of the device name “N_MOS_D” is inconsistent because P + implant PIMP is excessively defined.

  In the LVS rule correction process (S44), the device definition of the LVS rule file 52 is corrected based on this comparison information. Specific examples of the correction contents will be described with reference to FIGS. 18A, 18B, and 19. FIG.

  18A is a diagram showing a specific example of the LVS rule file 52 before correction stored in the storage device 4 of FIG. FIG. 18B is a diagram showing a specific example of the modified LVS rule file 53 stored in the storage device 4 of FIG. Here, FIG. 18A shows the LVS rule file 52 before correction relating to the device “N_MOS_C”, and the layer “STR_C” which is the layer configuration of the device name “N_MOS_C” does not include the layer of polysilicon PO. In the LVS rule correction process (S44), a process of adding the logical product of the polysilicon PO layers as shown in FIG. 18B from the comparison information in which the polysilicon PO layer is undefined in the device definition of the device name “N_MOS_C”. This is performed for the LVS rule file 52. Then, the corrected LVS rule file 53 including the corrected LVS rule is output.

  FIG. 19A is a diagram showing a specific example of the LVS rule file 52 before correction stored in the storage device 4 of FIG. FIG. 19B is a diagram showing a specific example of the modified LVS rule file 53 stored in the storage device 4 of FIG. Here, FIG. 19A is an LVS rule file 52 before correction relating to the device “N_MOS_D”, and an extra layer “STR_D” P + implant PIMP which is a layer configuration of the device name “N_MOS_D” is included. In the LVS rule correction process, the process of removing the logical product of the layers of the P + implant PIMP as shown in FIG. 19B from the comparison information that the layer PIMP is excessively defined in the device definition of the device name “N_MOS_D” is performed in the LVS rule file. 52. Then, the corrected LVS rule file 53 including the corrected LVS rule is output.

  In the above embodiment, the difference, which is the comparison result, is obtained by comparing the layout verification pattern used when verifying the layout verification rule used when verifying the layout of the semiconductor integrated circuit with the layout verification rule. The comparison process which produces | generates the comparison information containing is provided. The information processing apparatus 1 further includes a correction process for correcting the layout verification rule based on the comparison information when the difference exists. The present invention is not limited to this, and the information processing apparatus 1 may be configured to include only the comparison process.

  As described above, according to the information processing apparatus 1 according to the present embodiment, in the verification process of the layout verification DRC rule or the LVS rule, it is possible to reduce the number of correction processes compared to the conventional technique, and to correct the rule. Efficiency can be increased.

  In the LVS rule verification process, the LVS rule is defined using a logical expression including a logical product and a logical negation or a logical product. This makes it possible to compare and modify LVS rules expressed using the logical expressions.

Modification 1
FIG. 20 is a diagram illustrating a specific example of the comparison process (S41A) according to the first modification executed by the information processing apparatus 1 in FIG. In the above embodiment, the case where the number of the device layout pattern file 51 and the number of the LVS rule files 52A correspond one-to-one has been described. A comparison process when the correspondence is not achieved will be described below. In other words, the number of device definitions in the LVS rule file 52A is greater than or equal to the number of patterns set in the device layout pattern. At this time, in the comparison step (S41A), information on excess / deficiency of the device definition of the corresponding LVS rule file is output. This will be described below with reference to FIG.

  The comparison information file 54A of FIG. 20 shows a specific example when the device definition that should originally be set is not made in the LVS rule file 52A. Here, in the LVS rule file 52A, there is no device definition setting corresponding to “N_MOS_D” set in the device layout pattern file 51. At this time, this difference is detected in the comparison process S51A, and the result is output as a comparison information file 54A. In this example, the device names “N_MOS_A, N_MOS_B and N_MOS_C” have the same layer configuration and are output “MATCHED”. However, the device name “N_MOS_D” indicates that there is no corresponding device definition (N_MOS_D: NOT DEFINED, STR_D). The developer of the LVS rule can easily grasp from the comparison information file 54A that the device definition is missing in the LVS rule file 52A. The device name “STR_D” in the comparison information file 54A is a configuration layer corresponding to the device name “N_MOS_D” extracted from the device layout pattern file 51, and is generally described by a logical expression. Information to be used.

  FIG. 21 is a diagram showing a specific example of the modified LVS rule file 53A modified by the modification processing after the comparison processing (S41A) of FIG.

  In the correction process after the comparison process (S41A) in FIG. 20, the LVS rule file 52A is corrected using the comparison information file 54A. Specifically, the comparison information file 54A shows the device name of the unset device and its configuration layer. For example, a description of “DEFINE_DEVICE NMOS N_MOS_D STR_D” is added as a device definition statement to the LVS rule file 52A. That is, even if there is a missing device definition in the LVS rule file 52A, the modified LVS rule file 53A of FIG. 21 corresponding to the device layout pattern file 51 on a one-to-one basis can be obtained through this modification process.

Modification 2
FIG. 22 is a diagram illustrating a specific example of the comparison process (S41B) according to the second modification executed by the information processing apparatus 1 in FIG. The comparison information file 54B of FIG. 22 shows a specific example in the case where a device definition that originally does not need to be set is defined in the LVS rule file 52B.

  In the LVS rule file 52B of FIG. 22, a device definition corresponding to the device name “N_MOS_E” not set in the device layout pattern file 51 is set. In the comparison process (S41B), this difference is detected, and the result is output to the comparison information file 54B. In this example, the device names “N_MOS_A”, “N_MOS_B”, “N_MOS_C”, and “N_MOS_D” have the same layer configuration, and “MATCHED” is output. However, in the device name “N_MOS_E”, an excessive device definition (N_MOS_E: OVER DEFINED) is output. From this comparison information file 54B, the LVS rule developer can easily grasp that there is an extra device definition in the LVS rule file 52B.

  FIG. 23 is a diagram showing a specific example of the modified LVS rule file 53B modified by the modification process after the comparison process (S41B) of FIG.

  In the correction process after the comparison process (S41B) in FIG. 22, the LVS rule file 52B is corrected using the comparison information file 54B. Specifically, the device name of the over-set device is shown in the comparison information file 54B, and the corresponding device definition description is deleted from the LVS rule file 52B. Specifically, “DEFINE_DEVICE NMOS N_MOS_E STR_E” is deleted from the LVS rule file 52B. That is, even if there is a device definition that is not originally required in the LVS rule file 52B, the modified LVS rule file 53B of FIG. 23 corresponding to the device layout pattern file 51 on a one-to-one basis can be obtained through this modification process. it can.

1 Information processing device,
2 ... Keyboard,
3 ... mouse,
4 ... Storage device,
10 ... DRC rule comparison and correction processing unit,
11 ... Test pattern file,
12 ... DRC rule file,
13 ... The modified DRC rule file,
14 ... Comparison information file,
50 ... LVS rule comparison and correction processing unit,
51 ... Device layout pattern file,
52, 52A, 52B ... LVS rule file,
53, 53A, 53B ... LVS rule file after modification,
54, 54A, 54B: Comparison information file.

JP 2011-060194 A Japanese Patent Laid-Open No. 10-063699

Claims (12)

In an information processing apparatus for verifying a layout verification rule used when verifying a layout of a semiconductor integrated circuit,
Comparing means for comparing a layout verification pattern used when verifying the layout verification rule with the layout verification rule, and generating comparison information including a difference as a comparison result. Information processing device.   The information processing apparatus according to claim 1, further comprising a correcting unit that corrects the layout verification rule based on the comparison information when the difference exists.   The information processing apparatus according to claim 2, wherein the correction unit adds an insufficient device definition when the difference is an insufficient device definition.   The information processing apparatus according to claim 2, wherein the correction unit deletes an excessive device definition when the difference is an excess of a device definition. The layout verification rule is at least one of a layout verification design rule and a layout verification device layout rule.
When the layout verification rule is a layout verification design rule, the layout verification pattern is a layout verification test pattern,
3. The information processing apparatus according to claim 1, wherein when the layout verification rule is a layout verification device layout rule, the layout verification pattern is a layout verification device layout pattern.   6. The information processing apparatus according to claim 5, wherein the comparison information is information on a mismatch between the number of layout verification test patterns and the number of design rules defined by the layout verification design rules.   6. The information processing apparatus according to claim 5, wherein the comparison information is information on a mismatch between a wiring width of the layout verification test pattern and a wiring width defined by the layout verification design rule.   6. The information processing apparatus according to claim 5, wherein the comparison information is information on a mismatch between a wiring interval of the layout verification test pattern and a wiring interval defined by the layout verification design rule.   6. The information processing apparatus according to claim 5, wherein the device of the layout verification device layout rule is defined using a logical expression including a logical product and a logical negation.   6. The information processing apparatus according to claim 5, wherein the device of the layout verification device layout rule is defined using a logical expression including a logical product. In an information processing method executed by an information processing apparatus including a processing unit for verifying a layout verification rule used when verifying a layout of a semiconductor integrated circuit,
The processing means includes a step of comparing a layout verification pattern used when verifying the layout verification rule with the layout verification rule, and generating comparison information including a difference as a comparison result. A characteristic information processing method. In a program executed by an information processing apparatus having a processing means for verifying a layout verification rule used when verifying a layout of a semiconductor integrated circuit,
The processing means includes a step of comparing a layout verification pattern used when verifying the layout verification rule with the layout verification rule, and generating comparison information including a difference as a comparison result. A featured program.

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