JP5663380B2 - Layout verification apparatus and layout verification method - Google Patents

Description

  The present invention relates to a layout verification apparatus and layout verification method for performing layout verification on a mask pattern used for manufacturing a semiconductor integrated circuit.

  The layout verification is to perform layout verification as to whether a manufactured mask pattern may cause a defect in a semiconductor manufacturing process or a defect in product specifications. Specifically, the layout refers to the shape, width, gap, etc. of the pattern drawn on the mask pattern.

  In the semiconductor manufacturing technology, layout verification is performed by determining whether a prescribed rule is violated based on a predetermined rule file. However, in such a layout verification, there is a problem that a pseudo error is generated without any problem even if it is not an error. In view of this, various means are provided for passing a pseudo error without an error and extracting only a true error (for example, Patent Document 1).

  In addition, a technology for specifying a pseudo-error occurrence area to extract a pseudo-error occurrence area from the entire layout, and for this area only, layout verification is performed using a loose rule different from other areas. Has also been proposed (see, for example, Patent Document 2).

Japanese Patent Laid-Open No. 8-101859 JP 2000-99558 A

  However, as described above, there are various types of layout patterns even if a means for extracting a true error is taken even if a pseudo error is passed. Therefore, although solutions corresponding to individual patterns have been taken, it is difficult to construct general-purpose solutions.

  In addition, according to the technique for performing layout verification with a gradual rule for the above-described pseudo error occurrence region, it is necessary to perform verification twice in combination with verification based on such a rule and verification based on a normal rule. The verification process becomes redundant.

  In addition, it is possible to perform layout verification using normal rules once, create error data containing pseudo errors, and specify parameters for the pseudo error area on the design system. Therefore, there are many problems such as inducing the occurrence of mistakes and complicated operations.

  An object of the present invention is to provide a layout verification technique that is highly versatile and capable of performing verification processing efficiently in view of the problems of the prior art.

  In order to achieve this object, a layout verification apparatus according to the present invention is a layout verification apparatus that verifies whether layout data violates a design rule, and has a second design rule different from a normal first design rule. Based on a design value prepared for specifying a pseudo error area to be applied, data classification means for classifying layout data into layout data in the pseudo error area and layout data outside the pseudo error area; and Rule creating means for creating the second design rule as being within the allowable range based on the allowable range from the first design rule determined for specifying the second design rule; It is verified whether layout data violates the first design rule, and a layout in the pseudo error area is verified. Data is characterized by comprising a verification means for verifying whether contrary to the second design rule.

  According to this, the pseudo error area is automatically specified based on the design value, the layout data is divided into those in the pseudo error area and those in the other areas, and the layout data in each area is respectively determined. Since different design rules are applied to verify the existence of rule violations, it is necessary to repeat the verification by the gradual design rule for the pseudo error area and the verification by the normal design rule as before. Since there is not, verification can be performed efficiently.

  In addition, since different design rules are applied to the pseudo error area and other areas, it is possible to eliminate the pseudo error generated by applying the normal first design rule to the layout data in the pseudo error area. it can. Further, since different second design rules can be created and different pseudo error areas can be extracted according to the design values, it is possible to cope with verification of various layout data.

  In the present invention, the design value prepared for specifying the pseudo error area may be for specifying an area including layout data related to the arc-shaped layout pattern as a pseudo error area. According to this, for the layout data of the guard ring portion in the high breakdown voltage device such as the insulated gate bipolar transistor, the arc portions at the four corners can be specified as the pseudo error region and verified.

  Further, in the present invention, the design value is obtained by setting each area including layout data relating to each layout pattern of the arc shape having the first radius and the arc shape having the second radius as the first and second pseudo error areas, respectively. First and second design values for specifying, the data sorting means, based on the first and second design values, layout data, layout data in the first pseudo error region, and the first The layout data is divided into layout data in two pseudo error areas and layout data other than the first and second pseudo error areas, and the allowable range for the first design rule is the first and second design values. And the rule creating means sets the second design rule as the second design rule based on the first and second tolerance ranges. A design rule for the first pseudo error area and a design rule for the second pseudo error area are created respectively, and the verification unit performs the verification on the layout data in the pseudo error area as the first Verification is performed by applying the design rule for the first pseudo error area to the layout data in the pseudo error area, and verification is performed by applying the design rule for the second pseudo error area to the layout data in the second pseudo error area. It may be what performs.

  According to this, since the pseudo error area for each of the layout data related to the different layout patterns is extracted and the rule check is performed with different design rules for each pseudo error area, each pseudo error area of each layout pattern is Even when different design rules are applied, the verification can be performed efficiently without overlapping the areas to be verified. In addition, since the pseudo error area can be classified without looking at the result of the layout verification using the normal rule once, the verification can be performed more efficiently.

The layout verification method of the present invention is a layout verification method for verifying whether layout data violates a design rule by a layout verification device, and a second design rule different from a normal first design rule is applied. A data partitioning step of partitioning layout data into layout data within the pseudo error area and layout data outside the pseudo error area based on a design value prepared for specifying the pseudo error area; and the second design A rule creation step for creating the second design rule as being within the allowable range based on the allowable range from the first design rule determined to specify the rule, and layout data outside the pseudo error area It is verified whether or not the first design rule is violated, and the layer in the pseudo error area is checked. Todeta is characterized by comprising a verification step of verifying whether contrary to the second design rule.

  According to this, as in the case of the layout verification apparatus of the present invention, verification can be performed efficiently, pseudo errors can be eliminated, and verification of various layout data can be handled.

  In the layout verification method of the present invention, the design value prepared for specifying the pseudo error area is for specifying the area including the layout data related to the arc-shaped layout pattern as the pseudo error area. Also good. According to this, as in the case of the layout verification apparatus of the present invention, the arc data at the four corners can be specified as the pseudo error area and verified for the layout data of the guard ring portion in the high breakdown voltage device.

  In the layout verification method according to the present invention, the design values may include first and second regions each including layout data relating to each layout pattern having an arc shape having a first radius and an arc shape having a second radius. 1st and 2nd design information for specifying as a pseudo error area, and in the data classification step, layout data is laid out in the first pseudo error area based on the first and second design information. Data, layout data in the second pseudo error area, and layout data other than the first and second pseudo error areas, and an allowable range for the first design rule is the first and second tolerances. First and second tolerance ranges respectively corresponding to design values, and in the rule creation step, the second design is based on the first and second tolerance ranges. As the rules, a design rule for the first pseudo error area and a design rule for the second pseudo error area are created, respectively, and in the verification step, the first pseudo error area is verified by verifying the layout data in the pseudo error area. The layout data in the error area is verified by applying the design rule for the first pseudo error area, and the layout data in the second pseudo error area is verified by applying the design rule for the second pseudo error area. You may do it.

  According to this, as in the case of the layout verification apparatus of the present invention, even when different design rules are applied to each pseudo error area of each layout pattern, the verification target areas are not overlapped. Verification can be performed efficiently. Further, the areas are automatically divided for each area to be verified, and the design rule corresponding to each area is applied, so that the verification can be performed more efficiently.

It is a block diagram which shows the structure of the layout verification apparatus which concerns on one Embodiment of this invention. It is a figure which shows a mode that layout data is divided in the apparatus of FIG. It is a flowchart which shows the layout verification process using the apparatus of FIG. It is a figure which shows a part of layout pattern which concerns on the layout data about the guard ring part of the high voltage | pressure-resistant device used as the object of the rule check by the apparatus of FIG. It is a figure which shows another example of a mode that layout data is divided in the apparatus of FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a layout verification apparatus according to an embodiment of the present invention. This layout verification apparatus is incorporated as a design rule check tool (hereinafter referred to as “DRC tool”) 10 in a CAD system.

  The DRC tool 10 verifies whether or not the layout data 1 designed by CAD violates the design rule, and outputs verification result data 2 indicating the result. Then, the user corrects the layout data 1 as necessary based on the verification result data 2 and activates the DRC tool 10 again to finally obtain the layout data 3 verified to be free from violations. be able to.

  In the present embodiment, layout data of a guard ring portion in a high voltage device such as an IGBT (Insulated Gate Bipolar Transistor) is used as the layout data 1 and is to be verified. The design rule defines the dimensions of elements and wiring in the design of an integrated circuit. In the case of guard ring layout data, the design rule defines the width and interval of the guard ring.

  In the layout data 1, a portion where the guard ring width cannot be accurately represented because the coordinates below a predetermined grid interval cannot be input in the CAD system to be used, such as a corner portion provided with a curvature in the guard ring. There are also data. Among such layout data, if normal design rules are applied, the rules are violated and the result of verification is determined to be an error, but the layout data is acceptable without being an error. That is, there is also layout data that becomes a pseudo error.

  Therefore, in the DRC tool 10, an area where such layout data that can generate a pseudo error exists is set as a pseudo error area, and the layout data in the pseudo error area is more gradual than a normal design rule. Is applied so that data indicating a pseudo error is not included in the verification result data 2.

  As shown in FIG. 1, the DRC tool 10 generates a design rule file 11 corresponding to a pseudo error based on the design rule file 4 and the definition file 5 of the pseudo error area and the area limitation rule. An extraction unit 12 is provided. The design rule file 4 stores normal design rules applied to layout verification of the layout data 1. The pseudo error area rule extraction unit 12 constitutes a rule creation means in the present invention.

  In the definition file 5, design values such as the chip size of the circuit chip and the radius of the curved part of the guard ring related to the layout data 1 are recorded as information defining the pseudo error area. In addition, an allowable range from a normal design rule is recorded as information defining a limited design rule that is applied only to the pseudo error area related to the layout data 1. A limited design rule can be obtained by changing a normal design rule within the allowable range.

  Selection of design values and allowable ranges recorded in these definition files 5 is performed by the user in correspondence with the layout data 1 to be subjected to layout verification. The design value can be recorded in the definition file 5 based on the contents of the design specification file 6 in which the design specifications are stored. The allowable range can be recorded based on the contents of the process specification file 7 in which the process specifications are recorded.

  The pseudo error area rule extraction unit 12 creates a pseudo error handling design rule file 11 by adding a pseudo error area rule 13 and a pseudo error area extraction rule 14 to the design rule file 4. The rule 13 for the pseudo error area is a modified design rule applied to the pseudo error area and the rule for the application area of the design rule modified so as to exclude the pseudo error area from the layout verification based on the design rule file 4. Including.

  The pseudo error area extraction rule 14 is a rule for specifying a pseudo error area based on the design value recorded in the definition file 5. That is, by applying this rule to the chip size recorded as the design value in the definition file 5 and the radius of the curved portion of the guard ring, as a pseudo error area in the layout data of the guard ring, A region including curved portions at the four corners is specified.

  The DRC tool 10 also includes a pseudo error area extraction unit 16 that generates pseudo error area additional layout data 15 based on the pseudo error area extraction rule 14 and the layout data 1. The pseudo error area additional layout data 15 is obtained by dividing the layout data 1 into pseudo error area data 17 which is layout data in the pseudo error area and layout data other than the pseudo error area. The pseudo error area rule extraction unit 12 and the pseudo error area extraction unit 16 constitute data classification means in the present invention.

  The pseudo error area extraction unit 16 specifies the pseudo error area by applying the design value of the definition file 5 to the pseudo error area extraction rule 14. Then, the layout data 1 is divided into pseudo error area data 17 and layout data other than the pseudo error area, and pseudo error area additional layout data 15 is generated. As a result, the layout data other than the pseudo error area and the layout data in the pseudo error area can be distinguished and processed.

  Further, the DRC tool 10 verifies whether the layout data in the pseudo error area added layout data 15 violates the design rule in the pseudo error handling design rule file 11 (hereinafter referred to as “rule check”). A design rule check unit 18 is provided. The design rule check unit 18 constitutes verification means in the present invention.

  The design rule check unit 18 performs a rule check on the pseudo error area data 17 in the pseudo error area additional layout data 15 using the pseudo error area rule 13, and for layout data other than the pseudo error area data 17, A rule check is performed based on normal design rules other than the pseudo error area rule 13 in the pseudo error handling design rule file 11.

  The user can confirm the verification result by the verification result data 2. Moreover, the layout data 3 after verification can be obtained.

  FIG. 2 shows how the layout data 1 is divided by the pseudo error area extraction unit 16. It is assumed that the layout based on the layout data 1 has the guard ring layout pattern 21 shown in FIG.

  In this case, the pseudo error area extraction unit 16 applies the chip size recorded as the design value in the definition file 5 and the radius of the curved part of the guard ring to the pseudo error area extraction rule 14, thereby generating the pseudo error area 22. Identify. As a result, the non-pseudo error area 23 other than the pseudo error area 22 is also specified.

  The guard ring is designed to have a partial circular shape with a radius R because the pressure resistance deteriorates when the four corners are formed in a square shape. In other words, there are always areas where there are partial circular portions that can be calculated from the radius R at the four corners of the guard ring. If the radius R is specified from the design specifications, the areas can be extracted as pseudo error areas. By applying the guard ring radius R to the pseudo error region extraction rule 14, the pseudo error region is extracted.

  Then, based on the specified pseudo error area 22, the pseudo error area extraction unit 16 converts the layout data 1 into pseudo error area data 17 corresponding to the pattern portion 24 in the pseudo error area 22 shown in FIG. This is divided into layout data of the pattern portion 25 in the non-pseudo error area 23 shown in FIG.

  The design rule check unit 18 performs a rule check on the pseudo error area data 17 corresponding to the pattern part 24 using the pseudo error area rule 13, and the layout data of the pattern part 25 is stored in the design rule file 11 corresponding to the pseudo error. A rule check can be performed based on the normal design rule.

  FIG. 3 is a flowchart showing a layout verification process using the DRC tool 10. As shown in the figure, when the process is started, first, in step 31, the user creates a pseudo error area and an area limitation rule definition file 5 based on the design specification file 6 and the process specification file 7. In step 32, layout data 1 of the highest hierarchy having layout data of all hierarchies is created. Then, the DRC tool 10 is activated.

  In response to this, first, the pseudo error area rule extracting unit 12 extracts an area specifying rule for specifying the corresponding pseudo error area based on the design value of the definition file 5 in step 33. Furthermore, based on the allowable range of the definition file 5, the design rule applied to the pseudo error area is extracted.

  In step 34, the extracted area specifying rule is added to the design rule file 4 as a pseudo error area extraction rule 14, the extracted design rule is added as a pseudo error area rule 13, and the design rule By modifying the rule for the application area so as to exclude the pseudo error area from the layout verification based on the design rule file 4, the pseudo error handling design rule file 11 is created.

  Next, in step 35, the pseudo error area extraction unit 16 extracts a pseudo error area by applying the design value of the definition file 5 to the pseudo error area extraction rule 14. Next, in step 36, the pseudo error area extraction unit 16 classifies the layout data 1 into pseudo error area data 17 and layout data other than the pseudo error area based on the extracted pseudo error area, and generates a pseudo error. The area addition layout data 15 is created.

  Next, in step 37, the design rule check unit 18 performs a rule check on the created pseudo error area added layout data 15. That is, the rule 13 for the pseudo error area is applied to the pseudo error area data 17, and the normal design rule in the design rule file 11 for pseudo error is applied to the layout data other than the pseudo error area data 17, and the rule check is performed. I do. The check result is output as verification result data 2.

  Next, in step 38, verified layout data 3 is created. Since the pseudo error area data 17 is checked by applying the rule 13 for the pseudo error area, no error corresponding to the pseudo error is recorded in the verification result data 2. That is, all errors counted in the verification result data 2 are regarded as true errors.

  Next, when it is recognized in step 39 that there is a true error based on the verification result data 2, the user returns to step 32, corrects the top layer layout data, and again executes the DRC tool 10. It can be activated and a rule check can be performed. When there is no true error in the verification result data 2, the user can acquire the layout data 3 verified as having no error.

  FIG. 4 shows a part of the layout pattern related to the layout data for the guard ring portion of the high-breakdown-voltage device that is subject to rule check. The design value of the guard ring related to this layout data is recorded in the design specification file 6, and the radius R of the curved part having a partial circular shape located at the four corners of the outermost guard ring is 10 μm wide and 20 μm wide. Is 270 μm, the radius R of the curved portion located at the four corners of the innermost guard ring is 150 μm, and the number of guard rings is five.

  In FIG. 4, one curved portion of the innermost guard ring pattern 41 having a curved portion radius R of 150 μm is indicated by a solid line. R1 is an inner radius of the curved portion, and R2 is an outer radius. If the radius R is defined as a value for the inner line of the curved portion, R1 is 150 μm and R2 is 160 μm. In FIG. 4, the outer shape of the curved portion according to the design value is indicated by a broken line 42.

  In CAD, since the points between the minimum grids that can be input cannot be expressed, the layout data is constituted by values rounded to the points on the minimum grid. Therefore, as shown in the figure, the width of the straight line portion of the pattern 41 along the vertical and horizontal lines of the grid exactly follows the design value of 10 μm, while the width of the curved portion follows the design value of 10 μm. For example, as shown in the figure, it becomes 10 μm-16 nm.

  In this case, if the design rule stipulates that all guard ring widths should be checked at 10 μm, if this is applied to check the layout data rule in the curved portion, the check result will be an error. . This error includes acceptable pseudo errors.

  Therefore, an area including the layout data of such a curved portion is set as a pseudo error area 43, and the layout data in the pseudo error area 43 is not for 10 μm according to a normal design rule, but for a pseudo error area that is gentler than that. A rule, for example, (10-0.02) μm is applied, and an error is not generated unless the width is narrower than this.

  For example, when a rule check is performed on the innermost guard ring in accordance with the guard ring design values shown in FIG. 4, the chip size value 10 mm and the innermost guard ring curve based on the design specification file 6 are used. The value 150 μm of the radius R of the part is recorded in the definition file 5. Based on the process specification file 7, ± 0.02 μm is recorded as an allowable range when performing a rule check on the width or space of the guard ring.

  The design rule file 4 is recorded with a design rule “check all guard ring widths at 10 μm” used for guard ring rule check. In addition, it is assumed that layout data created for the innermost guard ring is recorded in the layout data 1.

  In this state, when the DRC tool 10 is activated, the pseudo error area rule extraction unit 12 causes the chip size and the radius R of the curved part of the guard ring to be recorded in the definition file 5. A pseudo error region extraction rule 14 for specifying a pseudo error region where a curved portion exists from the radius R is added to the design rule file 4.

  In addition, the rule for the application area of the design rule is changed to a rule for excluding the pseudo error area from the rule check based on the design rule file 4, and according to the allowable range ± 0.02μ of the definition file 5, “the guard ring width is A rule 13 for a pseudo error area, “Check with (10−0.02) μm” is added. As a result, a pseudo-error handling design rule file 11 is generated.

  For the added pseudo error region extraction rule 14, the pseudo error region extraction unit 16 applies the chip size 10 mm of the definition file 5 and the radius of the curved portion 150 μm, and the pseudo error region 43 of FIG. Extracted about. Then, the layout data 1 of the inner ring guard ring is divided into data 17 in the pseudo error area and data other than the pseudo error area, and pseudo error area additional layout data 15 is created.

  For the pseudo error area data 17 in the generated pseudo error area additional layout data 15, the design rule check unit 18 performs a pseudo error area that “the guard ring width is checked at (10−0.02) μm”. Rule 13 is applied and a rule check is performed. For data other than the pseudo-error area data 17, a normal rule “check the guard ring width at 10 μm” is applied, and the rule check is performed.

  FIG. 5 shows another example of how the layout data 1 is divided by the pseudo error area extraction unit 16. In this case, as a design value in the definition file 5, in addition to the chip size, the value of the radius R of the curved portion in the two adjacent guard rings is recorded, and the width of each of the layout data of the two guard rings is recorded. Alternatively, an allowable range for performing the rule check regarding the space is recorded.

  In this example, the pseudo error area extraction unit 16 applies the chip size recorded as the design value in the definition file 5 and the radius R of the two types of curved parts to the pseudo error area extraction rule 14 to obtain FIG. As shown in a), pseudo error areas 53 and 54 corresponding to the patterns 51 and 52 of each guard ring are specified. As a result, non-pseudo error areas 55 other than the pseudo error areas 53 and 54 are also specified.

  Based on the specified pseudo error areas 53 and 54, the pseudo error area extracting unit 16 converts the layout data 1 into pseudo error area data corresponding to the pattern portion 56 in the pseudo error area 53 shown in FIG. 5C, the pseudo error area data corresponding to the pattern part 57 in the pseudo error area 54 shown in FIG. 5C, and the layout data of the pattern part 58 in the non-pseudo error area 55 shown in FIG. 5D. Then, pseudo error area additional layout data 15 is generated. In this case, the pseudo error area data 17 includes the pseudo error area data of the pseudo error area 53 and the pseudo error area data of the pseudo error area 54.

  In this case, the pseudo error area rule extraction unit 12 sets the pseudo error area rules for the pseudo error areas 53 and 54 in the design rule file as the pseudo error area rule 13 based on the allowable range for each guard ring. Add to Further, as the pseudo error area extraction rule 14, a rule for specifying the pseudo error areas 53 and 54 is added based on the chip size and the radius R of the two types of curved portions.

  At this time, the radius of the outer curved portion may be defined based on design specifications. That is, if the radius of the inner curved portion is Ri, the width of the curved portion is W, and the interval between the two curved portions is S, the radius Ro of the outer curved portion is obtained by Ro = Ri + W + S. Also good. In this embodiment, an example in which two types of curve portions are targeted is shown, but the present invention is not limited to this, and the number of target curve portions may be three or more.

  Further, the design rule check unit 18 performs a rule check on the pseudo error area 53 data in the pseudo error area data 17 by applying the pseudo error area rule for the pseudo error area 53 in the pseudo error area rule 13. . The data in the pseudo error area 54 is checked by applying the pseudo error area rule for the pseudo error area 54. Data other than the pseudo error area data 17 in the pseudo error area additional layout data 15 is verified by applying a normal design rule in the pseudo error corresponding design rule file 11.

  According to this embodiment, the layout data is divided into those in the pseudo error area and those in the non-pseudo error area, and the rule check is performed on the layout data in each area with different design rules. As described above, since it is not necessary to duplicately perform a rule check with a loose rule for a pseudo error area and a rule check with a normal rule, the rule check can be performed efficiently.

  In addition, the pseudo error area for each layout data related to different layout patterns is extracted, and the rule check is performed with different design rules for each pseudo error area, so different design rules for each pseudo error area of each layout pattern Even if is applied, it is possible to efficiently perform the rule check without overlapping the areas to be subject to rule check.

  In addition, since different design rules are applied to the pseudo error area and other areas, it is possible to eliminate a pseudo error generated by applying a normal design rule to the pseudo error area.

  In addition, since the areas are automatically divided for each area to be verified and the design rule corresponding to each area is applied, the verification can be performed efficiently.

  Furthermore, different pseudo error area rules 13 can be created according to design specifications and the like, and pseudo error areas can be extracted using different pseudo error area extraction rules 14. It is possible to respond while minimizing the width of the rule from the rule to the applied design rule.

  4 ... Design rule file, 5 ... Pseudo error area and area limitation rule definition file, 11 ... Pseudo error corresponding design rule file, 12 ... Pseudo error area rule extraction unit, 13 ... Pseudo error area rule, 14 ... Pseudo error area extraction Rules, 16 ... Pseudo error area extraction unit, 15 ... Pseudo error area additional layout data, 17 ... Pseudo error area data, 18 ... Design rule check unit.

Claims (6)

A layout verification device for verifying whether layout data violates design rules,
Based on the design value prepared for specifying the pseudo error area to which the second design rule different from the normal first design rule is applied, the layout data is divided into the layout data in the pseudo error area and the pseudo error area. Data classification means for classifying the data into outside layout data;
Rule creation means for creating the second design rule as being within the allowable range based on the allowable range from the first design rule determined to identify the second design rule;
Verification means for verifying whether layout data outside the pseudo error area violates the first design rule, and verifying whether layout data within the pseudo error area violates the second design rule. A layout verification apparatus characterized by:   The design value prepared for specifying the pseudo error area is for specifying, as a pseudo error area, an area including layout data related to an arcuate layout pattern. Layout verification device. The design value is a first value for specifying each region including layout data relating to each layout pattern of an arc shape having a first radius and an arc shape having a second radius as first and second pseudo error regions, respectively. And a second design value,
The data sorting means is configured to, based on the first and second design values, layout data, layout data in the first pseudo error area, layout data in the second pseudo error area, and the first and second 2 is divided into layout data other than the pseudo error area,
The permissible range for the first design rule is a first and second permissible range corresponding to the first and second design values, respectively.
The rule creating means creates a design rule for the first pseudo error area and a design rule for the second pseudo error area, respectively, as the second design rule based on the first and second allowable ranges. Yes,
The verification means performs verification by applying a design rule for the first pseudo error area to the layout data in the first pseudo error area as verification for the layout data in the pseudo error area, and The layout verification apparatus according to claim 2, wherein the layout data in the error area is verified by applying the design rule for the second pseudo error area. A layout verification method for verifying whether layout data violates design rules by a layout verification device ,
Based on the design value prepared for specifying the pseudo error area to which the second design rule different from the normal first design rule is applied, the layout data is divided into the layout data in the pseudo error area and the pseudo error area. A data segmentation process for segmenting into external layout data;
A rule creation step of creating the second design rule as being within the allowable range based on the allowable range from the first design rule determined to identify the second design rule;
Verifying whether layout data outside the pseudo error area violates the first design rule and verifying whether layout data within the pseudo error area violates the second design rule. A layout verification method characterized by:   5. The design value prepared for specifying the pseudo error area is for specifying an area including layout data related to an arc-shaped layout pattern as a pseudo error area. Layout verification method. The design value is a first value for specifying each region including layout data relating to each layout pattern of an arc shape having a first radius and an arc shape having a second radius as first and second pseudo error regions, respectively. And second design information,
In the data classification step, based on the first and second design information, layout data includes layout data in the first pseudo error area, layout data in the second pseudo error area, and the first and second design information. It is divided into layout data other than 2 pseudo error areas,
The permissible range for the first design rule is a first and second permissible range corresponding to the first and second design values, respectively.
In the rule creating step, a design rule for the first pseudo error area and a design rule for the second pseudo error area are created as the second design rule based on the first and second allowable ranges,
In the verification step, as the verification of the layout data in the pseudo error area, the layout data in the first pseudo error area is verified by applying a design rule for the first pseudo error area, and the second pseudo error area is verified. 6. The layout verification method according to claim 5, wherein verification is performed by applying the design rule for the second pseudo error area to the layout data in the error area.

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