JP5293521B2 - Design rule check verification apparatus and design rule check verification method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a design rule check verification device and a design rule check verification method capable of verifying easily a DRC rule, and capable of confirming easily whether a verification result is correctly executed or not. <P>SOLUTION: A processor 1 compares a result of the user preparation DRC rule checked using a test pattern graphic form with a result of the automatically generated DRC rule checked using the test pattern graphic form, and determines the user preparation DRC rule to be correct when matched. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a design rule check verification apparatus and a design rule check verification method for testing a design rule file for verifying a layout of a semiconductor integrated circuit.

  In designing a semiconductor integrated circuit, a layout verification process is performed to check whether a layout called a mask pattern satisfies a design rule defined by a manufacturing process. In the layout verification process, in order to perform verification according to the design rule using a layout verification tool (also referred to as a DRC (Design Rule Check) tool), a description such as a command for inputting and instructing the design rule to the DRC tool is described. This is done using a design rule file made (also called DRC rule).

  This DRC rule is often created manually, or may be erroneously included because it may be manually modified after being automatically created by a tool or the like. If an error is included in the DRC rule, accurate layout verification cannot be performed. Therefore, first, whether or not the DRC rule itself is correctly created is checked using a test pattern.

  In order to create the test pattern, a method of manually creating it using a layout editor has been conventionally performed. In this method, there are usually several patterns with no error and some patterns with an error (for example, a combination of the minimum value specified by the design rule, one grid smaller than the minimum value, one grid larger than the minimum value, etc.). It is necessary to create each figure type, and since there are usually several tens to several hundreds of DRC rules, an enormous amount of patterns are created, which requires a lot of labor.

  In order to reduce this effort, a method of automating test pattern creation as in Patent Document 1, reducing test patterns as in Patent Document 2, and automatic rule creation rather than test pattern creation as in Patent Document 3 The prior art which improves by is proposed.

  Patent Document 1 describes that a test pattern is generated in consideration of a grid value, a number is assigned to each rule, and a test pattern for the rule is generated in a matrix.

  In Patent Document 2, individual rules are extracted from user-created DRC rules, the range of the extracted rules is expanded for each OK pattern that does not cause an error, and DRC is executed for each. As a result, it is described that if an error occurs outside the check range of the extracted standard rule, it is determined that the rule is correct.

  Patent Document 3 describes that rules for DRC and LVS (comparison between layout and netlist) are automatically generated from a template file, and layers and conditions are described in the template file.

  Although the above-described Patent Documents 1 to 3 significantly reduce the labor for creating a test pattern compared to a complete manual operation, the test pattern is not completely unnecessary. For example, in some cases, a desired DRC rule cannot be created completely automatically, and when the automatically created DRC rule is manually corrected, verification by a test pattern is required. There may also be a parameter input error during automatic generation. Therefore, it is still necessary to verify the DRC rule using the test pattern.

  In the prior art, there are places where the creation of such test patterns and DRC rules can be automated, but manual correction may be performed as described above, and the effort in DRC rule verification in such cases can be sufficiently reduced. There was no problem.

  In addition, when outsourcing DRC rule verification work, it is necessary to check whether the verification work or the like is correctly performed, and there is a problem that labor is required for such confirmation work.

  The present invention aims to solve such problems.

  That is, the present invention provides a design rule check verification apparatus and a design rule check verification method that can easily verify DRC rules and also can easily check whether the verification work or the like is performed correctly. It is intended to provide.

  According to the first aspect of the present invention, there is provided test pattern generation means for generating a test pattern for testing a design rule file for verifying a layout of a semiconductor integrated circuit, and the design using the test pattern generated by the test pattern generation means. In a design rule check verification device comprising a test means for testing a rule file, a design rule input means for inputting the design rule file generated manually, and a design rule generation means for automatically generating the design rule file And comparing the result of testing the design rule file input from the design rule input means with the test means and the result of testing the design rule file automatically generated by the design rule generation means with the test means, one The case is design rule check verification apparatus being characterized in that and a judging means judges that the input design rule file is correct from said design rule input means.

  The invention described in claim 2 is characterized in that, in the invention described in claim 1, the design rule generation means generates a plurality of design rule files by a plurality of description methods capable of obtaining the same logical result. And

  According to a third aspect of the present invention, in the second aspect of the present invention, if the determination means includes at least one of the plurality of design rule files that matches the result, the design rule input The design rule file input from the means is determined to be correct.

  The invention described in claim 4 is the invention described in any one of claims 1 to 3, wherein the checksum element of the result file in which the result determined by the determining means is described is encrypted. An encryption means is provided for generating a ciphertext and adding the ciphertext to the result file.

The invention described in claim 5 is a design rule check verification method for generating a test pattern for testing a design rule file for verifying a layout of a semiconductor integrated circuit, and testing the design rule file using the test pattern. Using the test pattern, the design rule input step for inputting the design rule file generated manually, the design rule generation step for automatically generating the design rule file, and the design rule file input in the design rule input step A first test step for testing, a second test step for testing the design rule file automatically generated in the design rule generation step using the test pattern, a result of the first test step, and the first test step Results of the second test process Comparing, if a match is design rule check verification method characterized by having a a determination step of determining a design rule file you entered is correct by the design rule input step.

  The invention described in claim 6 is the invention described in claim 5, wherein, in the design rule generation step, a plurality of design rule files are generated by a plurality of description methods capable of obtaining the same logical result. And

  In the invention described in claim 7, in the invention described in claim 6, the determination step includes inputting the design rule if any one of the plurality of design rule files matches the result. It is determined that the design rule file input in the process is correct.

  The invention described in claim 8 is the ciphertext obtained by encrypting the checksum element of the result file describing the result determined in the determination step in the invention described in any one of claims 5 to 7. And an encryption step of adding the ciphertext to the result file.

  According to the invention described in claim 1, the result of testing the design rule file input from the design rule input unit by the test unit, and the result of testing the design rule file automatically generated by the design rule generation unit by the test unit, , And the design rule file input from the design rule input means determines that the design rule file is correct, the determination means determines that the DRC rule (design rule file) created by the user is automatically generated as a standard DRC. By checking using the rules, it is possible to verify that the DRC rules created by the user are correct. For this reason, it is possible to omit the process of manually determining that the execution result of the user-created DRC rule is correct with respect to the automatically generated test pattern. Can be greatly reduced.

  According to the invention described in claim 2, the design rule generating means generates a plurality of design rule files by a plurality of description methods that can obtain the same logical result, that is, a description method having the same meaning and purpose. Therefore, the design rule file input from the design rule input means can be checked without depending on the description method.

  According to the third aspect of the present invention, the determination means determines that the design rule file input from the design rule input means is correct if at least one of the plurality of design rule files matches the result. Therefore, it is possible to prevent erroneous determination due to a difference in the automatically generated description.

  According to the invention described in claim 4, since the encryption unit for adding the ciphertext obtained by encrypting the checksum element of the result file in which the result determined by the determination unit is described is added to the result file, When verifying DRC rules by outsourcing, etc., it is possible to encrypt the result file indicating that the verification has been performed correctly at the outsourcer, so that the verification result can be prevented from being falsified and verified correctly at the outsourcer. Can be omitted.

  According to the invention of claim 5, the result of testing the design rule file input in the design rule input process is compared with the result of testing the design rule file automatically generated by the design rule generation process. In this case, since the determination process determines that the design rule file input in the design rule input process is correct, the user-created DRC rule (design rule file) is checked using the automatically generated standard DRC rule. Thus, it is possible to verify that the DRC rule created by the user is correct. For this reason, it is possible to omit the process of manually determining that the execution result of the user-created DRC rule is correct with respect to the automatically generated test pattern. Can be greatly reduced.

  According to the invention described in claim 6, since the design rule generation step generates a plurality of design rule files by a plurality of description methods capable of obtaining the same logical result, the design rule generation process does not depend on the description method. The design rule file input from the rule input means can be checked.

  According to the seventh aspect of the present invention, the determination step determines that the design rule file input from the design rule input means is correct if at least one of the plurality of design rule files matches the result. Therefore, it is possible to prevent erroneous determination by the automatically generated description.

  According to the invention described in claim 8, since it includes an encryption step of adding to the result file a ciphertext obtained by encrypting the checksum element of the result file in which the result determined by the determination step is described. When verifying DRC rules by outsourcing, etc., it is possible to encrypt the result file indicating that the verification has been performed correctly at the outsourcer, so that the verification result can be prevented from being falsified and verified correctly at the outsourcer. Can be omitted.

It is a block diagram of the design rule check verification apparatus concerning one Embodiment of this invention. It is a flowchart of operation | movement of the design rule check verification apparatus shown in FIG. It is an example of a test pattern figure automatically generated by the design rule check verification apparatus shown in FIG. It is a rule description example for width check automatically generated by the design rule check verification apparatus shown in FIG. FIG. 4 is a diagram in the case where the DRC execution results of the DRC file described manually in the test pattern graphic example shown in FIG. 3 and the automatically generated DRC file match. FIG. 3 is a file example describing an execution result of the flowchart shown in FIG. 2. FIG. FIG. 4 is an error graphic when the DRC execution results of the DRC file described manually in the test pattern graphic example shown in FIG. 3 and the automatically generated DRC file do not match.

[First Embodiment]
Hereinafter, an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a configuration diagram of a design rule check verification apparatus according to an embodiment of the present invention. FIG. 2 is a flowchart of the operation of the design rule check verification apparatus shown in FIG. FIG. 3 is an example of a test pattern graphic automatically generated by the design rule check verification apparatus shown in FIG. FIG. 4 shows an example of a width check rule description automatically generated by the design rule check verification apparatus shown in FIG. FIG. 5 is a diagram in the case where the DRC execution results of the DRC file described manually in the test pattern graphic example shown in FIG. 3 and the automatically generated DRC file match. FIG. 6 is a file example describing the execution result of the flowchart shown in FIG. FIG. 7 shows an error graphic when the DRC execution results of the DRC file described manually in the test pattern graphic example shown in FIG. 3 and the automatically generated DRC file do not match.

  FIG. 1 shows a design rule check verification apparatus 10 according to an embodiment of the present invention. A design rule check verification apparatus 10 shown in FIG. 1 includes a test pattern generation unit, a test unit, a design rule generation unit, a processing unit 1 as a determination unit, a keyboard 2 as a design rule input unit, a mouse 3, and a design. A storage device 4 as rule input means and a display device 5 are provided.

  The processing device 1 performs design rule check processing (test pattern generation, design rule check (DRC) execution, result comparison, encryption processing) based on input from the keyboard 2 and mouse 3 and data stored in the storage device 4. The result is displayed on the display device 5 or stored in the storage device 5.

  The keyboard 2 inputs commands for design rule check processing. The mouse 3 is used as an auxiliary means for command input for the design rule check process when an instruction is given by a GUI (Graphical User Interface) during input or display. Not only the mouse 3 but also a pointing device such as a tablet or a trackball may be used.

  The storage device 4 stores test pattern data, DRC rules, design rule check execution results, result files, and the like. The DRC rule in this embodiment indicates a design rule file in the scope of claims.

  The display device 5 displays an execution state and a result file in response to an input from the keyboard 2 or the mouse 3.

  Next, the operation of the design rule check verification apparatus 10 shown in FIG. 1 will be described with reference to the flowchart of FIG.

  First, in step S201, DRC check values are designated using the keyboard 2 or the like, and the processing apparatus 1 automatically generates test patterns corresponding to the check values, and the process proceeds to steps S202 and S204. For this automatic generation, a known technique that has been conventionally performed may be used.

Examples of the check value include the following. Only the main designated elements are listed here, but it is assumed that necessary check values are prepared according to the application.
Rule value: A value specified by a design rule, and a minimum value of the width and interval of a figure is specified.
・ Usage: Check rule types for width check, interval check, overlap check, etc.
Grid value: The minimum grid value when creating a layout pattern and when executing DRC.
Layer number: The layer number of the generated test pattern. Multiple designations may be made depending on the application.
-File name: File name for storing the generated test pattern.
-Cell name: The cell name of the generated test pattern.

  In addition, the test pattern generated in this step includes both a pattern in which there is no error in DRC and a pattern in which there is an error. In the pattern without error, for example, a figure equal to the check value is generated, and in the pattern with error, for example, a figure smaller by one grid than the check value is generated.

  There are two steps S202 and S204 as the next step of the process of step S201. These may be executed from either of them or may be processed in parallel. It is sufficient that both processes (the process from step S202 to S203 and the process from step S204 to S206) have been completed by step S207.

  In step S202 as the first test process, the processing device 1 executes DRC with a user-created DRC rule as a manually generated design rule file created in advance, and proceeds to step S203. The DRC rule may be stored in advance in the storage device 4 as a file, or may be input from the keyboard 2 and stored in the storage device 4 as a file. The process of storing this DRC rule in the storage device 4 in advance or inputting it from the keyboard 2 and storing it in the storage device 4 as a file is the design rule input step. In this step, a rule corresponding to the check value designated in step S201 is executed. That is, the user-created DRC rule includes a plurality of check descriptions, but only the target of the check value is executed.

  Next, in step S203, the processing apparatus 1 generates an error graphic for the pattern with error obtained as a result of step S202, and the process proceeds to step S207.

  On the other hand, in step S204 as the design rule generation process, the processing apparatus 1 automatically generates a standard DRC rule based on the check value designated in step S201, and the process proceeds to step S205. In automatic generation, even if the standard DRC rule has the same purpose (check value), a plurality of descriptions can be made depending on the method. Further, in this case, the shape of the output figure may differ as a DRC result. The number of standard DRC rules corresponding to the number is generated. That is, a plurality of design rule files are generated by a plurality of description methods that can obtain the same logical result. In addition, this method includes generation of necessary layer calculation processing according to the application (for example, in the application of the minimum width check for the figure constituting the gate part of the MOS transistor, the AND of the diffusion part and the polysilicon part) Process, etc. These processes are defined according to the application).

  Next, in step S205 as the second test process, the processing apparatus 1 executes DRC for one of the standard DRC rules generated in step S204, and the process proceeds to step S206.

  Next, in step S206, as in step S203, the processing apparatus 1 generates an error graphic for the pattern with error obtained as a result of step S205, and the process proceeds to step S207.

  Next, in step S207, the processing apparatus 1 performs graphic pattern comparison for each error graphic obtained in steps S203 and S206, and proceeds to step S208. The comparison in this step is the same as the conventional LVL (Layout Versus Layout), and the difference between each error graphic is detected by exclusive OR (XOR). For example, if the two are the same error graphic, the difference is not detected, but if there is a different part, the different part is output as a result. Another method may be a method of performing simple file comparison instead of LVL. This is because there may be no difference as a result of the assumption that each error graphic is executed with the same version of the same layout verification tool. It is possible to substitute.

  Next, in step S208 as a determination step, the processing device 1 determines whether there is no difference in the comparison result in step S207, that is, whether both error graphics match. If they match, it can be determined that the user-created DRC rule and the standard DRC rule are performing the same processing for the test pattern, and as a result, it is determined that the user-created DRC rule is performing standard processing. it can. Therefore, the DRC rule created by the user is verified by the test pattern, and it can be treated that the quality can be ensured. In this case, the process proceeds to step S211. If they do not match, the process proceeds to step S209. That is, the result of testing the design rule file input from the design rule input means by the test means and the result of testing the design rule file automatically generated by the design rule generation means by the test means are compared. The design rule file input from the design rule input means is determined to be correct.

  Next, in step S209, the processing apparatus 1 determines whether or not the standard DRC rules for all the methods have been implemented. If the standard DRC rules for the unimplemented methods remain, the process returns to step S204, When the standard DRC rule process is performed and the standard DRC rules for all techniques are executed, the process proceeds to step S210.

  Next, in step S210, when all the standard DRC rules are executed, a matching error graphic is not obtained as a result, and the processing apparatus 1 determines that there is a problem with the user-created DRC rule. . The mismatch status is displayed as a report on the display device 5 to inform the rule creator that there may be a problem with the rule.

  On the other hand, in step S211, the processing apparatus 1 creates the result of matching in step S208, the check value specified in step S201, and execution time data (rule name, execution environment, execution date and time, executor, etc.) as a result file. The process proceeds to S212.

  Next, in step S212 as an encryption step, the processing device 1 adds, for example, a sentence obtained by encrypting the checksum element of each row to the result file in step S211 to the last row of the result file. A known method may be applied as an encryption method.

  The design rule check verification apparatus 10 shown in FIG. 1 also has a function of checking that the result file to which the ciphertext is added in step S212 in FIG. 2 has not been tampered with. This check is performed by, for example, a method of encrypting a portion other than the ciphertext with respect to the result file in the same manner as the process of step S212 and confirming that the same ciphertext as the result file is obtained and not falsified. Use.

  Next, an embodiment in which processing is performed according to the flowchart shown in FIG. 2 will be described with reference to FIGS.

  FIG. 3 is an example of a test pattern figure that is automatically generated in step S201 of FIG. In the area of the error-free pattern 301, pattern figures having no error in DRC are collected, and in the area of the pattern with error 305, pattern figures having an error in DRC are collected. FIG. 3 shows an example of a test pattern for width check.

  Each of the graphics 302 to 304 is drawn with a rectangle, a polygon, and a line segment graphic with a width, and has a width corresponding to the check value designated in step S201 for each side of each graphic. However, since the width of the oblique portion of the graphic 304 of this embodiment cannot be expressed accurately by one grid, the check value is added with an interval of less than one grid.

  The figures 306 to 308 are similar to the figures 302 to 304, but the distance (width) between some sides of each figure is one grid smaller than the check value. Specifically, the width of the left and right is small in the graphic 306, the width of the constricted portion is small in the graphic 307, and the width of the oblique portion is small by one grid in the graphic 308. However, since the width of the oblique portion of the graphic 308 of this embodiment cannot be expressed accurately by one grid, the check value is obtained by subtracting an interval less than one grid. Further, in the figure, the difference of one grid is exaggerated and expressed in a large size.

  Next, FIG. 4 shows an example of a width check rule automatically generated in step S204. The description example depends on the DRC tool to be used. Therefore, FIG. 4 is an example, and only a conceptual part will be described.

  First, FIG. 4A will be described. “WIDTH_CHECK_L02_1” in FIG. 4A indicates a rule name to be checked. In the width check for the layer “L02”, the last “1” indicates that the pattern number is 1. The following “[]” indicates a check description for the rule name. "" Min. Layer02 width 1.7um (INTERNAL) "" indicates a comment character string indicating the check content. “INTERNAL L02 <1.7” in the next line indicates that the width check for “L02” is an error of less than 1.7 μm in INTERNAL processing (interval spacing check). The next “POLYGON_OUT” indicates that an error is output as a polygonal figure.

  Next, FIG. 4B will be described. “WIDTH_CHECK_L02_2” in FIG. 4B indicates a rule name to be checked. In the width check for the layer “L02”, the last “2” indicates that the pattern number is 2. “[]” Indicates a check description for the rule name. ““ Min. Layer02 width 1.7um (WIDTH) ”” indicates a comment character string indicating the check content. “L02 WIDTH <1.7” indicates that the width check for “L02” is an error of less than 1.7 μm in WIDTH processing (extracting a figure that does not satisfy the specified width).

  As described above, there are a plurality of description methods for checking the distance (width) between some sides of each figure. In step S204 of FIG. 2, when there are such a plurality of methods, a plurality of DRCs are used. While outputting the rule, steps S204 to S209 are repeated a plurality of times (in this embodiment, twice when both (a) and (b) of FIG. 4 are performed). That is, in the present invention, not the DRC rule grammar check but the purpose and meaning indicated by the description are checked, and there are a plurality of methods (command descriptions) for performing the correct check. Have the same purpose and meaning, but there are cases where the error figures output as a result of commands or options do not match. In addition, since the purpose and meaning indicated by the description of the DRC rule are checked, it is only necessary that one of the plurality matches. In this way, when only one type is generated, there is a possibility of erroneous determination, so that a plurality of methods are generated to reduce rework due to erroneous determination.

  FIG. 5 shows an error graphic as a result obtained by DRC execution in steps S202 and S203 and steps S205 and S206. Note that only the hatched portion is actually output, but the figure in FIG. 3 is superimposed for easy understanding. FIG. 5 shows a case where the same error graphic is obtained as a result of steps S202 and S203 and steps S205 and S206. Further, the rule automatically generated in step S204 is assumed to use FIG. The error-free pattern 301 is in the same state as the error-free pattern 301 because no error is detected, indicating that there is no hatched portion and no error graphic. The figure of the pattern 305 with an error has a hatched portion, the figure 306 has an error figure 406, the figure 307 has an error figure 407, and the figure 308 has an error figure 408.

  In the case of FIG. 5, since the same error graphic is obtained in the results in steps S202 and S203 and the results in steps S205 and S206, the error graphic matches in the process of step S208. Therefore, the process proceeds to step S211.

  An example of the result file created in step S210 is shown in FIG. This example includes the processing result of step S212. Note that the numbers on the left side of FIG. 6 indicate line numbers for the following explanation, and are not included in the file contents.

  The contents of FIG. 6 will be described. Lines 01 to 08 are comments. Line 09 describes the name of the process to be checked. Line 10 describes the process summary as a comment of the process name. The eleventh line indicates a check name in the rule (the rule has a plurality of check contents, and the contents of one check among them). The 12th line contains a check name comment. Lines 13 to 22 indicate that the result of step S208 is the same. Lines 23 to 26 describe a check environment as auxiliary information. In this example, each is an execution host name, execution date, execution user name, and execution directory. Line 28 describes a marker character string “END ...” indicating that the processing in step S210 has been completed. This is the output in step S211.

  The encrypted character string processed in step S212 is described in line 29. When the first half is an encryption type and a plurality of encryption means are prepared, a type code indicating the means is described for identification. This is the result of the latter half hexadecimal number being encrypted. Thus, in this embodiment, the encryption is not performed on the entire file, but in this example, the result of encrypting the checksum elements in the file up to the 28th line is added.

  The encryption method is, for example, calculating the checksum of each line of the result file with 1 byte, concatenating it as a character string, further encrypting with the DES (Data Encryption Standard) method, MYSTY method, etc., and lower 16 bytes A ciphertext method or a method that considers a checksum of a vertical line instead of a checksum of each line (encryption by combining vertical and horizontal checksum character strings) is performed. However, the method is not limited to these, and other methods may be used as long as the checksum of the result file is encrypted.

  Note that the function of checking that the result file to which the ciphertext is added in step S212 described above has not been tampered with, for example, re-encrypts and reads all but the last line when the result file of FIG. 6 is read. As a result, it is detected that the file contents have not been tampered with by comparing the ciphertext of the file with the re-encrypted ciphertext. If the file contents have been tampered with, the ciphertext of the read result file will not match the re-encrypted ciphertext.

  Next, the case where the error graphic does not match in the determination in step S208 will be described with reference to FIG. For example, when the place that should be 1.7 μm in the user-created DRC rule in step S202 is 1.8 μm, the result of step S203 for the test pattern graphic of FIG. 3 is as shown in FIG. The grid value in the case of FIG. 7 is 0.1 μm.

  In FIG. 3, since the width of each figure of the error-free pattern 301 is set to 1.7 μm, the distance between most sides does not satisfy 1.8 μm, and the error figure 502, 503 and 504 appear. The error pattern 305 also results in an increase in errors compared to FIG.

  On the other hand, since the rule generated in step S204 is 1.7 μm, the result of step S206 is the same as in FIG. Accordingly, the error graphic of FIG. 4 and FIG. 5 is compared in the process of step S207, and the process moves to the process of step S209 because the error graphic does not match.

  In step S209, it is determined whether all the standard DRC rules have been implemented. If there is only one rule shown in FIG. 4A, a report that the error graphic does not match is created in step S210 and the process ends. To do. This report is displayed on the display device 5 but may be stored in the storage device 4 at the same time. The rule writer can obtain information for correcting the mistake of the rule by this report. If the rule of FIG. 4B exists in step S209, the process proceeds to step S204 for the rule of FIG. 4B.

  Here, another example in which the error graphic does not match in the determination in step S208 will be described. When the place that should be 1.7 μm is 1.6 μm in the user-created DRC rule in step S202, the following result is obtained for the test pattern figure of FIG. In this case as well, the grid value is set to 0.1 μm. As a result of step S203, no error is output in the error-free pattern 301 (because the interval between each side of each figure is 1.7 μm or more). No error is output even in the error pattern 305 (because the interval between each side in each figure is 1.6 μm or more). For this reason, the determination in step S208 does not match. The subsequent processing is the same as in the above-described embodiment.

  According to the present embodiment, the processing device 1 compares the result of testing the user-created DRC rule with the test pattern graphic and the result of testing the automatically generated DRC rule with the test pattern graphic, If they match, it is determined that the user-created DRC rule is correct. Therefore, the DRC rule created by the user is tested using the automatically generated standard DRC rule to verify that the DRC rule is correct. For this reason, it is possible to omit the process of manually determining that the execution result of the user-created DRC rule is correct with respect to the automatically generated test pattern. Can be greatly reduced.

  Moreover, it is possible to determine whether the user-created DRC rule is correct as a result only by first setting and executing a check value. Conventionally, the operation of confirming the shape of the error graphic for each pattern on the graphic display device can be omitted if the DRC rule created by the user is correct.

  Further, the processing device 1 generates a plurality of DRC rules by a plurality of description methods capable of obtaining the same logical result, and if any one of the plurality of DRC rules matches the result, the user-created DRC Since the rule is determined to be correct, the user-created DRC rule can be tested without depending on the description method, and erroneous detection due to a difference in automatically generated description can be prevented.

  In addition, since the processing apparatus 1 adds a ciphertext obtained by encrypting the checksum element of the result file in which the determined result is described to the result file, the DRC rule is verified by an outsourcing or the like In addition, it is possible to encrypt the result of whether the verification at the consignee has been correctly performed, and it is possible to detect whether the verification result has been falsified by reading the result file again. Therefore, tampering can be prevented and the reconfirmation process of whether or not the verification is correctly performed at the consignor can be omitted.

  It should be noted that by adding the above-mentioned ciphertext, not only outsourcing, but also if there is a discrepancy in the verification result due to insufficient capacity or mistake of the verifier (an error is output by comparing the DRC results) Nevertheless, it is possible to cope with cases such as a case where an error is missed.

  In addition, the present invention can be configured as a program that is installed on a general-purpose computer instead of a dedicated device.

  The present invention is not limited to the above embodiment. That is, various modifications can be made without departing from the scope of the present invention.

1 Processing device (test pattern generation means, test means, design rule generation means, determination means)
2 Keyboard (design rule input means)
3 mouse 4 storage device (design rule input means)
DESCRIPTION OF SYMBOLS 5 Display apparatus 10 Design rule check verification apparatus S202 1st test process S204 Design rule production | generation process S205 2nd test process S208 Judgment process S211 Encryption process

JP-A-6-290235 JP 2006-350420 A Japanese Patent Laid-Open No. 10-63699

Claims (8)

Test pattern generation means for generating a test pattern for testing a design rule file for verifying a layout of a semiconductor integrated circuit; and test means for testing the design rule file using the test pattern generated by the test pattern generation means. In the provided design rule check verification device,
A design rule input means for inputting the manually generated design rule file;
Design rule generation means for automatically generating the design rule file;
The result of testing the design rule file input from the design rule input unit by the test unit and the result of testing the design rule file automatically generated by the design rule generation unit by the test unit were compared and matched. A determination means for determining that the design rule file input from the design rule input means is correct, and
A design rule check verification device characterized by comprising:   The design rule check verification apparatus according to claim 1, wherein the design rule generation unit generates a plurality of design rule files by a plurality of description methods capable of obtaining the same logical result.   The determination means determines that the design rule file input from the design rule input means is correct if there is a match among the plurality of design rule files. 2. The design rule check verification device according to 2.   An encryption unit that generates a ciphertext obtained by encrypting a checksum element of a result file in which a result determined by the determination unit is described, and adds the ciphertext to the result file is provided. The design rule check verification device according to any one of Items 1 to 3. In a design rule check verification method for generating a test pattern for testing a design rule file for verifying a layout of a semiconductor integrated circuit, and testing the design rule file using the test pattern,
A design rule input process for inputting the manually generated design rule file;
A design rule generation step for automatically generating the design rule file;
A first test process for testing the design rule file input in the design rule input process using the test pattern ;
A second test process for testing the design rule file automatically generated in the design rule generation process using the test pattern ;
The result of the first test step and the result of the second test step are compared, and if they match, a determination step for determining that the design rule file input in the design rule input step is correct,
A design rule check verification method characterized by comprising:   6. The design rule check verification method according to claim 5, wherein, in the design rule generation step, a plurality of design rule files are generated by a plurality of description methods capable of obtaining the same logical result.   The determination step determines that the design rule file input in the design rule input step is correct if at least one of the plurality of design rule files has a matching result. 6. The design rule check verification method according to 6.   6. The method according to claim 5, further comprising: an encryption step of generating a ciphertext obtained by encrypting a checksum element of a result file describing a result determined in the determination step, and adding the ciphertext to the result file. The design rule check verification method according to any one of 7.

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