JP2013077263A - Layout pattern generation device and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily generate layout patterns used for correctly verifying the validity of a design rule check.SOLUTION: A graphics input section 24 accepts the input of an OK pattern that is generated so as to satisfy a predetermined drawing standard for a layout pattern of a semiconductor device. A reference position specification section 28 accepts, for the OK pattern, an input that specifies a part satisfying the drawing standard as a reference position. A verification pattern generation section 34 adds a predetermined change to the reference position of the OK pattern, thereby generating an NG pattern that does not satisfy the drawing standard.

Description

  The present invention relates to a layout pattern generation apparatus and program, and more particularly to a layout pattern generation apparatus and program for generating a layout pattern of a semiconductor device.

  In general, in LSI design, a design rule check that reports an error to a layout location that violates the drawing standard (hereinafter referred to as DRC) to confirm whether the LSI layout is created according to the drawing standard. Has been implemented.

  The DRC receives a verification rule describing a check rule or procedure, and detects and reports a location that violates the drawing standard in the layout according to the input.

  DRC needs to accurately detect and report on all layouts that violate the drawing criteria, but nothing should be reported for non-violating layouts, and its accuracy is an input validation rule Depends on the rules and procedures described in.

  In order to confirm whether the correct rule or procedure is described in the verification rule, DRC is performed on a layout pattern (hereinafter referred to as “OK pattern”) that does not have a violation of the drawing standard, and no violation is reported. In addition, it is necessary to confirm that the violation part and the content of the violation are reported by performing DRC on the layout pattern (hereinafter referred to as NG pattern) where the drawing standard violation exists.

  As for the NG pattern, in order to confirm that the violation of the drawing standard is accurately detected for the complex combination of the actual layout, all the combinations of the layout patterns assumed in the actual layout data are determined as the NG pattern. Need to be created as.

  In general, there are multiple plotting standard items for a single process, so create an OK pattern and NG pattern layout for each plotting standard item (hereinafter, the OK pattern and NG pattern will be referred to as the verification pattern). Then, it is necessary to confirm the validity of the verification rule by executing DRC on the verification pattern and confirming the result.

  Here, a technique for automatically generating test data for checking an error in an LSI layout verification rule is known (Patent Documents 1 and 2).

JP-A-6-290235 Japanese Patent Laid-Open No. 10-063699

  However, since the number of drawing standard items for one process is very large, there is a problem that it takes a very long time to create a verification pattern manually using a drawing device.

  In addition, when the layout pattern is assumed as the layout data but is not created as an NG pattern, it is not possible to confirm the detection failure of the drafting violation by the DRC, and the layout data in which the drafting standard violation exists. Will be leaked as a defective product.

  In addition, in the techniques described in Patent Documents 1 and 2, since the pattern is automatically generated from the verification rule, the validity of the verification rule itself cannot be correctly confirmed even if the generated pattern is used. There is a problem.

  The present invention has been made to solve the above-described problems, and provides a layout pattern generation apparatus and program that can easily generate a layout pattern used to correctly confirm the validity of a design rule check. For the purpose.

  In order to achieve the above object, a layout pattern generation device according to the present invention includes a pattern input unit that receives an input of a reference layout pattern generated so as to satisfy a predetermined drawing standard for a layout pattern of a semiconductor device; By applying a predetermined change to the reference location of the reference layout pattern, reference specifying means for receiving an input that specifies a portion that satisfies the drawing standard as a reference location for the reference layout pattern, Generating means for generating a layout pattern that does not satisfy the drawing standard.

  The program according to the present invention draws a computer on a pattern input unit for receiving an input of a reference layout pattern generated so as to satisfy a predetermined drawing standard for a layout pattern of a semiconductor device, and drawing the reference layout pattern. A reference designating unit that accepts an input designating a portion that satisfies the standard as a standard location, and a layout pattern that does not satisfy the drawing standard by adding a predetermined change to the standard location of the standard layout pattern. It is a program for making it function as a production | generation means to produce | generate.

  According to the present invention, an input of a reference layout pattern generated so as to satisfy a predetermined drawing standard for a layout pattern of a semiconductor device is received by a pattern input unit. The reference designating unit accepts an input for designating a portion satisfying the drawing standard as a standard location for the standard layout pattern.

  Then, the generation unit generates a layout pattern that does not satisfy the drawing standard by making a predetermined change to the reference location of the reference layout pattern.

  In this way, it is possible to generate layout patterns that do not satisfy the drawing standards by making changes to the reference points that satisfy the drawing standards specified for the reference layout pattern. A layout pattern used for correct confirmation can be generated easily.

  As described above, according to the layout pattern generation apparatus and program of the present invention, the layout pattern that does not satisfy the drawing standard is changed by changing the reference point that satisfies the drawing standard specified for the reference layout pattern. Therefore, the layout pattern used for correctly confirming the validity of the design rule check can be easily generated.

It is the schematic which shows the structure of the verification rule test apparatus which concerns on the 1st Embodiment of this invention. It is a functional block diagram which shows the structure of the verification rule test apparatus which concerns on the 1st Embodiment of this invention. It is a figure which shows an example of a drawing reference book. It is a figure which shows an example of an OK pattern. It is a figure which shows the example which has arrange | positioned the marker to (A)-(C) OK pattern. It is a figure which shows an example of an NG pattern. It is a figure which shows a mode that the variation of a NG pattern is produced | generated from an OK pattern. It is a figure which shows a mode that the variation of a NG pattern is produced | generated from an OK pattern. It is a figure which shows a mode that the variation of a NG pattern is produced | generated from an OK pattern. It is a flowchart which shows the content of the processing routine in the verification rule test apparatus which concerns on the 1st Embodiment of this invention. It is a functional block diagram which shows the structure of the verification rule test apparatus which concerns on the 2nd Embodiment of this invention. It is a figure which shows an example of topology. It is a figure which shows the example which has arrange | positioned the marker to topology. It is a figure which shows an example of the OK pattern produced | generated from topology. It is a flowchart which shows the content of the processing routine in the verification rule test apparatus which concerns on the 2nd Embodiment of this invention. It is a figure which shows an example of (A) OK pattern, and a figure which shows an example of (B) NG pattern. It is a figure which shows an example of (A) OK pattern, and a figure which shows an example of (B) NG pattern. (A) A figure showing an example of an OK pattern, (B) A figure showing an example of an NG pattern, and (C) A figure showing an example of an NG pattern. (A) A diagram showing an example of an OK pattern, (B) a diagram showing an example of an NG pattern, (C) a diagram showing an example of an NG pattern, and (D) a diagram showing an example of an NG pattern. (A) A diagram showing an example of an OK pattern, (B) a diagram showing an example of an NG pattern, (C) a diagram showing an example of an NG pattern, and (D) a diagram showing an example of an NG pattern. (A) A diagram showing an example of an OK pattern, (B) a diagram showing an example of an NG pattern, (C) a diagram showing an example of an NG pattern, (D) a diagram showing an example of an NG pattern, and (E) an NG pattern It is a figure which shows an example. (A) A diagram showing an example of an OK pattern, (B) a diagram showing an example of an NG pattern, (C) a diagram showing an example of an NG pattern, and (D) a diagram showing an example of an NG pattern. (A) A diagram showing an example of an OK pattern, (B) a diagram showing an example of an NG pattern, (C) a diagram showing an example of an NG pattern, and (D) a diagram showing an example of an NG pattern. (A) A diagram showing an example of an OK pattern, (B) a diagram showing an example of an NG pattern, (C) a diagram showing an example of an NG pattern, (D) a diagram showing an example of an NG pattern, and (E) an NG pattern It is a figure which shows an example.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. An example in which the present invention is applied to a verification rule test apparatus for generating a verification pattern and checking whether a verification rule is valid will be described.

  As illustrated in FIG. 1, the verification rule test apparatus 10 according to the first embodiment is configured by a computer including a control unit 12, a storage unit 14, an input unit 16, and a display unit 18. The control unit 12 includes a CPU, an interface unit between the CPU and other components, and the like, and comprehensively controls the operation of the verification rule test apparatus 10. The storage unit 14 includes a storage medium that can be attached to and detached from the verification rule test apparatus 10 such as a hard disk or a flexible disk, and has a test program for causing the verification rule test apparatus 10 to test the layout verification rule file. I remember it. The input unit 16 is configured with a keyboard or the like, and receives data input from the user of the verification rule test apparatus 10. The display unit 18 includes a liquid crystal display device and the like, and displays various types of information.

  The control unit 12 reads the test program from the storage unit 14 and executes it. Thereby, a plurality of functional blocks are formed in the verification rule test apparatus 10. FIG. 2 is a diagram showing these functional blocks. As shown in FIG. 2, the verification rule test apparatus 10 includes a verification rule input unit 20, a verification rule storage unit 22, a graphic input unit 24, an OK pattern storage unit 26, a reference position specifying unit 28, a reference position storage unit 30, A verification pattern generation unit 32, a verification pattern storage unit 34, a rule determination unit 36, an error graphic storage unit 38, and a graphic display unit 40 are provided. The rule determination unit 36 is an example of a verification unit, and the graphic display unit 40 is an example of a verification result output unit.

  The verification rule input unit 20 accepts, as a layout verification rule file, rules and procedures that the DRC creates while viewing the drawing standard document when the DRC checks layout data. The verification rule storage unit 22 stores the input layout verification rule file. When DRC is executed in the design process, DRC is performed according to the rules and procedures stored in the verification rule storage unit 22.

  The drawing reference book is a drawing reference book for a layout pattern that exists for each process, and is a document in which the reference value of each drawing layer is described. In general, the drawing standard document is used when creating a layout for all drawing layers corresponding to the mask process of the process, such as the minimum width, minimum spacing, and minimum margin between figures. All the values (drawing standard) on drawing that are necessary are described. A description example of the drawing standard is shown in FIG.

  The graphic input unit 24 displays a graphic on the display unit 18, and the user operates the input unit 16 while looking at the drawing reference document, so that all the reference items in the drawing reference document are OK patterns according to the reference value. And accepts the input of the created OK pattern. For example, when it is determined that the width of layer A is 2.0 μm, the interval between layers A and B is 0.5 μm, and the margin between layers A and C is 1.0 μm as the drawing reference items, FIG. As shown in FIG. 5, a layout pattern that satisfies each item of the drawing standard is created.

  The OK pattern storage unit 26 stores the input OK pattern.

  The reference position designating unit 28 displays the OK pattern figure input on the display unit 18, and the user operates the input unit 16 to satisfy the reference value for one reference item in the drawing reference document. In addition to designating the portion created in step S3 as a reference location, an input for designating the name of the drawing layer corresponding to the reference item, the type of drawing reference, and the numerical value of the drawing reference is accepted.

  For example, as shown in FIGS. 5A to 5C, one reference point is provided by arranging a pair of marks (hereinafter referred to as markers) indicating positions that satisfy the drawing standard with respect to the OK pattern. specify. In the present embodiment, the shape of the marker is an arrow for convenience. The marker has a rule that means which end part of the OK pattern satisfies the drawing standard. For example, the rule is that the longest side of the arrow indicates the end of the pattern that satisfies the drawing criteria. In addition, the marker can have information indicating which layer is the reference. Further, when there are a plurality of reference items as shown in FIGS. 5A to 5C, an OK pattern in which one marker is arranged for each reference item is obtained.

  FIG. 5A shows a case where a marker is arranged at a position that satisfies the creation criterion item that the width of the layer A is 2.0 μm. , Information "Layer A" is given.

  FIG. 5B shows a case where a marker is placed at a position that satisfies the creation criterion item that the distance between layers A and B is 0.5 μm. Information “Layer A” is given as the name of the layer, and information “Layer B” is given as the name of the designation target layer to the right marker.

  FIG. 5C shows a case where a marker is arranged at a position satisfying the creation criterion item that the margin of layers A and C is 1.0 μm. Information “Layer A” is given as the name of the layer, and information “Layer C” is given as the name of the designation target layer to the lower marker.

  The reference position storage unit 30 stores the input reference position (marker arrangement) together with an OK pattern for each reference item for which the reference position is designated.

  The verification pattern generation unit 32 generates NG patterns of all variations based on the OK patterns and markers for each of all the reference locations stored in the reference position storage unit 30.

  The NG pattern is duplicated using the OK pattern and the marker assigned to the OK pattern as one unit, and has an end that satisfies the drawing criteria indicated by the marker in the duplicated layout pattern. For a figure drawn on the same layer as the drawing layer that the marker has as information, move the end in the direction perpendicular to the end indicated by the marker (the longest side of the marker). , A variation of the NG pattern is generated.

  Variations in the amount of movement when moving the end are moved to the right (up) by one drawing unit, moved to the left (down) by one drawing unit, moved so that the ends indicated by the two markers overlap, and two There are four types of movement as the marker positional relationship is reversed. Therefore, a maximum of four variations of NG patterns are generated for one OK pattern.

  Variations when an NG pattern is generated for the example of FIG. 5C are shown in FIGS. When a layout variation is created by moving an end portion to which a marker is attached, it is only necessary to move a figure having a side (end portion) on which one of a pair of markers is arranged. Here, an example in which a figure of layer C having an end indicated by a lower marker having layer C as layer information is moved is shown.

  In FIG. 6A, the upper end of the layer C is moved up by one drawing unit, and a layout in which the margins of the layers A and C are smaller by one drawing grid than the drawing reference value is generated as an NG pattern. Since the upper marker has “layer A” as the layer information, the end of the layer A figure does not move along with the marker. Since the lower marker has “layer A” as layer information, the upper end of “layer D” does not move in accordance with the marker.

  In FIG. 6B, the upper end of layer C is moved downward by one drawing unit, and a layout in which the margins of layers A and C are larger by one drawing grid than the drawing reference value is generated as an NG pattern. Since the upper marker has “layer A” as the layer information, the end of the layer A figure does not move along with the marker. Since the lower marker has “layer A” as layer information, the upper end of “layer D” does not move in accordance with the marker.

  In FIG. 6C, the upper end of the layer C is moved to the position of the upper marker, and the layout in which the positions of the layers A and C match (the layout in which the margins of the layers A and C are 0) is set as the NG pattern. Generate.

  In FIG. 6D, the upper end of the layer C is further moved upward by one drawing unit from the position of the upper marker, and a layout in which the positional relationship between the layers A and C is reversed is generated as an NG pattern.

  As shown above, the verification pattern generation unit 32, for each of all the reference locations stored in the reference position storage unit 30, as shown in FIGS. A variation NG pattern is generated.

  For each of all reference items, all variations of the NG pattern generated by the verification pattern generation unit 32 are stored in the verification pattern storage unit 34. The corresponding OK pattern is also stored in the verification pattern storage unit 34.

  The rule determination unit 36 performs DRC and checks whether or not the LSI layout data is created according to the drawing standard document in the LSI design process according to the rules and procedures described in the verification rule storage unit 22. To do. In accordance with the procedure of the verification rule storage unit 22, the rule determination unit 36 checks whether there is a violation of the drawing standard for all the verification patterns (OK pattern and NG pattern) stored in the verification pattern storage unit 34, and violates the drawing standard. The position of the current pattern is stored in the error graphic storage unit 38 as an error graphic.

  The graphic display unit 40 superimposes all verification patterns (OK pattern and NG pattern) stored in the verification pattern storage unit 34 on the DRC error graphic stored in the error graphic storage unit 38 and causes the display unit 18 to display them. .

  The user confirms the validity of the contents of the rule file for layout verification in the verification rule storage unit 22 by checking the OK pattern, the NG pattern, and the error graphic among the verification patterns displayed on the display unit 18. Can do.

  That is, among the verification patterns displayed by the graphic display unit 40, no DRC error graphic is displayed at the position of the OK pattern, and a DRC error graphic is displayed at the position of the NG pattern violation of the drawing standard. In the case (hereinafter referred to as a match between the verification rule and the verification pattern), it is possible to confirm that the rules and procedures for implementing DRC, that is, the contents stored in the verification rule storage unit 22 are correct.

  If the verification rule does not match the verification pattern, the DRC rules and procedures stored in the verification rule storage unit 22 are corrected, and the rule determination unit 36 again applies the verification pattern stored in the verification pattern storage unit 34 to the verification pattern. Then, DRC is performed, and the result displayed by the graphic display unit 40 is confirmed. The layout verification rule file is corrected and DRC is repeated until the verification rule and the verification pattern are finally matched.

  Next, the operation of the verification rule test apparatus 10 according to the present embodiment will be described. First, the user operates the input unit 16 while viewing the drawing standard document, creates a layout verification rule file, and inputs it to the verification rule test apparatus 10. The input layout verification rule file is stored in the verification rule storage unit 22. Then, the processing routine shown in FIG. 10 is executed by executing the test program in the control unit 12.

  In step 100, an OK pattern graphic input process is performed. The display unit 18 displays a layout pattern creation screen and accepts an input of an OK pattern created by an operation of the input unit 16 by the user. In step 102, the OK pattern input in step 100 is stored in the OK pattern storage unit 26.

  In the next step 104, a reference location designation process is performed. The display unit 18 displays the input OK pattern and accepts the marker arrangement designated by the user's operation of the input unit 16 for each reference item. In step 106, the marker arrangement specified in step 104 is stored in the reference position storage unit 30 together with the OK pattern.

  In step 108, the OK pattern is duplicated for each reference item by the number of variations of the NG pattern, and a predetermined value is set for each duplicated OK pattern based on the marker arrangement specified in step 106. The NG pattern of all the variations is generated, and the generated NG pattern is stored in the verification pattern storage unit 34 together with the OK pattern.

  In the next step 110, the layout verification rule file is read from the verification rule storage unit 22, and in step 112, all of the data stored in the verification pattern storage unit 34 are stored in accordance with the layout verification rule file read in step 110. DRC is performed on OK and NG patterns.

  In step 114, based on the result of DRC in step 112, the position of the pattern that violates the drawing standard is stored in the error graphic storage unit 38 as an error graphic.

  In the next step 116, all OK patterns and NG patterns stored in the verification pattern storage unit 34 and the error graphic stored in the error graphic storage unit 38 are overlapped and displayed on the display unit 18, and the processing routine is executed. Exit.

  The user confirms whether or not the verification rule and the verification pattern match with the display on the display unit 18, and when the verification rule and the verification pattern do not match, the user checks the verification rule storage unit 22. Modify the rules and procedures of the layout verification rule file stored in.

  As described above, according to the verification rule test apparatus according to the first embodiment, by making a predetermined change with respect to a reference location that satisfies the drawing criteria specified for the input OK pattern. Since an NG pattern can be generated, a verification pattern used to correctly confirm the validity of the design rule check can be easily generated.

  Also, an OK pattern drawn according to the drawing standard is input. Generally, the drawing layer name and the drawing reference value vary depending on the process. However, since these are input as OK patterns, the versatility of the verification rule test apparatus can be improved, and as a result, a verification pattern is generated. Can be shortened.

  Also, when LSI layout verification is performed, by designating a portion that satisfies the drawing standard in the LSI layout pattern and the numerical value of the drawing standard, all patterns assumed in the layout data can be generated as NG patterns. it can. For this reason, it is possible to prevent the generation of NG patterns necessary for confirming whether DRC can normally detect an error for each item of the drawing standard, and it is due to the detection failure of the design standard violation in the product design. The outflow of defective products can be prevented.

  Even if the OK pattern is a complicated layout pattern, it is possible to generate a variation of the NG pattern of a specific layer. For this reason, complex preconditions (such as when surrounded by a large number of complex recognition layers or when the surrounding drawing standards are constant values) are required for the standard to be checked. Even with a certain drawing standard, a verification pattern can be easily created by creating and inputting a layout pattern according to the drawing standard.

  In the above embodiment, the case where an OK pattern is created and input has been described as an example. However, the present invention is not limited to this. For example, layout data may be used as an OK pattern. For example, TEG data at the time of process development may be used as it is as an OK pattern. In this case, the time for generating the verification pattern can be further shortened.

  Next, a second embodiment will be described. In addition, about the part which becomes the structure similar to 1st Embodiment, the same code | symbol is attached | subjected and description is abbreviate | omitted.

  In the second embodiment, the first point is that the user inputs a layout created while keeping the relative positional relationship of the drawing layers in the creation standard, and the point that the verification rule test apparatus generates an OK pattern. This is different from the embodiment.

  As shown in FIG. 11, the verification rule test apparatus 210 according to the second embodiment includes a verification rule input unit 20, a verification rule storage unit 22, a graphic input unit 24, a topology storage unit 226, a reference position specifying unit 28, A reference position storage unit 30, a verification pattern generation unit 32, a verification pattern storage unit 34, a rule determination unit 36, an error graphic storage unit 38, and a graphic display unit 40 are provided.

  The graphic input unit 24 displays a layout pattern creation screen on the display unit 18, and the user operates the input unit 16 while looking at the drawing standard document, so that all the standard items defined in the drawing standard document are obtained. A layout pattern (hereinafter referred to as topology) that keeps the relative positional relationship of each drawing layer described in the reference document is created, and an input of the created topology is accepted. When creating the topology, it is created so as to satisfy only the relative positional relationship of the drawing layer indicated by each item of the reference document, but it is not necessary to satisfy the numerical value of the drawing reference. An example of the created topology is shown in FIG. In the example of FIG. 12 described above, as the drawing reference items, the width of layer A is 2.0 μm, the distance between layers A and B is 0.5 μm, and the margin between layers A and C is 1.0 μm. It has been.

  The topology storage unit 226 stores a topology that is created by the graphic input unit 24 and that satisfies the relative positional relationship indicated by each reference item of the drawing reference document.

  The reference position specifying unit 28 displays the layout of the topology stored in the topology storage unit 226 on the display unit 18 and specifies a portion in the topology that should satisfy the drawing standard indicated by the item of the drawing reference book as a reference location. , Accepts an input for designating the type of drawing reference and the value of the drawing reference at the reference location.

  For example, for all the topologies stored in the topology storage unit 226, in the topology displayed on the display unit 18, the input unit 16 is operated to place markers indicating the positions corresponding to the corresponding drawing reference items. . The meaning and use of the marker are the same as those in the first embodiment, but in addition, a reference value can be held as information by designating a numerical value of the drawing reference. FIG. 13 shows an example in which markers are arranged with respect to the topology of FIG. 12 for the item that the margin of layers A and C is 1.0 μm in the drawing standard.

  In the example of FIG. 13, as the name of the designation target layer, information “layer A” is given to the upper marker and “layer B” is given to the lower marker. The marker is given information that the drawing reference value at the position indicated by the marker is 1.0 μm.

  Information on each marker designated for the topology is stored in the reference position storage unit 30 together with the topology.

  The verification pattern generation unit 32 generates an OK pattern and an NG pattern as follows for all the topologies stored in the reference position storage unit 30 according to the marker arrangement and information of each topology.

  First, the verification pattern generation unit 32 duplicates the topology and the marker, and among the figures that coincide with the long side of the marker, for the figure that has the same layer name as the marker, the end of the figure is set so that the interval becomes the reference value. Move and use this as an OK pattern. An example of the created OK pattern is shown in FIG.

  Next, the verification pattern generation unit 32 generates NG patterns of all variations based on the positions and information of the OK patterns and markers. Since the method for generating the NG pattern based on the marker information is the same as that in the first embodiment, the description thereof is omitted. The created OK pattern and all variations of NG patterns are stored in the verification pattern storage unit 34.

  Next, the operation of the verification rule test apparatus 210 according to the present embodiment will be described. First, the user operates the input unit 16 while viewing the drawing standard document, creates a layout verification rule file, and inputs it to the verification rule test apparatus 10. The input layout verification rule file is stored in the verification rule storage unit 22. Then, when the test program is executed in the control unit 12, the processing routine shown in FIG. 15 is executed. In addition, about the process similar to 1st Embodiment, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted.

  First, in step 250, topology graphic input processing is performed. A layout creation screen is displayed on the display unit 18 and an input of a topology created by an operation of the input unit 16 by the user is accepted. In step 252, the topology input in step 250 is stored in the topology storage unit 226.

  In the next step 254, a reference location designation process is performed. The displayed topology is displayed on the display unit 18 and, for each reference item, the marker arrangement in the portion that should satisfy the reference item specified by the operation of the input unit 16 by the user, the type of the reference item, and Accepts input with reference value.

  In step 256, the marker arrangement input in step 254 is stored in the reference position storage unit 30 together with the topology.

  Then, in step 258, for each reference item, based on the marker arrangement input in step 254, the topology reference point is changed and specified so as to satisfy the input reference value. An OK pattern that satisfies the reference items is generated.

  In the next step 108, for each reference item, the OK pattern generated for the reference item in step 258 is duplicated by the number of variations of the NG pattern, and based on the marker arrangement input in step 254, A predetermined change is made to each copied OK pattern to generate NG patterns of all variations, and the generated NG patterns are stored in the verification pattern storage unit 34 together with the OK patterns.

  In the next step 110, the layout verification rule file is read from the verification rule storage unit 22, and in step 112, all of the data stored in the verification pattern storage unit 34 are stored in accordance with the layout verification rule file read in step 110. DRC is performed on OK and NG patterns.

  In step 114, based on the result of DRC in step 112, the position of the pattern that violates the drawing standard is stored in the error graphic storage unit 38 as an error graphic.

  In the next step 116, all OK patterns and NG patterns stored in the verification pattern storage unit 34 and the error graphic stored in the error graphic storage unit 38 are overlapped and displayed on the display unit 18, and the processing routine is executed. Exit.

  As described above, according to the verification rule test apparatus according to the second embodiment, the topology layout is used as an input. , Topology layout can be used. Therefore, the versatility of the created topology layout can be enhanced, and the versatility of the verification rule test apparatus can be enhanced. As a result, the time for generating the verification pattern can be shortened.

  Next, a third embodiment will be described. Since the configuration of the verification rule test apparatus according to the third embodiment is the same as that of the first embodiment, the same reference numerals are given and description thereof is omitted.

  In the third embodiment, the point that the minimum value or the maximum value is designated as the reference value for the drawing reference, and the variation of the NG pattern according to the type of the reference value is that of the first embodiment. It is different from the form.

  In the verification rule test apparatus according to the third embodiment, the graphic input unit 24 allows the user to operate the input unit 16 while viewing the drawing reference document, so that all the reference items in the drawing reference document are drawn. An OK pattern that satisfies the above is created, and an input of the created OK pattern is accepted. For example, when the minimum value of the graphic width is determined as the drawing reference item, a layout pattern having the minimum graphic width is generated as an OK pattern. When the maximum value of the graphic width is determined as the drawing standard item, a layout pattern having the maximum graphic width is created as an OK pattern. When the minimum value and the maximum value of the graphic width are defined as the drawing reference items, a layout pattern having the minimum or maximum graphic width is created as an OK pattern.

  In addition, the reference position designating unit 28 displays the OK pattern figure input to the display unit 18, and the user operates the input unit 16 to satisfy the drawing standard for one reference item in the drawing standard document. The part created to be specified is designated as the reference location, the name of the drawing layer, the type of drawing standard, the numerical value of the drawing standard, and the type of reference value (minimum value, maximum value, minimum value and maximum value) Accepts input specifying.

  The verification pattern generation unit 32 generates NG patterns of all variations based on the OK patterns and markers for each of all the reference locations stored in the reference position storage unit 30.

  If the figure width is specified as the drawing reference type for the reference location and the minimum value is specified as the reference value type, the expected violation layout in the layout data is the width less than the minimum width. The pattern. Therefore, the verification pattern generation unit 32 has a figure having a width smaller by one drawing unit than the reference minimum width based on an OK pattern (see FIG. 16A) having a figure having the same width as the reference minimum width. NG pattern (see FIG. 16B) having

  Further, when the figure width is specified as the drawing reference type and the maximum value is specified as the reference value type for the reference location, the verification pattern generation unit 32 is the same as the reference maximum width. Based on an OK pattern having a figure with a width (see FIG. 17A), an NG pattern (see FIG. 17B) having a figure having a width larger by one drawing unit than the standard maximum width is generated. .

  In addition, when the figure width is specified as the drawing reference type and the minimum value and the maximum value are specified as the reference value type for the reference location, the verification pattern generation unit 32 sets the reference maximum value. Based on an OK pattern (see FIG. 18 (A)) having a figure having a substantially same width, an NG pattern (see FIG. 18 (C)) having a figure having a width one drawing unit larger than the standard maximum width. And an NG pattern (see FIG. 18B) having a figure having a width smaller by one drawing unit than the reference minimum width.

  When the interval between figures is specified as the drawing reference type for the reference location and the minimum value is specified as the reference value type, the verification pattern generation unit 32 determines the reference minimum value and An NG pattern is generated based on an OK pattern (see FIG. 19A) having figures having the same interval. Here, the type of violation layout assumed in the layout data is a pattern in which the interval between two figures is smaller than the minimum interval by one drawing unit (see FIG. 19B), and two figures are in contact (figure (Interval between intervals = 0) pattern (refer to FIG. 19C) (hereinafter referred to as a TOUCH graphic), and the relative positions of two graphic sides are reversed and overlapped (interval between graphic <0) pattern ( Since there are three types (refer to FIG. 19D) (hereinafter referred to as OVERLAP figures), three types of patterns are generated as NG patterns.

  Similarly, when the interval between figures is specified as the drawing reference type for the reference location and the maximum value is specified as the reference value type, the verification pattern generation unit 32 sets the reference maximum value. Based on an OK pattern (see FIG. 20A) having a figure having the same interval as the pattern, the interval between the two figures is one pattern larger than the maximum interval by one drawing unit (see FIG. 20B), and the TOUCH figure (see FIG. 20). 20 (C)) and OVERLAP figure (see FIG. 20D) are generated as NG patterns.

  Similarly, when the interval between figures is specified as the drawing reference type and the minimum value and the maximum value are specified as the reference value type for the reference location, the verification pattern generation unit 32 generates the reference pattern. Based on an OK pattern having a figure having the same interval as the maximum value (see FIG. 21A), the interval between the two figures is a pattern smaller than the minimum interval by one drawing unit (see FIG. 21B), 2 There are four types of patterns: NG (see Fig. 21 (C)), TOUCH (see Fig. 21 (D)), and OVERLAP (see Fig. 21 (E)). Generate as a pattern.

  In addition, when a margin between figures is specified as the drawing reference type for the reference location, and the minimum value is specified as the reference value type, the verification pattern generation unit 32 determines the reference minimum value and An NG pattern is generated based on an OK pattern having a figure with the same margin (see FIG. 22A). Here, the type of violation layout assumed in the layout data is a pattern in which the margin of two figures is smaller than the minimum margin by one drawing unit (see FIG. 22B), and two figures are in contact (margin). = 0) pattern (TOUCH figure) (see FIG. 22C), the relative positions of the sides of the two figures are reversed (margin <0) pattern (OVERLAP figure) (see FIG. 22D) Since it is a type, three types of patterns are generated as NG patterns.

  Similarly, when a margin between figures is specified as the type of drawing reference for the reference location and the maximum value is specified as the type of reference value, the verification pattern generation unit 32 sets the reference maximum value. Based on an OK pattern (see FIG. 23A) having a figure with the same margin as the pattern, the margin of two figures is a pattern larger than the maximum margin by one drawing unit (see FIG. 23B), and a TOUCH figure (see FIG. 23). 23 (C)) and OVERLAP figures (see FIG. 23D) are generated as NG patterns.

  Similarly, when the margin between figures is specified as the drawing reference type for the reference location and the minimum value and the maximum value are specified as the reference value type, the verification pattern generation unit 32 generates the reference pattern. A figure having the same margin as the maximum value of the pattern is an OK pattern (see FIG. 24A), and the two figures have a margin smaller than the minimum margin by one drawing unit (see FIG. 24B). Four types are generated as NG patterns: a pattern whose margin is one drawing unit larger than the maximum margin (see FIG. 24C), a TOUCH figure (see FIG. 24D), and an OVERLAP figure (see FIG. 24E). To do.

  The other configuration and operation of the verification rule test apparatus according to the third embodiment are the same as those in the first embodiment, and thus the description thereof is omitted.

  As described above, according to the verification rule test apparatus according to the third embodiment, the type of the drawing reference and the value are input together with the designation of the reference point, and NG patterns of all variations are input according to the type of the drawing reference. Can be generated, and it is possible to prevent omission of creation of an NG pattern necessary for confirming whether DRC can normally detect an error for each item of the drawing standard.

  Note that the NG pattern generation method in the present embodiment may be applied to the second embodiment described above.

  In the present specification, the embodiment has been described in which the program is installed in advance. However, the program may be provided by being stored in a storage medium such as a CDROM.

10, 210 Verification rule test device 12 Control unit 14 Storage unit 16 Input unit 18 Display unit 20 Verification rule input unit 22 Verification rule storage unit 26 OK pattern storage unit 28 Reference position specifying unit 30 Reference position storage unit 32 Verification pattern generation unit 34 Verification pattern storage unit 36 Rule determination unit 38 Error graphic storage unit 40 Graphic display unit 226 Topology storage unit

Claims (8)

Pattern input means for receiving an input of a reference layout pattern generated so as to satisfy a predetermined drawing standard for a layout pattern of a semiconductor device;
A reference designating unit that accepts an input for designating a portion that satisfies the drawing standard as a standard location for the standard layout pattern;
Generating means for generating a layout pattern that does not satisfy the drawing standard by adding a predetermined change to the reference location of the reference layout pattern;
A layout pattern generation device including: Pattern input means for receiving an input of a layout pattern of a semiconductor device;
For the input layout pattern, a portion that should satisfy a drawing standard determined in advance for the layout pattern of the semiconductor device is designated as a reference position, and a reference value at the reference position for satisfying the drawing standard A standard designating means for accepting input for designating,
A reference layout pattern is generated by changing the reference location of the layout pattern based on the reference value so as to satisfy the drawing standard, and the reference location of the reference layout pattern Generating means for generating a layout pattern that does not satisfy the drawing standard by making a predetermined change;
A layout pattern generation device including: Rule storage means for storing a layout verification rule file created in advance according to the drawing standard and used for verifying a layout pattern of a semiconductor device;
Verifying the reference layout pattern using the layout verification rule file, and verifying means for verifying the layout pattern generated by the generating means;
Verification result output means for outputting a verification result by the verification means;
The layout pattern generation apparatus according to claim 1, further comprising:   The layout pattern generation device according to any one of claims 1 to 3, wherein the drawing standard defines a standard related to at least one of a graphic width, a space between graphics, and a margin between graphics. The drawing standard defines a standard for the width of a drawing,
5. The layout pattern generation according to claim 4, wherein the generation unit generates a layout pattern in which a width of a figure at the reference location of the reference layout pattern is changed so as to violate a reference related to a figure width defined by the drawing reference. apparatus. The drawing standard defines a standard for the interval between drawings,
The generation means includes a layout pattern in which an interval between figures at a reference position of the reference layout pattern is changed so as to violate a reference regarding an interval between figures determined by the drawing reference, and a figure at a reference position of the reference layout pattern. The layout pattern generation apparatus according to claim 4, wherein a layout pattern in which an interval between them is zero and a layout pattern that is changed so that two figures having an interval overlap at a reference location of the reference layout pattern are generated. The drawing standard defines a standard for a margin between drawings,
The generating means includes a layout pattern in which a margin between figures at a reference location of the reference layout pattern is changed so as to violate a standard regarding a margin between graphics determined by the drawing standard, and a graphic at a reference location of the reference layout pattern. 5. A layout pattern generation according to claim 4, wherein a layout pattern in which a margin between them is zero and a layout pattern in which a relative positional relationship between two figures having a margin at a reference location of the reference layout pattern is reversed are generated. apparatus. Computer
Pattern input means for receiving an input of a reference layout pattern generated so as to satisfy a predetermined drawing standard for a layout pattern of a semiconductor device;
With respect to the reference layout pattern, a reference designating unit that accepts an input that designates a portion that satisfies a drawing standard as a reference location, and a predetermined change to the reference location of the reference layout pattern, A program for functioning as generation means for generating a layout pattern that does not satisfy the drawing standard.

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