JP2006350420A - Device for testing rule file for layout verification and test method and test program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology for easily testing a rule file. <P>SOLUTION: A design rule extracting part 1 in a test device 10 extracts a certain design rule from a test object rule file RF. A rule file for test preparing part 2 prepares a plurality of rule files TRF for test in which a plurality of types of design rules for test including the same check items as those of the design rule extracted by the design rule extracting part 1, and including at least a design rule having a check value which is the same as that of the pertinent design rule and a design rule having a check value which is larger than the check value of the pertinent design rule are described. A design rule deciding part 3 decides the validity/invalidity of the design rule extracted by the design rule extracting part 1 by using a plurality of rule files TRF for test. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a test apparatus and test method for a layout verification rule file used when verifying a layout pattern of a semiconductor device, and a test program for causing a computer to execute a test for a layout verification rule file.

  When designing a semiconductor device including an LSI (large-scale integrated circuit) or the like, a layout verification device that verifies whether or not the layout pattern satisfies the design rule described in the design manual is used. . In this layout verification apparatus, a rule file describing a plurality of types of design rules and layout data indicating a layout pattern are input, and the layout pattern is verified based on the rule file.

  In general, design rules are written manually in a rule file, so it is necessary to test the created rule file. Conventionally, layout patterns that satisfy the design rules described in the design manual (hereinafter referred to as “OK patterns”) and layout patterns that do not satisfy the design rules (hereinafter referred to as “NG patterns”) are prepared. The OK pattern and the NG pattern are verified based on the created rule file, and the correctness of the created rule file is determined from the verification result.

  For example, if the design manual describes a design rule that the pattern width must satisfy 4.0 μm or more, an OK pattern with a pattern width of 4.0 μm, an NG pattern with a pattern width of 3.99 μm, And a design rule check (hereinafter referred to as “DRC”) is executed for these patterns using the created rule file. As a result, when there is no error in the DRC result of the OK pattern and there is an error in the DRC result of the NG pattern, it is determined that the created rule file is correct, and in other cases, the error is determined to be incorrect. .

  Patent Documents 1 to 3 describe techniques related to layout verification.

JP-A-6-290235 Japanese Patent Laid-Open No. 10-63699 JP 2004-5031 A

  As described above, in the conventional rule file test method, it is necessary to prepare an OK pattern and an NG pattern, and it takes time and effort to create these patterns. Particularly for the NG pattern, in order to improve the test accuracy, a pattern having a value shifted from the check value in the design rule by the minimum grid value at the time of pattern design (the minimum unit in which the coordinates of the vertex of the figure can be input) is prepared. Because it was necessary, it took time and effort.

  Therefore, the present invention has been made in view of the above-described problems, and an object thereof is to provide a technique capable of easily testing a rule file.

  A layout verification rule file test apparatus according to the present invention is a layout verification rule file test apparatus used when verifying a layout pattern of a semiconductor device, and includes a plurality of types of design rules. From each of the extraction unit for extracting a design rule from the above, the check item that is the same as the design rule extracted by the extraction unit, and the check value that is the same as the design rule and the check value of the design rule A test rule file creating unit for creating a plurality of test rule files each including a plurality of types of test design rules including at least a check value having a larger check value, and the plurality of test rule files Using the data extracted by the extraction unit. And a determination unit for determining correctness of the in-rules.

  The layout verification rule file test method of the present invention is a layout verification rule file test method used when verifying a layout pattern of a semiconductor device, and includes (a) a plurality of types of design rules. A step of extracting a design rule from the rule file to be tested; and (b) each having the same check items as the design rule extracted in the step (a) and having the same check value as the design rule. Creating a plurality of test rule files each describing a plurality of types of test design rules including at least one having a check value larger than the check value of the design rule, and (c) Using the plurality of test rule files created in step (b), The correctness of the design rule extracted in serial steps (a) and a determining step.

  The layout verification design rule test program according to the present invention is a layout verification rule file test program used when verifying a layout pattern of a semiconductor device, and includes (a) a plurality of types of design rules. A step of extracting a design rule from the rule file to be tested; and (b) each having the same check items as the design rule extracted in the step (a) and having the same check value as the design rule. Creating a plurality of test rule files each describing a plurality of types of test design rules including at least one having a check value larger than the check value of the design rule, and (c) The plurality of test rule files created in step (b) Using, but for executing the step of determining the computer correctness of the said design rule extracted in step (a).

  According to the layout verification rule file test apparatus, test method, and test program of the present invention, each has the same check items as a certain design rule in the rule file to be tested, and the same check value as the design rule. A plurality of test rule files each including a plurality of types of test design rules including at least one having a check value greater than the check value of the design rule, and a rule file to be tested The correctness of the design rule is determined. Therefore, the rule file to be tested can be tested without using a layout pattern (NG pattern) that does not satisfy the design rules described in the design manual. In general, since a rule file can be created more easily than a layout pattern, a test rule file can be created more easily than an NG pattern. Therefore, the test of the rule file to be tested can be easily executed, and the development man-hour and development period of the layout verification rule file can be shortened.

  FIG. 1 is a block diagram showing the configuration of a layout verification rule file test apparatus 10 according to an embodiment of the present invention. As shown in FIG. 1, the test apparatus 10 according to the present embodiment includes a computer that includes a control unit 100, a storage unit 200, an input unit 300, and a display unit 400. The control unit 100 includes a CPU, an interface unit between the CPU and other components, and controls the operation of the test apparatus 10 in an integrated manner. The storage unit 200 includes a storage medium that can be attached to and detached from the test apparatus 10 such as a hard disk or a flexible disk, and stores a test program TPG for causing the test apparatus 10 to execute a test of a layout verification rule file. ing. The input unit 300 is configured with a keyboard or the like, and receives data input from the user of the test apparatus 10. The display unit 400 includes a liquid crystal display device and the like, and displays various types of information.

  The control unit 100 reads the test program TPG from the storage unit 200 and executes it. Thereby, a plurality of functional blocks are formed inside the control unit 100. FIG. 2 is a diagram showing these functional blocks. As shown in FIG. 2, the control unit 100 executing the test program TPG includes a design rule extraction unit 1, a test rule file creation unit 2, a design rule determination unit 3, and a determination result file creation unit 4. Consists of.

  The design rule extraction unit 1 generates one design rule from a test target rule file (hereinafter referred to as “test target rule file RF”) created based on the design manual and describing a plurality of types of design rules. To extract. Then, the design rule extraction unit 1 creates and outputs a rule file in which the extracted design rules are described (hereinafter referred to as “extraction rule file ERF”).

  Each design rule described in the test target rule file RF includes a check item indicating to which item it is a rule, and a check value indicating a reference value of the check item. For example, in the design rule that the pattern width must satisfy 4.0 μm or more, the pattern width is a check item, and 4.0 μm is a check value.

  In DRC, graphic operations such as AND processing and OR processing are performed between two patterns in order to prevent the occurrence of pseudo errors, etc., and verification of whether the resulting graphic satisfies the design rule. Is done. Therefore, graphic operation information corresponding to the design rule is also described in the test target rule file RF.

  The design rule extraction unit 1 extracts design rules from the test target rule file RF and extracts graphic operation information corresponding to the design rules, and creates an extraction rule file ERF in which they are described.

  In a general rule file, a check command for instructing the layout verification apparatus to execute verification of a design rule is described, and design rule information is included in the check command. The rule file describes a graphic operation command for instructing the layout verification apparatus to execute graphic operation, and the graphic operation information is included in the graphic operation command. Therefore, the design rule extraction unit 1 extracts a check command and a graphic operation command corresponding to the check command from the test target rule file RF, and creates an extraction rule file ERF in which they are described.

  FIG. 3 is a diagram for explaining the design rules described in the test target rule file RF. The test target rule file RF includes a design rule that the pattern width d1 of the layout pattern fl1 shown in FIG. 3A must satisfy a predetermined value or more, and two patterns fl1 shown in FIG. 3B. The design rule that the inter-pattern interval d2 must satisfy a predetermined value or more, or the inclusion distance d3 between the layout patterns c1 and fl1 of different layers shown in FIG. 3C satisfies the predetermined value or more. Design rules that must be written.

  The inclusion distance d3 indicates an overlap margin in the layout patterns c1 and fl1 of two different layers arranged to overlap each other, and the outer shape of the upper pattern c1 is larger in plan view than the outer shape of the lower pattern fl1. It means the distance in plan view between the outer shape of the upper layer pattern c1 and the outer shape of the lower layer pattern fl1 in the case of being located inside.

  The test rule file creation unit 2 creates and outputs a plurality of test rule files TRF based on the extracted rule file ERF output from the design rule extraction unit 1. The test rule file creation unit 2 according to the present embodiment has the same items as the check items of the design rule of the extraction rule file ERF, and ranges from a value smaller than the check value of the design rule to a larger value. A plurality of test rule files TRF in which a plurality of types of test design rules having different check values in the included range are respectively described are created. At this time, the interval between check values in a plurality of types of test design rules is, for example, the minimum grid value at the time of designing a layout pattern.

  For example, if the extraction rule file ERF includes a design rule with the pattern width d1 as a check item and a check value of 4.0 μm, and the minimum grid value is 0.01 μm, the check item “ 5 test design rules, each of which has a “pattern width d1” and each has check values of 3.98 μm, 3.99 μm, 4.00 μm, 4.01 μm and 4.02 μm, respectively. A test rule file TRF is created.

  Further, the test rule file creation unit 2 also includes graphic calculation information described in the extraction rule file ERF in each of the plurality of test rule files TRF to be created.

  The design rule determination unit 3 uses the plurality of test rule files TRF output from the test rule file creation unit 2 and uses the design rule described in the extraction rule file ERF created by the design rule extraction unit 1. The correctness is determined and the determination result is output to the determination result file creation unit 4. The determination result file creation unit 4 creates a file describing the received determination result and outputs the file as the determination result file JDF. The display unit 400 displays the determination result indicated by the determination result file JDF output from the determination result file creation unit 4 on a display screen (not shown). Thereby, the user of the test apparatus 10 can visually confirm the test result for the test target rule file RF.

  Next, a series of operations of the test apparatus 10 according to the present embodiment from the start to the end of the test for the test target rule file RF will be described in detail. FIG. 4 is a flowchart showing the operation of the test apparatus 10 in this case. When the execution of the test program TRG is started in the control unit 100, as shown in FIG. 4, first, in step s1, the design rule extraction unit 1 reads the test target rule file RF created by the user of the test apparatus 10. . As described above, the storage unit 200 includes a storage medium that can be attached to and detached from the test apparatus 10, and the design rule extraction unit 1 reads the test target rule file RF written in the storage medium.

  Next, in step s2, the design rule extraction unit 1 extracts a check command including information on a certain design rule and a graphic operation command corresponding to the check command from the test target rule file RF. In step s 3, the design rule extraction unit 1 creates an extraction rule file ERF in which the extracted check command and graphic operation command are described, and stores them in the storage unit 200. Hereinafter, the design rule extracted in step s2, that is, the design rule described in the extraction rule file ERF is referred to as “extracted design rule”.

  Next, in step s4, the test rule file creation unit 2 reads the extracted rule file ERF from the storage unit 200. In step s5, a plurality of test rule files TRF are created from the extracted rule file ERF based on the number of files created and the minimum grid value input to the test apparatus 10 by the user. Here, the “number of file creations” means the number of the plurality of test rule files TRF created by the test rule file creation unit 2. Note that the number of file creations and the minimum grid value are input to the control unit 100 when the user operates the input unit 300.

  For example, in the extraction rule file ERF, an extraction design rule in which the check item is the pattern width d1 and the check value is 4.0 μm is described, and “5” is input as the number of file creations, and the minimum grid value is set. If “0.01 μm” is input, the test rule file creation unit 2 creates the same file as the extraction rule file ERF as one test rule file TRF. Then, in the extraction rule file ERF, by changing the value of the check value included in the check command, a file whose check value is 0.01 μm larger than 4.0 μm, a file larger by 0.02 μm, and 0 A file smaller by .01 μm and a file smaller by 0.02 μm are respectively created as test rule files TRF. Thereby, each has the same item (pattern width d1) as the check item of the extracted design rule, and the value (4.98 μm) is larger than the check value (4.0 μm) of the extracted design rule (4.0 μm). Five test design rules having different check values (3.98 μm, 3.99 μm, 4.00 μm, 4.01 μm and 4.02 μm) in the range including up to .02 μm were described. Five test rule files TRF are created (hereinafter, this numerical example is referred to as “Example 1”).

  In addition, in the extraction rule file ERF, an extraction design rule in which the check item is the pattern interval d2 and the check value is 3.0 μm is described, and “3” is input as the number of file creations, and the minimum grid value is set. If “0.05 μm” is input, the test rule file creation unit 2 similarly has a check item “pattern interval d2” based on the extracted rule file ERF, and has a check value. Three test rule files TRF in which three types of test design rules each having 2.95 μm, 3.00 μm, and 3.05 μm are described are created (hereinafter, this numerical example is referred to as “Example 2”). ).

  In addition, in the extraction rule file ERF, an extraction design rule in which the check item is the inclusion distance d3 and the check value is 0.90 μm is described, and “9” is input as the number of file creations, and the minimum grid value is set. If “0.05 μm” is input, the test rule file creation unit 2 has check items “include distance d3” based on the extracted rule file ERF, and 0.70 μm as a check value. For nine tests, each of which describes nine test design rules, each having 0.75, 0.80, 0.85, 0.90, 0.95, 1.00, 1.05, and 1.10 μm A rule file TRF is created (hereinafter, this numerical example is referred to as “Example 3”).

  After creating the plurality of test rule files TRF, the test rule file creation unit 2 stores the plurality of test rule files TRF in the storage unit 200 in step s6.

  Next, in step s7, the design rule determination unit 3 reads a plurality of test rule files TRF from the storage unit 200, one of them, and layout data indicating an OK pattern (hereinafter referred to as “OK layout data LD”). Are used to execute DRC for the OK pattern. In step s8, the design rule determination unit 3 creates a file indicating the DRC result (hereinafter referred to as “DRC result file”) and stores it in the storage unit. The design rule determination unit 3 performs the same operation for all test rule files TRF.

  In the present embodiment, OK layout data LD indicating an OK pattern used as a reference layout pattern is individually prepared for each extracted design rule. For example, if the extracted design rule has the pattern width d1 as a check item, the same design rule check as the extracted design rule described in the design manual in the pattern fl1 shown in FIG. A pattern having the same pattern width d1 as the value is adopted as an OK pattern, and layout data indicating the OK pattern is used in step s7.

  If the extracted design rule has the pattern interval d2 as a check item, the same design rule as the extracted design rule described in the design manual for the two patterns fl1 shown in FIG. A pattern having the same pattern interval d2 as the check value is adopted as an OK pattern, and layout data indicating the OK pattern is used in step s7.

  If the extracted design rule has the inclusion distance d3 as a check item, the two patterns c1 and fl1 shown in FIG. 3C are the same as the extracted design rule described in the design manual. The one having the same inclusion distance d3 as the check value of the design rule is adopted as the OK pattern, and the layout data indicating the OK pattern is used in step s7.

  Next, in step s9, the design rule determination unit 3 refers to the DRC result files related to all the test rule files TRF stored in step s8, determines whether the extracted design rule is correct, and determines the determination result. Output to the result file creation unit 4. In step s10, the determination result file creation unit 4 creates a file in which the received determination result is described, and stores the file in the storage unit 200 as the determination result file JDF.

  5-7 is a figure for demonstrating the determination operation | movement in the design rule determination part 3. FIG. FIG. 5 shows a result of the DRC result when the DRC is executed in step s7 using the five test rule files TRF in the first embodiment, and the result of determining whether the extracted design rule is correct or not based on the DRC result. It shows. In the example of FIG. 5, the pattern width d1 of the OK pattern is set to 4.0 μm, which is the same as the check value in the design manual, and the five test rule files TRF used are tested in order from the smallest check value. TRF1 to TRF5.

  FIG. 6 shows a DRC result when DRC is executed using the three test rule files TRF in the above-described second embodiment, and a result of determining whether the extracted design rule is correct or not based on the DRC result. ing. In the example of FIG. 6, the pattern interval d2 of the OK pattern is set to 2.0 μm, which is the same as the check value in the design manual, and the three test rule files TRF used are respectively tested rule files in order from the smallest check value. TRF11 to TRF13.

  FIG. 7 shows a DRC result when DRC is executed using the nine test rule files TRF in Example 3 described above, and a result of determining whether the extracted design rule is correct or not based on the DRC result. ing. In the example of FIG. 7, the inclusion distance d3 of the OK pattern is set to 1.0 μm, which is the same as the check value in the design manual, and the nine test rule files TRF used are respectively tested rule files in order from the smallest check value. TRF21-29.

  As shown in FIG. 5, the check value of the test design rule in the test rule file TRF1 is 3.98 μm, which is not more than 4.0 μm of the pattern width d1 of the OK pattern. Therefore, when the OK pattern is verified based on the test rule file TRF1, no error occurs in the DRC result. Similarly, since the check values of the test design rules in the test rule files TRF2 and TRF3 are less than or equal to the pattern width d1 of the OK pattern, when the OK pattern is verified based on the test rule files TRF2 and TRF3, respectively. However, no error occurs in the DRC result.

  On the other hand, since the check values of the test design rules in the test rule files TRF4 and TRF5 shown in FIG. 5 are larger than the pattern width d1 of the OK pattern, the OK pattern is determined based on the test rule files TRF4 and TRF5. If verified, an error occurs in the DRC result.

  Thus, when the DRC results regarding the test rule files TRF1 to TRF5 are viewed in order from the smallest check value, there is no error until the check value of the test rule file TRF is the same as the check value of the extraction design rule. When an error occurs only at the next check value, that is, a check value that is larger than the check value of the extracted design rule by the minimum grid value, the design rule determining unit 3 determines that the extracted design rule is correct. Therefore, the extraction design rule determination result in FIG. 5 is “OK”.

  On the other hand, when the DRC results regarding the test rule files TRF1 to TRF5 are viewed in order from the smallest check value, the check value of the test rule file TRF is not a value that is larger than the check value of the extraction design rule by the minimum grid value. When an error occurs in the DRC result for the first time with a value, in other words, there is an error in the DRC result for the first time except for the test rule file TRF4 having the next higher check value than the test rule file TRF3 having the same check value as the extracted design rule. If an error occurs in the DRC result in the entire range of check values in the created test rule file TRF, or if there is an error in the DRC result in the entire range of check values in the created test rule file TRF Does not occur Expediently, the design rule determining unit 3 determines that the extracted design rule is incorrect.

  In the example shown in FIG. 6, since an error has occurred in the DRC result in the entire range of check values in the created test rule files TRF11 to 13, the extracted design rule determination result in the figure is “NG”. Yes. In the example shown in FIG. 7, when the DRC results regarding the test rule files TRF21 to TRF29 are viewed in order from the smallest check value, the check value of the test rule file TRF is greater than the check value of the extracted design rule. Since an error has occurred in the DRC result with a value other than a value that is larger than the minimum grid value (error occurred in the test rule file TRF8 with a check value of 1.05 μm), the extracted design rule determination result in the figure is “NG” It has become.

  As described above, the design rule determination unit 3 refers to the DRC result file to determine whether the extracted design rule is correct, and the determination result file creation unit 4 creates the determination result file JDF indicating the determination result. Thereafter, the design rule determining unit 3 notifies the design rule extracting unit 1 that the extracted design rule is determined to be correct or not.

  Next, in step s11, the design rule extraction unit 1 determines whether or not correctness determination has been performed for all design rules described in the test target rule file RF. If not, step s2 is executed again. Then, the design rule different from the one extracted in the previous step s2 and the graphic operation information corresponding thereto are extracted from the test target rule file RF. In step s3, a new extraction rule file is created and stored. In step s4, a plurality of new test rule files TRF are created from the extracted rule file, and stored in step s6.

  Thereafter, in step s7, DRC for the OK pattern is executed based on each of the new plurality of test rule files TRF, and the DRC result file is created and stored in step s8. Next, step s9 is executed to determine whether the new extracted design rule is correct based on the newly created DRC result file. The determination result is described in the determination result file JDF created in the previous step s10. Then, when step s11 is executed again and it is determined that there is a design rule included in the test target rule file RF that has not been correctly determined, step s2 is executed and the same operation is performed thereafter. Is called. As a result, the final determination result file JDF describes the results of correct / incorrect determination for all rule files included in the test target rule file RF in a list format.

  If it is determined in step s11 that the correctness determination has been performed for all rule files included in the test target rule file RF, in step s12, the determination result file creation unit 4 stores the determination result file JDF from the storage unit 200. The data is read and output to the display unit 400, and the display unit 400 displays a list of determination results indicated by the determination result file JDF.

  FIG. 8 is a diagram illustrating an example of the contents of the determination result file JDF created by the determination result file creation unit 4. As shown in FIG. 8, in the determination result file JDF, the determination result in step s9 is described in a list format in association with the check command and the check value range.

  The check command “drc (fl1 with <4.0)” in the figure corresponds to the design rule that the pattern width d1 of the pattern fl1 in FIG. 3A should satisfy 4.0 μm or more. “Drc (fl1 sep <2.0)” corresponds to the design rule that the pattern interval d2 in the two patterns fl1 in FIG. 3B should satisfy 2.0 μm or more, and the check command “drc (fl1 c1 “enc <1.0)” corresponds to the design rule that the inclusion distance d3 in the patterns c1 and fl1 in FIG. 3C should satisfy 1.0 μm or more. The check value range in the figure does not mean the check value range in the test rule file TRF actually used in step s7, but the positive check value range, that is, the determination in step s9. This means the range of check values in the test rule file TRF at step s7 when it is assumed that the result is OK.

  As described above, the test apparatus 10 performs a test on the test target rule file RF created by the user and displays the test result.

  In the above operation example, in step s4, a check rule file TRF having a check value smaller than the extracted design rule, one having the same check value, and one having a larger check value are created. Even in the case of creating one having a large value and one having a large check value, the test target rule file RF can be tested.

  For example, when testing the test target rule file RF by using only the test rule file TRF having the same check value as the extracted design rule and the check value larger than that, the same check value is used. If an error does not occur in the DRC result when using a thing, and an error occurs in the DRC result when using a thing with a large check value, it is determined that the extraction design rule is correct, otherwise it is incorrect. It is determined that Even in such a case, the correctness of the extracted design rule can be determined with a certain degree of accuracy.

  As described above, in this embodiment, each check item has the same check item as the extracted design rule and has the same check value as the extracted design rule, and a check value larger than the check value of the extracted design rule. Whether or not the extracted design rule is correct is determined by using a plurality of test rule files TRF in which a plurality of types of test design rules including at least one having a value are described. Therefore, the test target rule file RF can be tested without using an NG pattern as in the present embodiment. In general, since the rule file can be easily created as a text file or the like, the test rule file TRF can be created more easily than the NG pattern. Therefore, the test of the test target rule file RF can be easily executed, and the development man-hour and development period of the layout verification rule file can be shortened.

  In the present embodiment, the plurality of types of test design rules have the same check value as the extracted design rule, and are larger than the check value of the extracted design rule by the minimum grid value at the time of designing the layout pattern. Since at least one having a check value is included, it is possible to reliably determine whether the extracted design rule is correct or not, and it is possible to improve the test accuracy for the test target rule file RF.

  For example, the extraction rule file ERF describes an extraction design rule in which the check item is the pattern width d1 and the check value is 3.99 μm, and the minimum grid value is 0.01 μm, which is different from the present embodiment. When two test rule files TRF with check values of 3.99 μm and 4.01 μm are created and DRC is executed on an OK pattern with a pattern width d1 of 4.0 μm using these, the check value is An error does not occur in the DRC result in the 3.99 μm test rule file TRF, and an error occurs in the DRC result in the test rule file TRF whose check value is 4.01 μm. In this case, as can be understood from the above description, the design rule determination unit 3 determines that the extracted design rule that is actually incorrect is correct.

  In this way, if multiple types of test design rules do not include a check value that is larger than the check value of the extracted design rule by the minimum grid value at the time of layout pattern design, the extracted design rule There is a possibility that an error occurs in the correctness determination of. Therefore, in order to improve test accuracy, as in this embodiment, some types of test design rules have a check value that is larger than the check value of the extracted design rule by a minimum grid value. It is desirable to be included.

  In this embodiment, since the determination result file JDF describing the determination result in step s9 in a list format is created, the determination result in step s9 can be easily confirmed by referring to the determination result file JDF. This can prevent omission of confirmation of the determination result.

It is a block diagram which shows the structure of the test apparatus which concerns on embodiment of this invention. It is a figure which shows the functional block of the control part which concerns on embodiment of this invention. It is a figure for demonstrating a design rule. It is a flowchart which shows operation | movement of the test apparatus which concerns on embodiment of this invention. It is a figure for demonstrating the determination operation | movement in the design rule determination part which concerns on embodiment of this invention. It is a figure for demonstrating the determination operation | movement in the design rule determination part which concerns on embodiment of this invention. It is a figure for demonstrating the determination operation | movement in the design rule determination part which concerns on embodiment of this invention. It is a figure which shows the content of the determination result file in the test apparatus which concerns on embodiment of this invention.

Explanation of symbols

1 design rule extraction unit, 2 test rule file creation unit, 3 design rule judgment unit, 4 judgment result file creation unit, 10 test device, JDF judgment result file, RF test target rule file, TPG test program, TRF test rule File.

Claims (6)

A test device for a layout verification rule file used when verifying a layout pattern of a semiconductor device,
An extraction unit that extracts a design rule from a rule file to be tested including multiple types of design rules;
Each having the same check item as the design rule extracted by the extraction unit, and having the same check value as the design rule and having a check value larger than the check value of the design rule A test rule file creation unit for creating a plurality of test rule files each including at least a plurality of types of test design rules including;
A layout verification rule file test apparatus comprising: a determination unit that determines whether the design rule extracted by the extraction unit is correct by using the plurality of test rule files. The layout verification rule file test apparatus according to claim 1,
The plurality of types of test design rules have the same check value as the design rule extracted by the extraction unit, and a check of a value larger than the check value of the design rule by a minimum grid value at the time of layout pattern design A device for testing a rule file for layout verification including at least one having a value. A layout verification rule file test apparatus according to any one of claims 1 and 2,
The determination unit verifies the reference layout pattern based on the test rule file for each of the plurality of test rule files, and the extraction unit extracts the extraction result based on the verification result obtained thereby. A layout verification rule file test device that determines whether a design rule is correct. The layout verification rule file testing device according to any one of claims 1 to 3,
The extraction unit extracts each of the plurality of types of design rules from the rule file to be tested,
The test rule file creation unit creates the plurality of test rule files for each of the plurality of types of design rules extracted by the extraction unit,
The determination unit determines correctness for each of the plurality of types of design rules extracted by the extraction unit,
A layout verification rule file test apparatus, further comprising: a determination result file creation unit that creates a file in which a determination result in the determination unit is described in a list format. A method for testing a layout verification rule file used when verifying a layout pattern of a semiconductor device,
(A) extracting a design rule from a test target rule file including a plurality of types of design rules;
(B) Each check item having the same check value as the design rule extracted in the step (a) and having the same check value as the design rule and a check value larger than the check value of the design rule Creating a plurality of test rule files each including a plurality of types of test design rules including at least
(C) using the plurality of test rule files created in the step (b) to determine whether the design rule extracted in the step (a) is correct or not, a layout verification rule file Testing method. A test program for a layout verification rule file used when verifying a layout pattern of a semiconductor device,
(A) extracting a design rule from a test target rule file including a plurality of types of design rules;
(B) Each check item having the same check value as the design rule extracted in the step (a) and having the same check value as the design rule and a check value larger than the check value of the design rule Creating a plurality of test rule files each including a plurality of types of test design rules including at least
(C) a layout for causing a computer to execute the step of determining whether the design rule extracted in the step (a) is correct using the plurality of test rule files created in the step (b) Test program for verification rule file.

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