JP2006221417A - Semiconductor integrated circuit, design method and device for semiconductor integrated circuit and design program for semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide the design method of a semiconductor integrated circuit capable of dispensing with visual check of layout data. <P>SOLUTION: This design method of a semiconductor integrated circuit has a step (a) for performing first simulation based on a ROM code, a step (b) for preparing layout data based on the ROM code, a step (c) for performing second simulation based on the layout data and a step (d) for comparing the result of the first simulation with the result of the second simulation. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit design method and a semiconductor integrated circuit designed by using such a semiconductor integrated circuit design method. Furthermore, the present invention relates to a semiconductor integrated circuit design apparatus using such a semiconductor integrated circuit design method and a program for designing the semiconductor integrated circuit.

  Conventionally, layout data in ROM (Read Only Memory) has been checked visually by a designer using a layout viewer or the like. However, it is practically impossible to check all of the enormous layout data by visual inspection by the designer, and it is a reality that only a part of the layout data is checked.

  Further, in view of the above situation, it is also confirmed that there is no error in the contents of the ROM by manufacturing a product (chip) without checking layout data and testing the chip. . However, in this case, if there is an error in the contents of the ROM, it is necessary to create layout data and manufacture a chip again, which causes a problem that TAT (Turn Around Time) becomes longer and costs increase.

By the way, ROM process EB data creating means for creating ROM process EB data based on ROM data, ROM process stream data creating means for creating ROM process stream data based on ROM data, and ROM process EB data creating means. There is known a ROM process EB data verification device comprising a comparing means for comparing the read ROM process EB data and the ROM process stream data created by the ROM process stream data creating means (for example, a patent) Reference 1).
However, the ROM process EB data verification apparatus disclosed in Patent Document 1 is for verifying ROM process EB data, not for verifying layout data.

JP 10-335227 A

  Therefore, in view of the above points, a first object of the present invention is to provide a method for designing a semiconductor integrated circuit that makes it unnecessary to visually check layout data. A second object of the present invention is to provide a semiconductor integrated circuit designed using such a method of designing a semiconductor integrated circuit. A third object of the present invention is to provide a semiconductor integrated circuit design apparatus using such a semiconductor integrated circuit design method. A fourth object of the present invention is to provide a program for designing a semiconductor integrated circuit.

  In order to solve the above problems, a method for designing a semiconductor integrated circuit according to the present invention includes a step (a) of performing a first simulation based on a ROM code, and a step (b) of generating layout data based on the ROM code. ), A step (c) for performing the second simulation based on the layout data, and a step (d) for comparing the result of the first simulation with the result of the second simulation.

The method for designing a semiconductor integrated circuit further includes a step (e) of repeating steps (b) to (d) when the result of the first simulation and the result of the second simulation do not match. Also good.
Further, the first simulation may be a logic simulation, and the second simulation may be a transistor switching simulation.

Further, step (a) may include a step (a1) for creating a behavior model based on the ROM code and a step (a2) for performing a logic simulation using the behavior model.
Step (c) may include a step (c1) for creating a net list based on the layout data and a step (c2) for performing a transistor switching simulation based on the net list.

  A semiconductor integrated circuit according to the present invention is designed by using the semiconductor integrated circuit design method according to the present invention.

  In addition, a semiconductor integrated circuit design apparatus according to the present invention includes a first simulation processing unit for performing a first simulation based on a ROM code, and layout data generation for generating layout data based on the ROM code. A processing unit, a second simulation processing unit for performing a second simulation based on the layout data, and a simulation result comparison processing unit for comparing the result of the first simulation with the result of the second simulation It comprises.

  The semiconductor integrated circuit design program according to the present invention includes a procedure (a) for performing a first simulation based on a ROM code, a procedure (b) for creating layout data based on a ROM code, and layout data. Based on this, the CPU executes the procedure (c) for performing the second simulation and the procedure (d) for comparing the result of the first simulation with the result of the second simulation.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing an outline of a semiconductor integrated circuit design apparatus according to an embodiment of the present invention. As shown in FIG. 1, the semiconductor integrated circuit design apparatus 1 includes an input unit 2, a display unit 3, a ROM (Read Only Memory) code recording unit 4, a first simulation processing unit 5, and layout data generation. A processing unit 6, a layout data recording unit 7, a second simulation processing unit 8, and a simulation result comparison processing unit 9 are provided.

The input unit 2 is a keyboard, a mouse, or the like for receiving input from a user (semiconductor integrated circuit design engineer), and the display unit 3 is a CRT, LCD, or the like for displaying a design result of the semiconductor integrated circuit. It is.
The ROM code recording unit 4 records a ROM code representing the data content of the ROM to be designed. As the ROM code format, the Intel HEX format, the Motorola S format, or the binary format is generally used.

The first simulation processing unit 5 includes a ROM library creation processing unit 11 and a logic simulation processing unit 12.
The ROM library creation processing unit 11 creates a ROM library (behavior model) capable of performing logic simulation based on the ROM code recorded in the ROM code recording unit 4. Specifically, the ROM library creation processing unit 11 converts the ROM code into a behavior model described in HDL (Hardware Description Language) such as Verilog (specified by IEEE1364-1995), VHDL (specified by IEEE1076-1987, etc.), and the like. Convert.

  The logic simulation processing unit 12 executes logic simulation of the behavior model created by the ROM library creation processing unit 11. The result of this logic simulation is sent to the simulation result comparison processing unit 9 as text data, waveform data, or the like. As the logic simulation processing unit 12, for example, a Verilog logic simulator, a VHDL logic simulator, or the like can be used.

The layout data creation processing unit 6 includes a ROM code format conversion processing unit 21 and a ROM data arrangement processing unit 22.
The ROM code format conversion processing unit 21 converts the ROM code format recorded in the ROM code recording unit 4 from a HEX format, an S format, or the like into a predetermined format that can be read by the ROM data arrangement processing unit 22.
The ROM data placement processing unit 22 creates layout data by performing placement / wiring processing on the ROM code that has been converted into a predetermined format by the ROM code format conversion processing unit 21. This layout data is recorded in the layout data recording unit 7.

The second simulation processing unit 8 includes an element extraction processing unit 31 and a transistor switching simulation processing unit 32.
The element extraction processing unit 31 extracts elements and wirings from the layout data recorded in the layout data recording unit 7 and creates a net list that is element and element connection information.

  The transistor switching simulation processing unit 32 performs transistor switching simulation based on the netlist created by the element extraction processing unit 31. The result of this transistor switching simulation is sent to the simulation result comparison processing unit 9 as text data, waveform data, or the like. As the transistor switching simulation processing unit 32, for example, a transistor switching simulation function of a Verilog logic simulator, a VHDL logic simulator, or the like can be used.

  The simulation result comparison processing unit 9 compares the result of the first simulation by the first simulation processing unit 5 with the result of the second simulation by the second simulation processing unit 8.

  ROM library creation processing unit 11, logic simulation processing unit 12, ROM code format conversion processing unit 21, ROM data arrangement processing unit 22, element extraction processing unit 31, transistor switching simulation processing unit 32, and simulation result comparison shown in FIG. The processing unit 9 can be configured by a CPU and software (program). This program, ROM code, and layout data can be recorded on a recording medium such as a hard disk, flexible disk, MO, MT, RAM, CD-ROM, or DVD-ROM.

  2 to 5 are flowcharts showing a semiconductor integrated circuit design process of the semiconductor integrated circuit design apparatus 1. The semiconductor integrated circuit design process of the semiconductor integrated circuit design apparatus 1 will be described below with reference to FIGS.

First, the first simulation processing unit 5 performs a first simulation process based on the ROM code in accordance with an instruction input from the user (semiconductor integrated circuit design engineer) (step S11).
FIG. 3 is a flowchart showing the contents of the first simulation process based on the ROM code. Hereinafter, the first simulation process based on the ROM code will be described with reference to FIG.

When the processing of FIG. 3 is started, first, the ROM library creation processing unit 11 creates a ROM library (behavior model) from the ROM code recorded in the ROM code recording unit 4 (step S21).
Next, the logic simulation processing unit 12 executes a logic simulation of the behavior model created by the ROM library creation processing unit 11 (step S22). Thus, the first simulation process based on the ROM code is completed.

Referring to FIG. 1 again, the layout data creation processing unit 6 performs layout data creation processing based on the ROM code in accordance with the user's instruction input (step S12). At this time, the user may optionally specify whether to create positive logic ROM layout data or negative logic ROM layout data. The layout data creation process based on the ROM code may be performed in parallel with the first simulation process based on the ROM code as a multitask process.
FIG. 4 is a flowchart showing the contents of layout data creation processing based on the ROM code. Hereinafter, the layout data creation processing based on the ROM code will be described with reference to FIG.

When the processing in FIG. 4 is started, first, the ROM code format conversion processing unit 21 converts the ROM code format recorded in the ROM code recording unit 4 into a predetermined format that can be read by the ROM data arrangement processing unit 22. (Step S31).
Next, the ROM data placement processing unit 22 creates layout data by performing placement / wiring processing on the ROM code converted by the ROM code format conversion processing unit 21 (step S32). Thus, the layout data creation process based on the ROM code is completed.

Referring to FIG. 1 again, the second simulation processing unit 8 performs a second simulation process based on the layout data (step S13). The second simulation process based on the layout data may be performed as a multitask process in parallel with the first simulation process based on the ROM code.
FIG. 5 is a flowchart showing the contents of the second simulation process based on the layout data. Hereinafter, the second simulation process based on the layout data will be described with reference to FIG.

When the processing of FIG. 5 is started, first, the element extraction processing unit 31 extracts elements and wirings from the layout data recorded in the layout data recording unit 7 and creates a net list (step S41).
Next, the transistor switching simulation processing unit 32 performs a transistor switching simulation based on the net list created by the element extraction processing unit 31 (step S42). This completes the second simulation process based on the layout data.

Referring again to FIG. 1, the simulation result comparison processing unit 9 includes a result of the first simulation (logic simulation) by the first simulation processing unit 5 and a result of the second simulation (transistor switching simulation) by the second simulation processing unit 8. Are compared (step S14).
When the result of the first simulation (logic simulation) matches the result of the second simulation (transistor switching simulation) (step S15), the simulation result comparison processing unit 9 is recorded in the layout data recording unit 7. Assuming that the layout data being correct is correct data, the process ends. In this case, the layout data recorded in the layout data recording unit 7 can be transferred to the mask manufacturing process. Further, the layout data recorded in the layout data recording unit 7 can be used as a ROM macro cell for an ASIC (Application Specific Integrated Circuit) or a single chip microcomputer.

  On the other hand, when the result of the first simulation (logic simulation) and the result of the second simulation (transistor switching simulation) do not match (step S15), the simulation result comparison processing unit 9 is recorded in the layout data recording unit 7. Assuming that the layout data is not correct, the process returns to step S12.

Note that the following may be considered as an example of the cause of the mismatch between the result of the first simulation (logic simulation) and the result of the second simulation (transistor switching simulation).
As described above, when creating layout data from a ROM code, the user can optionally specify whether to create positive logic ROM layout data or negative logic ROM layout data. It is common. In this option specification, when positive logic ROM layout data is to be created, it is erroneously specified to create negative logic ROM layout data, or when positive logic ROM layout data is to be created, positive logic ROM It may be erroneously specified to create layout data. In such a case, it is only necessary for the user to specify the correct option in the layout data creation process (step S12) again.

  As described above, according to the semiconductor integrated circuit design apparatus 1, whether the layout data is correct data by comparing the result of the first simulation based on the ROM code with the result of the second simulation based on the layout data. You can check that. As a result, it is possible to eliminate the need for checking the layout data by visual inspection, the entire layout data can be checked, the TAT can be shortened, and the cost can be reduced.

  The present invention can be used in a semiconductor integrated circuit including a ROM or a ROM macrocell, a semiconductor integrated circuit design method and design apparatus, and a semiconductor integrated circuit design program.

1 is a diagram showing an outline of a semiconductor integrated circuit design apparatus according to an embodiment of the present invention. 2 is a flowchart showing the operation of the semiconductor integrated circuit design apparatus 1 of FIG. 2 is a flowchart showing the operation of the semiconductor integrated circuit design apparatus 1 of FIG. 2 is a flowchart showing the operation of the semiconductor integrated circuit design apparatus 1 of FIG. 2 is a flowchart showing the operation of the semiconductor integrated circuit design apparatus 1 of FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Design apparatus of semiconductor integrated circuit, 2 Input part, 3 Display part, 4 ROM code recording part, 5 1st simulation process part, 6 Layout data creation process part, 7 Layout data recording part, 8 2nd simulation process part, 9 Simulation result comparison processing unit, 11 ROM library creation processing unit, 12 logic simulation processing unit, 21 ROM code format conversion processing unit, 22 ROM data arrangement processing unit, 31 element extraction processing unit, 32 transistor switching simulation processing unit

Claims (8)

Performing a first simulation based on the ROM code;
Creating layout data based on the ROM code (b);
Performing a second simulation based on the layout data;
Comparing the result of the first simulation with the result of the second simulation (d);
A method for designing a semiconductor integrated circuit comprising:   2. The semiconductor integrated circuit according to claim 1, further comprising a step (e) of repeating steps (b) to (d) when the result of the first simulation and the result of the second simulation do not match. Design method.   3. The method of designing a semiconductor integrated circuit according to claim 1, wherein the first simulation is a logic simulation and the second simulation is a transistor switching simulation. Step (a)
Creating a behavior model based on the ROM code (a1);
Performing a logic simulation using the behavior model (a2);
The method for designing a semiconductor integrated circuit according to claim 3, comprising: Step (c)
Creating a netlist based on the layout data (c1);
Performing a transistor switching simulation based on the netlist (c2);
The method for designing a semiconductor integrated circuit according to claim 3, further comprising:   A semiconductor integrated circuit, which is designed by using the semiconductor integrated circuit design method according to claim 1. A first simulation processing unit for performing a first simulation based on a ROM code;
A layout data creation processing unit for creating layout data based on the ROM code;
A second simulation processing unit for performing a second simulation based on the layout data;
A simulation result comparison processing unit for comparing the result of the first simulation and the result of the second simulation;
A device for designing a semiconductor integrated circuit. A procedure (a) for performing the first simulation based on the ROM code;
A procedure (b) for creating layout data based on the ROM code;
A procedure (c) for performing a second simulation based on the layout data;
A step (d) for comparing the result of the first simulation with the result of the second simulation;
A program for designing a semiconductor integrated circuit for causing a CPU to execute a program.

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