CN113627122A

CN113627122A - Test pattern verification method, device, equipment and storage medium

Info

Publication number: CN113627122A
Application number: CN202110925359.XA
Authority: CN
Inventors: 吴彬
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2021-08-12
Filing date: 2021-08-12
Publication date: 2021-11-09
Anticipated expiration: 2041-08-12
Also published as: CN113627122B

Abstract

The application provides a test pattern verification method, a test pattern verification device, test pattern verification equipment and a storage medium, which can be applied to the field of chip layout verification. The verification method comprises the following steps: and verifying whether the configuration file meets the requirements of the design rule or not by acquiring the configuration file of the test pattern to obtain a first verification result, and outputting the first verification result. The configuration file comprises a plurality of constraints configured for the test pattern by the designer, and the first verification result is used for indicating whether the test pattern is valid or not. The verification process is that the configuration file is verified before the configuration file is executed, and the test pattern is judged to be invalid as long as one item is found not to meet the requirement of the standard design rule, so that the efficiency and the accuracy of the verification of the test pattern can be improved.

Description

Test pattern verification method, device, equipment and storage medium

Technical Field

The present application relates to the field of chip verification, and in particular, to a method, an apparatus, a device, and a storage medium for verifying a test pattern.

Background

Generally, development of DRC is divided into two stages, the first stage being development of DRC code, and the second stage being development of verification graphics. Typically, the development time of the second stage takes two-thirds of the entire development cycle. As the process size becomes smaller, the design rule becomes more and more. Therefore, how to verify the validity of the test pattern quickly, comprehensively and accurately becomes a problem to be solved urgently.

Disclosure of Invention

The embodiment of the application provides a test pattern verification method, a test pattern verification device, test pattern verification equipment and a storage medium, and can improve the accuracy and efficiency of test pattern verification results.

According to some embodiments, a first aspect of the present application provides a method for verifying a test pattern, the method comprising:

acquiring a configuration file of a test pattern, wherein the configuration file comprises a plurality of constraint conditions configured for the test pattern;

verifying whether the configuration file meets the requirements of design rules to obtain a first verification result; the design rule requirements include rules for defining a range of values for each of the check terms in different check regions of the integrated circuit;

and outputting the first verification result, wherein the first verification result is used for indicating whether the test pattern is valid or not.

In an optional embodiment of the present application, the verifying whether the configuration file meets the requirement of the design rule to obtain a first verification result includes:

acquiring a first design rule and a second design rule of an inspection area where the test pattern is located through a Design Rule Manual (DRM) file; the first design rule includes a rule for defining a numerical range of a first check item in an inspection area where the test pattern is located, the second design rule includes a rule for defining a numerical range of a second check item in an inspection area where the test pattern is located, the first check item and the second check item having an association relationship therebetween;

verifying whether the configuration file meets a first design rule or not to obtain a second verification result;

verifying whether the configuration file meets a second design rule or not to obtain a third verification result;

and determining the first verification result according to the second verification result and the third verification result.

In an optional embodiment of the present application, the determining the first verification result according to the second verification result and the second verification result includes:

if the first verification result and the second verification result both indicate that the test pattern is valid, the first verification result is used for indicating that the test pattern is valid; or

And if at least one of the first verification result and the second verification result indicates that the test pattern is invalid, the first verification result is used for indicating that the test pattern is invalid.

In an optional embodiment of the present application, if the first verification result is used to indicate that the test pattern is invalid, the first verification result includes location information of an error field in the configuration file, and the method further includes:

responding to the input operation of a tester, and correcting the configuration file;

and verifying whether the modified configuration file meets the requirements of the design rule.

In an optional embodiment of the present application, if the first verification result is used to indicate that the test pattern is valid, the method further includes:

executing the configuration file of the test pattern to generate a test pattern;

and storing the test pattern into an effective test pattern library.

In an optional embodiment of the present application, the first check item comprises: a value of a distance between target objects in the integrated circuit, the second check term comprising: a positional relationship between target objects in the integrated circuit, the target objects including at least one of semiconductor structures, vias.

According to some embodiments, a second aspect of the present application provides a verification apparatus for a test pattern, the apparatus comprising: the device comprises an acquisition module, a processing module and an output module.

The acquisition module is used for acquiring a configuration file of a test graph, wherein the configuration file comprises a plurality of constraint conditions configured for the test graph;

the processing module is used for verifying whether the configuration file meets the requirement of a design rule or not to obtain a first verification result; the design rule requirements include rules for defining a range of values for each of the check terms in different check regions of the integrated circuit;

and the output module is used for outputting the first verification result, and the first verification result is used for indicating whether the test pattern is valid or not.

In an optional embodiment of the present application, the obtaining module is further configured to:

the processing module is specifically configured to:

In an optional embodiment of the present application, the processing module is specifically configured to:

In an optional embodiment of the application, if the first verification result is used to indicate that the test pattern is invalid, and the first verification result includes location information of an error field in the configuration file, the processing module is further configured to:

In an optional embodiment of the present application, the apparatus further comprises: a storage module; if the first verification result is used to indicate that the test pattern is valid, the processing module is further configured to:

the storage module is used for storing the test pattern into an effective test pattern library.

According to some embodiments, a third aspect of the present application provides an electronic device comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,

the memory stores instructions executable by the at least one processor to enable the electronic device to perform the method of any of the first aspects of the present application.

According to some embodiments, a fourth aspect of the present application provides a computer-readable storage medium having stored therein computer-executable instructions that, when executed by a processor, enable the processor to perform the method of any one of the first aspects of the present application.

According to some embodiments, a fifth aspect of the application provides a computer program product comprising a computer program which, when executed by a processor, implements the method of any of the first aspects of the application.

The embodiment of the application provides a test pattern verification method, a test pattern verification device, test pattern verification equipment and a storage medium, and can be applied to the field of chip layout verification. The verification method comprises the following steps: and verifying whether the configuration file meets the requirements of the design rule or not by acquiring the configuration file of the test pattern to obtain a first verification result, and outputting the first verification result. The configuration file comprises a plurality of constraints configured for the test pattern by the designer, and the first verification result is used for indicating whether the test pattern is valid or not. The verification process is that the configuration file is verified before the configuration file is executed, and the test pattern is judged to be invalid as long as one item is found not to meet the requirement of the standard design rule, so that the efficiency and the accuracy of the verification of the test pattern can be improved.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.

Fig. 1 is a first flowchart of a verification process of a test pattern provided in an embodiment of the present application;

fig. 2 is a second flowchart of a verification process of a test pattern provided in the embodiment of the present application;

FIG. 3 is a diagram illustrating check terms of a first design rule and a second design rule provided in an embodiment of the present application;

FIG. 4 is a first schematic diagram of an invalid test pattern provided by an embodiment of the present application;

FIG. 5 is a second schematic diagram of an invalid test pattern provided in the present application;

FIG. 6 is a schematic diagram of an effective test pattern provided by an embodiment of the present application;

fig. 7 is a first schematic structural diagram of a verification apparatus for a test pattern according to an embodiment of the present disclosure;

fig. 8 is a second schematic structural diagram of a verification apparatus for a test pattern according to an embodiment of the present application;

fig. 9 is a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms "first," "second," and the like in the description and in the claims of the present application and in the above-described drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein.

Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

From the initial architecture design of the chip to the final tape-out, the verification work runs through the whole design flow, and about 70% of the workload of the whole chip design is already occupied by verification. The layout verification is an indispensable link and mainly comprises Design Rule Check (DRC), circuit diagram layout comparison check (LVS), circuit extraction (NE) of the layout, Electrical Rule Check (ERC) and parasitic Parameter Extraction (PEX).

Design Rule Checking (DRC) is an important tool in layout verification, and includes checking whether a wiring pitch, a wiring width, and the like meet process requirements. It performs inspection on layout geometry to ensure that layout data can be produced and to achieve high yield on a given integrated circuit process technology.

The traditional layout verification process mainly depends on Manual work, and designers manually detect whether the test patterns of all regions on the layout meet the requirements of Design rules according to a Design Rule Manual (DRM). The layout verification process is time-consuming and labor-consuming, and missing or wrong detection exists due to the fact that the accuracy of detection results of manual detection is not high.

With the increasing scale and complexity of integrated circuits, the difficulty and workload of verification are also increased rapidly, and how to quickly, comprehensively and accurately verify the validity of a layout is a problem to be solved urgently at present.

In some embodiments, in the test pattern verification process, the test pattern may be generated by executing a configuration file of the test pattern, and it is verified whether the generated test pattern does not comply with the design rule, and the test time is to be improved. Generally, after a test pattern is generated according to a configuration file, if the generated test pattern does not conform to a certain design rule, an error is directly reported, so that the test time for verifying the test pattern in a test pattern library can be shortened on the whole, but the integrity and the accuracy of the test are also to be improved.

The verification process requires first executing a configuration file of the test pattern, and determining a valid or invalid test pattern based on the generated test pattern. Considering that the configuration file of the test pattern determines whether the test pattern is valid or invalid, the embodiment of the application starts from the configuration file, and verifies whether the test pattern is valid or not by analyzing whether each constraint condition in the configuration file meets each design rule requirement defined in a Design Rule Manual (DRM) file. Considering that there may be relevance between each constraint condition in the configuration file, for example, constraint condition 1 defines the width of a certain target object, and constraint condition 2 defines the position relationship between the target object and other target objects, after verifying whether constraint condition 1 matches with the corresponding design rule, regardless of the verification result, association constraint condition 2 of constraint condition 1 is also verified, so as to avoid missing or false detection of the constraint condition in the configuration file. On one hand, the process does not need to execute the configuration file of each test pattern, so that the test time can be shortened, and the test efficiency is improved; on the other hand, the accuracy of test pattern verification can be improved due to the analysis of all the constraint conditions in the configuration file.

Before describing the technical solutions of the present application, first, the terms of art related to the embodiments of the present application are briefly described.

The inspection areas involved in chip design include: a switch control (SWC) region, a Sense Amplifier (SA) region, a word-line driver (SWD) region, and a Peripheral (PERI) region.

Wherein the peripheral (circuit) region includes:

an X-decoder (XDEC), a Y-decoder (Y-DEC), an electrostatic discharge (ESD), a Seal Ring Seal-Ring, and the like.

The active region OD refers to a region on the silicon wafer where active devices are formed.

N-type metal-oxide-semiconductor: N-Metal-Oxide-Semiconductor, NMOS.

In the field of chip design, the design rule includes at least one design rule based on a width (width), a distance (space), an area (area), an inclusion relation (inclusion), and an extension relation (extended) of a semiconductor structure in a chip.

The width-based design rule is used to define a width of the semiconductor structure, for example, to define the width of the semiconductor structure to be less than a preset width.

Distance-based design rules are used to define the distance between semiconductor structures, e.g., to define the distance between semiconductor structures to be greater than a preset distance.

The area-based design rule is used to define an area of the chip region occupied by the semiconductor structure, for example, the area of the chip region occupied by the semiconductor structure is smaller than a preset area value.

Design rules based on containment relationships are used to define a positional relationship between semiconductors, such as defining another semiconductor structure contained within a certain semiconductor structure.

Design rules based on the extension relationship are used to define another positional relationship between the semiconductors, for example, to define the length of the polysilicon extending beyond the semiconductor layer to be greater than a predetermined length, so as to avoid short circuit.

The semiconductor structure of this embodiment may be a semiconductor layer, a semiconductor module, a semiconductor device, or the like, and this embodiment of the present application is not limited in any way.

Illustratively, table 1 is a table of design rule configurations based on POLY distance. As shown in table 1, the design rule PO _ S _01 defines that the distance between runner POLY is greater than or equal to 0.2 μm, and the design rule is applicable to the SA region, the SWD region, and the SWC region. The design rule PO _ S _05 defines that the distance between POLY is greater than or equal to 0.185 μm, and the design rule does not define the inspection region. The design rule PO _ S _28 defines that the distance between POLY is greater than or equal to 0.165 μm, which is applicable to NMOS transistors of the XDEC region.

TABLE 1

Illustratively, table 2 is a table of design rule configurations based on via contact to Poly tap distances. As shown in table 2, the design rule CT _ S _01 defines that the distance between contact and Poly tap is greater than or equal to 0.3 μm, which is applicable to the SA area. Poly tap is understood to be a contact on a semiconductor structure, which is used to connect other circuit elements. It should be noted that the configuration table of the design rule CT _ S _01 includes the design rule associated therewith, that is, "if tap cover contact < 1/2", "if tap cover contact < 1/2" defines the positional relationship between Poly tap and contact, and the overlap length of Poly tap and contact in a specific direction (e.g., horizontal direction) is less than half of the width value of contact in the specific direction.

TABLE 2

Illustratively, table 3 is a design rule configuration table based on contact width. As shown in table 3, the design rule CT _ W _01 defines the contact short side width to be 0.16 μm, and the design rule is applied to the SA area. The design rule CT _ W _02 defines the contact short side width to be 0.2 μm, and the design rule is applied to the SWD region. The design rule CT _ W _03 defines a contact short width of 0.26 μm, which is applicable to the PERI region.

TABLE 3

As can be seen from tables 2 and 3, the design rule CT _ S _01 of table 2 has an association relationship with the design rule CT _ W _01 of table 3, or the design rule CT _ W _01 is implicit in the design rule CT _ S _ 01. The test pattern is a valid test pattern only when both the design rule CT _ S _01 and the design rule CT _ W _01 are satisfied.

Based on the above description, the verification scheme of the test pattern provided in the present application is explained in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.

Fig. 1 is a first flowchart of a verification method for a test pattern according to an embodiment of the present application. The method of the present embodiment may be applied to any device that executes the test pattern verification method, such as a terminal device of a tester or a test server, and the present embodiment is not particularly limited.

As shown in fig. 1, the verification method of the test pattern of the present embodiment includes the following steps:

step 101, obtaining a configuration file of a test pattern, wherein the configuration file comprises a plurality of constraint conditions configured for the test pattern.

In this embodiment, the test pattern is used to reveal a spatial layout of at least one inspection area in the integrated circuit. The configuration file of the test pattern is a code file written by a designer according to a design rule manual DRM file, and the test pattern is automatically generated by executing the configuration file.

The DRM file comprises standard design rules for different check areas in the integrated circuit, the standard design rules for each check area comprising standard design rules for different check items in the check area. The DRM file is used as a basic file for assisting a designer to write a test pattern configuration file and a basic file for verifying the validity of the test pattern.

Inspection regions in integrated circuits include, but are not limited to, the SWC region, SA region, SWD region, PERI region, etc., described above.

The examination items in the examination area comprise at least one of the following examination items: a distance value between target objects in the integrated circuit, a width value of target objects in the integrated circuit, a positional relationship (including an inclusion relationship or an extension relationship) between target objects in the integrated circuit, and an area value of target objects in the integrated circuit. Wherein the target object comprises at least one of a semiconductor structure and a through hole. The semiconductor structure may be a semiconductor layer, a semiconductor module, a semiconductor device, or the like, and this embodiment is not particularly limited.

The plurality of constraints in the configuration file include: for defining attribute parameters of each target object in the test pattern, such as a distance value, an area value, etc. of the semiconductor structures, and for defining attribute parameters between the target objects in the test pattern, such as a distance value, etc. between the semiconductor structures. These constraints may or may not meet the standard design rule requirements of DRM, and therefore multiple constraints in the configuration file need to be validated to determine whether the test pattern is valid.

And 102, verifying whether the configuration file meets the requirement of the design rule or not to obtain a first verification result.

And 103, outputting a first verification result, wherein the first verification result is used for indicating whether the test pattern is effective.

In this embodiment, the design rule requirements include rules for defining a range of values for each of the check terms in different check regions of the integrated circuit. Illustratively, the SA area is an inspection area, and the design rule of the SA area includes: rules for defining the distance range between the semiconductor structures in the SA region, rules for defining the width range of the through-holes in the SA region, rules for defining the distance range between the semiconductor structures and the through-holes in the SA region, and the like.

It should be understood that the test pattern of the present embodiment may include a test pattern of one inspection region, and may also include test patterns of a plurality of inspection regions, which is not particularly limited in this embodiment. If the test pattern is a test pattern of an inspection area, only verifying whether the configuration file of the test pattern meets the standard design rule requirement of the inspection area; if the test pattern is a test pattern of a plurality of inspection regions, it is necessary to verify whether the configuration file of the test pattern meets the standard design rule requirements of each inspection region.

In this embodiment, the first verification result includes two results, i.e., a valid result and an invalid result of the test pattern. It should be understood that the test pattern is invalid as long as one check item in the test pattern does not meet the requirement of the design rule; and if all the check items in different check areas in the test pattern meet the requirements of the design rule, the test pattern is effective.

In the verification method for the test pattern shown in this embodiment, the configuration file of the test pattern is obtained, and whether the configuration file meets the requirement of the design rule is verified, so that a first verification result is obtained, and the first verification result is output. The configuration file comprises a plurality of constraints configured for the test pattern by the designer, and the first verification result is used for indicating whether the test pattern is valid or not. The verification process is that the configuration file is verified before the configuration file is executed, and the test pattern is judged to be invalid as long as one item is found not to meet the requirement of the standard design rule, so that the efficiency and the accuracy of the verification of the test pattern can be improved.

Optionally, in some embodiments, if the first verification result is used to indicate that the test pattern is invalid, where the first verification result includes location information of an error field in the configuration file, the method for verifying the test pattern further includes the following steps: responding to the input operation of a tester, and correcting the configuration file; and verifying whether the modified configuration file meets the requirements of the design rule.

Optionally, in some embodiments, if the first verification result is used to indicate that the test pattern is invalid, the method for verifying the test pattern further includes: correcting an error field in the configuration file according to the DRM file; and verifying whether the modified configuration file meets the requirements of the design rule.

Optionally, in some embodiments, after the configuration file is modified, it may be only verified whether the content of the error field in the configuration file meets the requirement of the design rule, so as to improve the detection efficiency.

On the basis of the above embodiments, the following embodiment mainly provides a detailed description of how to verify whether a configuration file meets the requirements of the design rule.

Fig. 2 is a second flowchart of a verification method for a test pattern according to an embodiment of the present application. As shown in fig. 2, the verification method of the test pattern of the present embodiment includes the following steps:

step 201, obtaining a first design rule and a second design rule of an inspection area where a test pattern is located through a design rule manual DRM file.

Wherein the first design rule includes a rule for defining a numerical range of a first check item in the inspection area where the test pattern is located, and the second design rule includes a rule for defining a numerical range of a second check item in the inspection area where the test pattern is located. The first check item is different from the second check item, and the first check item and the second check item have an association relationship.

It should be noted that, the two examination items have an association relationship therebetween, which can be understood as: the limitation conditions (e.g. numerical limitation conditions) of the two check items are that the inclusion and the included relationship or that the limitation conditions of the two check items have an association relationship. Illustratively, the inspection item 1 is a distance value between the through hole and the semiconductor structure, the inspection item 2 is a width of the through hole, and the definition condition of the inspection item 2 is included in the definition condition of the inspection item 1, so that the inspection item 1 and the inspection item 2 are considered to have an association relationship.

In an alternative embodiment of the present application, the first check item of the first design rule includes: a value of a distance between target objects in the integrated circuit, the second check term of the second design rule comprising: a width value of a target object in an integrated circuit. Illustratively, the first check term is a value of a distance between the semiconductor structures, and the second check term is a value of a width of the semiconductor structures.

In an alternative embodiment of the present application, the first check item of the first design rule includes: a width value of a target object in the integrated circuit, the second check term of the second design rule comprising: a distance value between target objects in the integrated circuit. Illustratively, the first check term is a width value of the semiconductor structure, and the second check term is a distance value of the semiconductor structure from the through hole.

In an alternative embodiment of the present application, the first check item of the first design rule includes: a positional relationship between target objects in the integrated circuit, the second check term of the second design rule including: a width value of a target object in an integrated circuit. Illustratively, the first check term is a positional relationship between the semiconductor structures, and the second check term is a width value of the semiconductor structures.

In an alternative embodiment of the present application, the first check item of the first design rule includes: a value of an area of a target object in the integrated circuit, the second check term of the second design rule comprising: a width value of a target object in an integrated circuit. Illustratively, the first check term is an area value of the semiconductor structure occupying the chip region, and the second check term is a width value of the semiconductor structure.

It should be noted that any two design rules with association relationship belong to the protection scope of the embodiments of the present application, and since all possible examples cannot be exhausted, the description of the solutions is only performed by the above-mentioned several embodiments.

Step 202, verifying whether the configuration file meets the first design rule to obtain a second verification result.

And step 203, verifying whether the configuration file meets the second design rule to obtain a third verification result.

In one possible implementation, if the second verification result indicates that the configuration file satisfies the first design rule, it is further verified whether the configuration file satisfies the second design rule.

In a possible implementation, if the second verification result indicates that the configuration file does not satisfy the first design rule, it is further verified whether the configuration file satisfies the second design rule.

From the above implementation manner, whether the configuration file satisfies the first design rule or not, it is necessary to further verify whether the configuration file satisfies the second design rule or not, so as to ensure the comprehensiveness of rule detection and reduce missed detection or false detection.

Optionally, in some embodiments, step 203 may be executed first, and then step 202 is executed, or step 202 and step 203 are executed simultaneously, which is not limited in this embodiment.

And step 204, determining a first verification result according to the second verification result and the third verification result.

In a possible implementation manner, if the first verification result and the second verification result both indicate that the test pattern is valid, the first verification result is used to indicate that the test pattern is valid.

In one possible implementation manner, if at least one of the first verification result and the second verification result indicates that the test pattern is invalid, the first verification result is used to indicate that the test pattern is invalid.

Step 205, outputting a first verification result, where the first verification result is used to indicate whether the test pattern is valid.

In the verification method for the test pattern shown in this embodiment, the DRM file is used to obtain the first design rule and the second design rule of the inspection area where the test pattern is located, and respectively verify whether the configuration file meets the first design rule and the second design rule to obtain the second verification result and the third verification result, and after the verification results are comprehensively analyzed, the final first verification result is output to indicate whether the test pattern is valid. The verification process is that the configuration file is verified before the configuration file is executed, and the test pattern is judged to be invalid as long as one item is found not to meet the requirement of the standard design rule, so that the efficiency and the accuracy of the verification of the test pattern can be improved.

The following embodiment shows a specific example, and the technical solution of the embodiment can be understood by referring to fig. 3 to 5.

Based on the embodiment shown in fig. 2, in this embodiment, the first design rule includes a rule for defining a distance value between target objects in the inspection area where the test pattern is located, and the second design rule includes a rule for defining a width value of the target objects in the inspection area where the test pattern is located.

Fig. 3 is a schematic diagram of check items of the first design rule and the second design rule provided in an embodiment of the present application. Fig. 4 is a first schematic diagram of an invalid test pattern provided in an embodiment of the present application. Fig. 5 is a second schematic diagram of an invalid test pattern provided in the embodiment of the present application. Fig. 6 is a schematic diagram of an effective test pattern provided in an embodiment of the present application.

As shown in fig. 3, the first design rule in this embodiment defines at least a distance value S between Poly tap and contact in a certain inspection area of the integrated circuit. Illustratively, as shown in table 2, the design rule CT _ S _01 defines a distance value S between Poly tap and contact in the SA area of the integrated circuit to be greater than or equal to 0.3 μm, provided that: the length of the overlap of Poly tap and contact in a specified direction (e.g., horizontal direction) is less than half of the width of contact in the specified direction.

As shown in fig. 3, the second design rule in the present embodiment defines at least the width value of the contact short side direction in the same inspection area in the integrated circuit. Illustratively, as shown in table 3, the design rule CT _ W _01 defines that the width W of a contact in the SA area in the integrated circuit in the short side direction is equal to 0.16 μm.

It should be understood that the width value of the contact in the short side direction in the design rule CT _ W _01 has an association relationship with the design rule CT _ S _01, for example, if the width value of the contact in the short side direction is too large, which may result in that the overlap length of the Poly tap and the contact in the specified direction is greater than half of the width value of the contact in the specified direction, even if the distance value S between the Poly tap and the contact is greater than or equal to 0.3 μm, it will be determined that the test pattern does not satisfy either the design rule CT _ S _01 or the design rule CT _ W _ 01.

The test patterns shown in fig. 4 to 6 all belong to the test pattern of the SA area, and the standard design rule of the SA area is obtained from the DRM file, including the first design rule and the second design rule. As can be seen from analyzing the DRM file, the distance between the Poly tap and the contact of the first design rule limited SA area should be greater than or equal to 0.3 μm, and the width of the contact of the second design rule limited SA area in the short side direction should be equal to 0.16 μm.

By verifying the configuration file of the test pattern shown in fig. 4, it can be determined that the configuration file satisfies the first design rule but does not satisfy the second design rule, and thus the verification result of the configuration file is used to indicate that the test pattern shown in fig. 4 is invalid.

By verifying the configuration file of the test pattern shown in fig. 5, it can be determined that the configuration file does not satisfy the first design rule but satisfies the second design rule, and thus the verification result of the configuration file is used to indicate that the test pattern shown in fig. 5 is invalid.

By verifying the configuration file of the test pattern shown in fig. 6, it can be determined that the configuration file satisfies both the first design rule and the second design rule, and thus the verification result of the configuration file is used to indicate that the test pattern shown in fig. 6 is valid. Further, a test pattern is generated by executing the configuration file, and the test pattern is stored in an effective test pattern library.

In the verification method for the test pattern shown in the above embodiment, whether the configuration file of the test pattern satisfies the distance-based design rule and the width-based design rule is verified, and the two design rules have an association relationship. Only if the configuration file meets the two design rules at the same time, the test pattern corresponding to the configuration file is regarded as a valid test pattern. The verification process is that the configuration file is verified before the configuration file is executed, and the test pattern is judged to be invalid as long as one item is found not to meet the requirement of the standard design rule, so that the efficiency and the accuracy of the verification of the test pattern can be improved.

In the embodiment of the present application, the functional modules of the verification apparatus for test patterns may be divided according to the method embodiments, for example, each functional module may be divided corresponding to each function, or two or more functions may be integrated into one processing module. The integrated module can be realized in a form of hardware or a form of a software functional module. It should be noted that, in the embodiment of the present application, the division of the module is schematic, and is only one logic function division, and there may be another division manner in actual implementation. The following description will be given by taking an example in which each functional module is divided by using a corresponding function.

Fig. 7 is a first schematic structural diagram of a verification apparatus for a test pattern according to an embodiment of the present application. As shown in fig. 7, the verification apparatus 300 for test patterns of the present embodiment includes: an acquisition module 301, a processing module 302 and an output module 303.

An obtaining module 301, configured to obtain a configuration file of a test pattern, where the configuration file includes multiple constraint conditions configured for the test pattern;

the processing module 302 is configured to verify whether the configuration file meets the requirement of the design rule, so as to obtain a first verification result; the design rule requirements include rules for defining a range of values for each of the check terms in different check regions of the integrated circuit;

an output module 303, configured to output the first verification result, where the first verification result is used to indicate whether the test pattern is valid.

In an optional embodiment of the present application, the obtaining module 301 is further configured to:

the processing module is specifically configured to:

In an optional embodiment of the present application, the processing module 302 is specifically configured to:

In an optional embodiment of the application, if the first verification result is used to indicate that the test pattern is invalid, and the first verification result includes location information of an error field in the configuration file, the processing module 302 is further configured to:

Fig. 8 is a second schematic structural diagram of a verification apparatus for a test pattern according to an embodiment of the present application. On the basis of the apparatus shown in fig. 7, as shown in fig. 8, the verification apparatus 300 for test patterns of the present embodiment further includes: a storage module 304.

In an optional embodiment of the application, if the first verification result is used to indicate that the test pattern is valid, the processing module 302 is further configured to:

the storage module 304 is configured to store the test pattern in an effective test pattern library.

The verification apparatus for a test pattern provided in the embodiment of the present application is configured to perform each step of the foregoing method embodiment, and the implementation principle and the technical effect are similar, which are not described herein again.

Fig. 9 is a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present application. As shown in fig. 9, the electronic device 400 of the present embodiment includes:

at least one processor 401 (only one processor is shown in FIG. 9); and

a memory 402 communicatively coupled to the at least one processor; wherein the content of the first and second substances,

the memory 402 stores instructions executable by the at least one processor 401 to enable the electronic device 400 to perform the steps of any of the method embodiments described above, when the instructions are executed by the at least one processor 401.

Optionally, the memory 402 may be separate or integrated with the processor 401.

When the memory 402 is a separate device from the processor 401, the electronic device 400 further comprises: a bus 403 for connecting the memory 402 and the processor 401.

Embodiments of the present application further provide a computer-readable storage medium, in which computer-executable instructions are stored, and when the computer-executable instructions are executed by a processor, the steps of any one of the foregoing method embodiments are implemented.

The present application provides a computer program product comprising a computer program that, when executed by a processor, performs the steps of any of the method embodiments described above.

An embodiment of the present application further provides a chip, including: a processing module and a communication interface, wherein the processing module can execute the technical scheme in any one of the method embodiments.

Further, the chip further includes a storage module (e.g., a memory), where the storage module is configured to store instructions, and the processing module is configured to execute the instructions stored in the storage module, and the execution of the instructions stored in the storage module causes the processing module to execute the technical solution in any one of the foregoing method embodiments.

It should be understood that the Processor mentioned in the embodiments of the present Application may be a Central Processing Unit (CPU), and may also be other general purpose processors, Digital Signal Processors (DSP), Application Specific Integrated Circuits (ASIC), Field Programmable Gate Arrays (FPGA) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, and the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

It will also be appreciated that the memory referred to in the embodiments of the application may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The non-volatile Memory may be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable PROM (EEPROM), or a flash Memory. Volatile Memory can be Random Access Memory (RAM), which acts as external cache Memory. By way of example, but not limitation, many forms of RAM are available, such as Static random access memory (Static RAM, SRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic random access memory (Synchronous DRAM, SDRAM), Double Data Rate Synchronous Dynamic random access memory (DDR SDRAM), Enhanced Synchronous SDRAM (ESDRAM), Synchronous link SDRAM (SLDRAM), and Direct Rambus RAM (DR RAM).

The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended ISA (EISA) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, the buses in the figures of the present application are not limited to only one bus or one type of bus.

It should be noted that when the processor is a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, the memory (memory module) is integrated in the processor.

It should be noted that the memory described herein is intended to comprise, without being limited to, these and any other suitable types of memory.

It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A verification method for a test pattern, comprising:

2. The method of claim 1, wherein verifying whether the configuration file meets the design rule requirement, resulting in a first verification result, comprises:

3. The method of claim 2, wherein determining the first verification result based on the second verification result and the second verification result comprises:

4. The method according to any of claims 1-3, wherein if the first verification result is used to indicate that the test pattern is invalid, the first verification result includes location information of an error field in the configuration file, the method further comprising:

5. The method according to any of claims 1-3, wherein if the first verification result indicates that the test pattern is valid, the method further comprises:

and storing the test pattern into an effective test pattern library.

6. The method according to claim 2 or 3, wherein the first check item comprises: a value of a distance between target objects in the integrated circuit, the second check term comprising: a positional relationship between target objects in the integrated circuit, the target objects including at least one of semiconductor structures, vias.

7. An apparatus for verifying a test pattern, comprising:

8. The apparatus of claim 7, wherein the obtaining module is further configured to:

the processing module is specifically configured to:

9. The apparatus of claim 8, wherein the processing module is specifically configured to:

10. The apparatus according to any of claims 7-9, wherein if the first verification result is used to indicate that the test pattern is invalid, the first verification result includes location information of an error field in the configuration file, and the processing module is further configured to:

11. The apparatus according to any one of claims 7-9, further comprising: a storage module; if the first verification result is used to indicate that the test pattern is valid, the processing module is further configured to:

12. The apparatus according to claim 8 or 9, wherein the first check item comprises: a value of a distance between target objects in the integrated circuit, the second check term comprising: a positional relationship between target objects in the integrated circuit, the target objects including at least one of semiconductor structures, vias.

13. An electronic device, comprising:

at least one processor; and

the memory stores instructions executable by the at least one processor to enable the electronic device to perform the method of any of claims 1-6.

14. A computer-readable storage medium having computer-executable instructions stored therein, which when executed by a processor, enable the processor to perform the method of any one of claims 1-6.

15. A computer program product comprising a computer program, characterized in that the computer program realizes the method of any of claims 1-6 when executed by a processor.