JP2008204371A - Logic verification support system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a logic verification support system for detecting an inconsistent place in a state transition graph of a logic circuit, for storing a temporarily detected inconsistent place in a storage area, and for clearly describing even a state which should not exist as an operation as a verification item. <P>SOLUTION: This logic verification support system for preparing verification items for verifying a logic circuit has an inconsistency extraction means for, when transition conditions shown by state transition information showing transition from a transition source state to a transition destination state are included in the transition conditions of the other state transition information, extracting it as an inconsistent place for each state information showing the logic circuit in the operation of the logic circuit. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention not only detects inconsistent portions in the state transition graph of the logic circuit, but also stores the inconsistent portions once detected in the storage area, and also checks the states that should not exist as operations as verification items. It relates to a logic verification support system that is explicitly described.

  In the conventional logic circuit logic verification method, as shown in FIG. 1, a verification engineer 2 that verifies a logic circuit reads and understands the contents of the specification 1 written in a natural language, and inputs it to the logic circuit. The verification item 3 was created in a tabular form in which the expected value of the operation for the above was described in a natural language. In FIG. 1, A and B indicate types of input data to the logic circuit, and (α) and (β) indicate processing contents of the logic circuit.

For example, the verification engineer 2 understands a description such as “(α) process when A is input, (β) process when B is input” in the specification 1, and “A is used as a circuit input. When “simulation” is performed, “confirmation that processing of (α) has been performed” is performed, and when “logic simulation is performed using B as a circuit input”, “confirmation that processing of (β) is performed” is performed. A list of verification items describing the above was created.
JP-A-8-110907 JP-A-8-29284

  In the conventional logic verification method of the logic circuit as described above, the verification engineer 2 determines “what verification should be performed” based on experience and writes the verification items manually. In such a case, given the specification 1 in a document written in a natural language or the like, the verification engineer 2 will, for example, consider all combinations that take into account the case where A and B are input in any possible order. Judgment as to whether or not sufficient consideration has been made depends on the experience of the verification engineer 2, and it was not easy to confirm whether or not the examination was sufficient. In the process, when the verification engineer 2 finds a contradiction based on experience, the verification engineer 2 performs a predetermined procedure for correction and checks the corrected specification 1 again.

  As a result, in the extraction of contradiction based on such experience and the extraction of verification items, the verification work is completed without extracting the items to be verified, which is caused by the lack of verification items at the logic circuit provider. In some cases, a logic failure occurred.

  Therefore, the object of the present invention is not only to detect inconsistent portions in the state transition graph of the logic circuit, but also to keep the detected inconsistent portions in the storage area and should not exist as an operation. Is to provide a logic verification support system that is explicitly described as a verification item.

  In order to solve the above problems, the present invention provides a logic verification support system for creating a verification item for verifying a logic circuit, wherein a transition is made for each status information indicating the status of the logic circuit in the operation of the logic circuit. When the transition condition indicated by the state transition information indicating the transition from the original state to the transition destination state is included in the transition condition of the other state transition information, it is configured to have a contradiction extraction means for extracting as a contradiction part.

  A program for causing a computer to execute the above means as a function, a computer-readable storage medium storing the program, and a method for the computer to process the above means as a function can be used.

  The present invention not only detects the contradictory part in the state transition graph of the logic circuit, but also stores the contradictory part once detected in the storage area, and also verifies the state that should not exist as an operation. It can be described explicitly.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 2 is a diagram illustrating a functional configuration of the logic verification system according to the embodiment of the present invention. In FIG. 2, the logic verification system 100 includes a specification description creation unit 10, a detection item extraction unit 30, a test data creation unit 80, and a logic simulator 90.

  The logic verification system 100 may be realized by one computer device, or may be realized by two or three computer devices. The entire detection item extraction unit 30 is preferably operated by one computer device. When implemented by a plurality of computer devices, the data created by the processing units 10, 30, 80 and 90 may be stored in an external storage medium and read by the processing units as necessary. Alternatively, a configuration is possible in which a plurality of computer devices can be connected to each other via a network or the like.

  The specification description creating unit 10 is a content that the verification engineer 2 inputs the input data to the logic circuit and the function (state transition, etc.) of the logic circuit in a predetermined description format based on the logic circuit specification or standard. To create specification description data 10a.

  The verification item extraction unit 30 is a processing unit that extracts verification items using the specification description data 10a created by the specification description creation unit 10 and creates verification item information 37a. It has a transition graph creation unit 32, a contradiction extraction unit 34, and a verification item creation unit 37.

  The specification description analysis unit 31 reads and analyzes the specification description data 10a, generates a state list 30a and input data 30b based on the specification description data 10a, and stores them in the storage area.

  The state transition graph creation unit 32 creates a state structure 32a indicating a state and a link structure 23b indicating a state transition by using the state list 30a and the input data 30b, and the state structure 32a and the link structure. State transition graph data representing the function of the logic circuit is created based on the field 23b. In addition, the state transition graph creation unit 32 adds the “not used” mark (×) to the state transition portion that is no longer used by the specification engineer 2 correcting the specification description data 10a, and the state transition graph data. Update.

  The contradiction extraction unit 34 is a processing unit that analyzes whether there is a contradiction in the state transition of the logic circuit based on the specification description data 10a, and the contradiction information creation unit 35 that creates the contradiction information structure 34a when there is a contradiction. Have. The contradiction extraction unit 34 analyzes whether there is a logical contradiction from the state transition graph data 32a created by the state transition graph creation unit 32, and if a contradiction is detected, the contradiction of the state transition is indicated by the specification contradiction item information 34a. A specification contradiction item file 34f is created and output to the storage area, and the verification engineer 2 is notified that a contradiction exists.

  The verification engineer 2 analyzes the specification contradiction item file 34f, causes the specification description creation unit 10 to execute, and corrects and updates the specification description data 10a.

  The verification item creation unit 37 creates a verification item structure 37a indicating an item to be verified, and outputs a verification item that explicitly describes whether or not processing can be performed based on the verification item structure 37a to the verification item file 37f. And a contradiction part verification item creation part 38 and an edge part verification item creation part 39.

  The verification item creation unit 37 uses the contradiction information structure 34a to create a verification item that explicitly expresses whether or not the process can be executed for the state transition portion to which the “not used” mark (×) is added. In order to determine whether it is necessary or not and to write out the state transition part to which the “not used” mark (×) is added as a verification item that explicitly states “do not execute the process”, “do not execute the process” "Flag (black circle) is set in the contradiction information structure 34a. When it is not necessary to create a verification item that explicitly expresses whether or not the process can be executed, the verification item creation unit 37a does not create a verification item based on the “not used” mark (×).

  Further, the verification item creation unit 37 creates a verification item structure 37a based on the contents of the state structure 32a for the state structure 32a without the “not used” mark (×). In this case, the verification item creation unit 37 does not add the “do not execute processing” flag (black circle). Alternatively, a flag “execute processing” may be added.

  The verification item creation unit 37 further creates a verification item structure 37a by each of the contradiction part verification item creation unit 38 and the edge part verification item creation unit 39, and the verification item structure 37a is used as a verification item. Are output to the verification item file 37f.

  The contradiction part verification item creation unit 38 creates the verification item structure 37a of the conflicting part using the contradiction information structure 37a, and outputs the verification item to the verification item file 37f based on the verification item structure 37a. To do.

  The edge part verification item creation unit 39 creates a verification item structure 37a other than the contradiction information structure 37a by using the state structure 32a, and adds a verification item to the verification item file 37f based on the verification item structure 37a. Output to.

  The test data creation unit 80 is a processing unit that supports creation of a test bench and a test pattern by the verification engineer 2 using the verification item information 37a created by the verification item extraction unit 30, and is used for simulating a circuit. Various test data 80a is output to the storage area.

  The logic simulator 90 is a processing unit that reads the test data 80a created by the test data creation unit 80 and executes a simulation for verifying the designed circuit.

  One to three computer apparatuses that implement the logic verification support system 100 have a hardware configuration as shown in FIG. FIG. 3 is a diagram illustrating a hardware configuration of a computer device that implements a logic verification support system according to an embodiment of the present invention.

  In FIG. 3, a logic verification support system 100 is a device controlled by a computer, and includes a CPU (Central Processing Unit) 11, a memory unit 12, a display unit 13, an output unit 14, an input unit 15, The communication unit 16, the storage device 17, and the driver 18 are configured and connected to the system bus B.

  The CPU 11 controls the logic verification support system 100 according to a program stored in the memory unit 12. The memory unit 12 includes a RAM (Random Access Memory), a ROM (Read-Only Memory), and the like, and is obtained by a program executed by the CPU 11, data necessary for processing by the CPU 11, and processing by the CPU 11. Stored data. A part of the memory unit 12 is allocated as a work area used for processing by the CPU 11.

  The display unit 13 displays various information required under the control of the CPU 11. The output unit 14 has a printer or the like, and is used for outputting various types of information in accordance with instructions from the user. The input unit 15 includes a mouse, a keyboard, and the like, and is used for a user to input various information necessary for the logic verification support system 100 to perform processing.

  The communication unit 16 is a device for the logic verification support system 100 to control communication via a network such as the Internet or a LAN (Local Area Network).

  The storage device 17 is composed of, for example, a hard disk unit, and stores data such as programs for executing various processes.

  A program that realizes processing in the circuit design method performed by the logic verification support system 100 is provided to the logic verification support system 100 by a storage medium 19 such as a CD-ROM (Compact Disk Read-Only Memory). That is, when the storage medium 19 storing the program is set in the driver 18, the driver 18 reads the program from the storage medium 19, and the read program is installed in the storage device 17 via the system bus B. . When the program is activated, the CPU 11 starts its processing according to the program installed in the storage device 17.

  The medium for storing the program is not limited to a CD-ROM, and any medium that can be read by a computer is acceptable. The program for realizing the processing according to the present invention may be downloaded via the network by the communication unit 16 and installed in the storage device 17. When the logic verification support system 100 has an interface such as a USB (Universal Serial Bus) for connecting to the outside, the program may be read from an external storage medium by USB connection.

  Next, an example of the specification description data 10a that the specification description creating unit 10 creates from the data input by the verification engineer 2 will be described with reference to FIG. FIG. 4 is a diagram illustrating an example of specification description data.

  In FIG. 4, the specification description data 10a includes an input data definition unit 10a-2 and a processing content definition unit 10a-4.

  The data definition unit 10a-2 shows the valid range of input data. In this case, “0x00” to “0xff” indicating that 1-byte data is input is defined as a valid data range.

  Also, by defining the input (mark) type that executes special processing or causes processing state transition, the definition of the state for executing special processing, the disclosure condition, the end condition, and the restrictions on the values that can be input in that state Define. For example, the mark A is defined by the input data “0xfe”, and the mark B is defined by the input data “0xff”. Also, in the state transition definition, it is defined that the disclosure condition for transitioning to “state A” is mark A, the end condition for transitioning from “state A” is mark B, and there is no input value constraint Has been.

  The process content definition unit 10a-4 includes a process to be executed when each data defined by the input data definition unit 10a-2 is input, and a process to be executed by the state transition definition defined by the input data definition unit 10a-2. Is defined. In this case, the “normal processing” column indicates that there is a process when the initial state does not match either the mark defined by the “input data definition unit” or the state transitioned by the mark. A plurality of arbitrary values can be written to the right of “:” in each process. In this case, it is defined that the process (α) is executed in the state A and the process (β) is executed by inputting the mark B.

  At this point, the specification description data 10a created in this way may contain inconsistencies. Therefore, the verification engineer 2 can write out items that can be conceived. In the present embodiment, in general, when comprehending a standard or specification, there are many logic faults at a place where misinterpretations are often made. Therefore, the logic verification support system 100 accepts contradictory declarations and is described below. In this way, the contradiction is pointed out, and all the information of the contradictory part in the specification is saved as a point to be noted in the logic verification.

  The specification description data 10a is analyzed by the specification description analysis unit 31, and is divided into a state list 31a and an input data list 31b and stored in the storage area. In the state list 31a, for example, state names such as “normal state” and “state A” as initial states, and conditions for state transition (hereinafter referred to as state transition conditions) are defined in the state transition definition. , Content defined in the processing content definition section. The input data list 31b includes valid data, a mark name, and a value recognized as a mark.

  Then, the state transition graph creation unit 32 creates a state structure 32a and a link structure 32b. FIG. 5 is a flowchart for explaining the state transition graph creation processing. In FIG. 5, the state transition graph creating unit 32 refers to the state list 31a and creates a structure indicating the state for each state as a state structure 32a in the storage area (step S131). In this case, if the state structure 32a has already been created due to specification correction or the like, the existing state structure 32a is adopted and stored in another storage area.

  The state transition graph creation unit 32 refers to the input data list 31b and creates a structure indicating a state transition for each state transition condition as a link structure 32b (step S132). The transition condition and the process name indicating the process to be executed are set in the link structure 32b, and the state structure of the transition source and the transition destination is connected with a pointer (step S133).

  In addition, the state transition graph creating unit 32 adds a “not used” mark (×) to the state structure and link structure that no longer exist due to the specification modification, and stores them in the storage area as they are (step S134). . The state structure that no longer exists is acquired by the difference between the state structure 32a stored in the storage area from the previous time and the state structure 32a adopted this time, and the difference is not used for the state structure 32a. "(X)" and a state structure 32a adopted this time may be stored in the storage area. The same applies to link structures that no longer exist. The “not used” mark (×) may be provided as an element in the state structure 32a and the link structure 32b, and information indicating “not used” may be set.

  Next, the contradiction information structure 34 a and the use contradiction item file 34 f are created by the contradiction extraction unit 34. FIG. 6 is a flowchart for explaining the contradiction extraction process.

  In FIG. 6, the contradiction extraction unit 34 sequentially reads one state structure 32 a created by the state transition graph creation unit 32 from the storage area, refers to the input data list 31 a, and connects the state structure 32 a to the connection source. As for the link structure 32b connected as, it is confirmed whether or not the link structure 32b having the transition condition including the transition condition of the link structure 32b is already stored in the storage area (step S141). For example, it is only necessary to check whether the transition conditions “other than mark A (other than 0xfe)” and “mark B (0xff)” are link structures 32b that are not mutually exclusive.

  In step S141, the state structure 32a and the link structure 32b are checked including those to which “not used” mark (×) is given due to the specification correction.

  When the same transition condition does not exist (NO in step S142), the contradiction extraction unit 34 refers to the input data list 31a and a pointer to the state structure 32a and a link connected to the state structure as a connection source The value set in the transition condition of the structure 32b and the pointer to the related link structure 32b are stored in the storage area (step S143).

  On the other hand, if the same transition condition exists (YES in step S142), the contradiction extraction unit 34 creates a pointer to the state structure 32a being processed, a pointer to the link structure 32b associated with an existing value, A contradiction information structure 34a indicating the pointer to the link structure 32b and the contradictory value set is created and saved in the contradiction information storage unit 41 as shown in FIG. 7 (step S142-2). . Further, the contradiction extraction unit 34 stores a pointer to the contradiction information structure 34a in the contradiction information storage unit 41 as shown in FIG. 7 (step S142-4).

  Referring to FIG. 7, the contradiction information storage unit 41 stores a pointer area 41a, a contradiction information structure 34a, and a value set 41s indicating a contradictory transition condition. In the pointer area 41a, pointers to the created contradiction information structure 34a are sequentially stored. The contradiction information structure 34a is the same by referring to the pointer to the state structure 32a where the conflicting link structure 32b exists, the respective pointers of the link structure 32b having the same value, and the input data list 31a. It is composed of elements such as a value set 41s indicating a description of transition conditions as values.

  For example, the transition condition description “other than mark A” and the transition condition description “mark B” have the same value “0xff” by referring to the input data list 31b, and the value set 41s includes “other than mark A”. "And" Mark B "are set.

  A structure in which a “not used” mark (×) is added to the state structure 32a and the link structure 32b that are referenced by the pointer from the contradiction information structure 34a stored in the contradiction information storage unit 41 The body may be present.

  Returning to FIG. 6, the contradiction extraction unit 34 determines whether or not all the state structures 32a have been processed (step S144). If not all have been processed, the contradiction extraction unit 34 returns to step S141 and repeats the same processing as described above.

  On the other hand, when all the processing is performed, the contradiction extraction unit 34 creates a specification contradiction item for each of the contradiction information structures 34a stored in the contradiction information storage unit 41 and outputs it as a specification conflict item file 34f (step S145). ). Then, the contradiction extraction unit 34 notifies the verification engineer 2 of the specification contradiction item file 34f (step S146), and ends the contradiction extraction process.

  The process of creating the state transition graph by the state transition graph creation unit 32, the contradiction extraction unit 34, and the process and the process of creating the specification contradiction item file 34f will be described with reference to FIG. FIG. 8 is a diagram illustrating a process up to extraction of contradictory items.

  In FIG. 8, the state transition graph creation unit 32 receives the state list 31a and creates a state in the state transition graph 50 (step S11). Here, the state structure 32a indicating the normal process and the state A as the “state” is created.

  The state transition graph creating unit 32 refers to the input data list 31b and sets an edge indicating “state transition” for each transition condition to the state in the specification description (step S12). An edge indicating “state transition” is indicated by a link structure 32b. In the state transition graph 51, the state transition between the normal processing state and the state A, the state transition in the normal processing state, which is made by the input related to the mark A (the input of the mark A and the input other than the mark A), And a state in which state transitions in state A are added. The state transition graph 52 shows a state where a state transition in the normal processing state and a state transition in the state A, which are made by an input related to the mark B (an input of the mark B), are added.

  Next, the contradiction extraction unit 34 checks whether there is a contradiction between the transition conditions for the transition from each state on the state transition graph 52 created by the state transition graph creation unit 32 (step S13). In the state transition graph 53, inconsistent transition conditions (edges) in the state transition graph 52 created by the state transition graph creating unit 32 are indicated by dotted lines. The state structure 32a and the link structure 32b related to the inconsistent transition condition (edge) are specified by the inconsistency state structure 34a.

  Then, the contradiction extraction unit 34 outputs the contradiction to a file in a predetermined format, notifies the verification engineer 2 and stores it in the logic verification support system 100 (step S14). The specification contradiction item file 34f includes, for example, items of transition source, transition destination, and transition condition for each contradiction point, and values are associated with them.

  For the contradiction 58 shown in the state transition graph 53, the “normal processing” state is set as the transition source, and there is a contradiction between the two edges in the “normal processing” state. It is set repeatedly as in the “normal processing” state, and a value is set for each edge like mark B in addition to mark A in the transition condition. Furthermore, for the contradiction 59 shown in the state transition graph 53, “state A” is set as the transition source, and there is a contradiction between two edges in “state A”. A ”is repeatedly set, and a value is set for each edge like mark B in addition to mark A in the transition condition.

  When the verification engineer 2 corrects the specification description data 10a with reference to such a specification contradiction item file 34f, the above-described processing by the specification description analysis unit 31, the state transition graph creation unit 32, and the contradiction extraction unit 35 is executed. A “not used” mark (×) is added to a portion that has been modified and is not used.

  Further, in the logic verification support system 100, the verification item creation unit 37 creates a verification item file 37f in which the verification items are described. FIG. 9 is a flowchart for explaining the verification item creation processing. In FIG. 9, the verification item creation unit 37 determines the combination of the state structure 32 a and the link structure 32 b that are associated with the pointer stored in the storage area by the state transition graph creation unit 32 in step S <b> 143 of FIG. 6. It acquires sequentially (step S151).

  The verification item creation unit 37 is stored in the contradiction information storage unit 41, the link structure 32b is given a “not used” mark (×), is a part of other transition conditions, and its processing content is It is confirmed that there is no link structure 32b that is different and has the same transition condition (step S152). When the condition of step S152 is satisfied, the verification item creation unit 37 determines that it is necessary to set a “do not execute process” flag indicating that the execution of the process is explicitly described. On the other hand, if the condition of step S152 is not satisfied, the verification item creation unit 37 determines that it is not necessary to set the “do not execute processing” flag.

  Based on the confirmation in step S152, it is determined whether it is necessary to set a “do not execute processing” flag (step S153). If it is determined that it is necessary to set the “do not execute” flag, the verification item creation unit 37 stores the state structure 32 a and the link structure 32 b to which the “do not execute” flag is stored. (Step S153-4), the process proceeds to step S157.

  On the other hand, if it is determined by the confirmation in step S152 that the setting of the “do not execute processing” flag is unnecessary, the verification item creation unit 37 does not satisfy step S152, and the state structure 32a “not use”. It is determined whether or not the combination is set with a "" mark (x) (step S154). In the case of a combination in which the “not used” mark (×) is set in the state structure 32a, the verification item creation unit 37 proceeds to step S157 without creating the verification item structure 37a.

  On the other hand, in the case of a combination in which the “not used” mark (×) is not set in the state structure 32a in step S154, the verification item creation unit 37 does not give the “do not execute processing” flag, The state structure 32a and the link structure 32b are stored in the storage area (step S156).

  The verification item creation unit 37 determines whether all combinations have been processed (step S157). If all the combinations have not been processed, the verification item creation unit 37 returns to step S151 and repeats the same processing as described above. On the other hand, when all the combinations have been processed, the verification item creation unit 37 describes the verification items based on the verification item structure 37a stored in the storage area and outputs the verification items to the verification item file 37f (step S158).

  In order to describe the verification item, the verification item structure 37a is acquired in order from the storage area, the state structure 32a is acquired from the verification item structure 37a, and the state name set in the state structure 32a To get. Further, the link structure 32b is acquired from the verification item structure 37a, and the transition condition set in the link structure 32b and the presence / absence of the “do not execute processing” flag are acquired. If there is a "do not execute" flag depending on the acquired state name, transition condition, and the presence or absence of the "do not execute" flag, "state name: transition condition: logical failure if process execution is detected" If there is no "do not execute process" flag, it is described to mean "state name: transition condition: logical failure if no process execution is detected" and output to the verification item file 37f As a result, the verification item table is created in the verification item file 37f.

  Verification item table creation processing performed by the verification item creation unit 37 will be described with reference to FIGS. 10, 11, and 12. FIG. 10 is a flowchart for explaining an overview of the verification item table creation process. In FIG. 10, the verification item creation unit 37 assigns a value for each process indicated by the state transition graph created by the state transition graph creation unit 32 (step S201). For example, “001” is assigned to the normal process, “010” is assigned to the process (α), and “100” is assigned to the process (β).

  Then, the verification item creation unit 37 selects one unselected “state” in the state transition graph (step S202), and determines whether or not it has been selected (step S203). If there is no unselected “state” and the selection cannot be made, the verification item creation process ends.

  On the other hand, when there is an unselected “state” and it can be selected, an unselected contradiction information structure 34a having the selected “state” as the state structure 32a is acquired from the contradiction information storage unit 41 (step S204). Then, it is determined whether or not the unselected contradiction information structure 34a has been acquired (step S205). If there is no unselected contradiction information structure 34a and cannot be acquired, the verification item creation unit 37 proceeds to step S207.

  On the other hand, if an unselected contradiction information structure 34a exists and can be acquired, the verification item creation unit 37 uses the contradiction information structure 34a described in FIG. A creation process is executed (step S206).

  Then, the verification item creation unit 37 selects one of the unselected edges starting from the “state” selected in step S202 (step S207), and determines whether or not it has been selected (step S208). An edge means a state transition portion from a state to another state or itself in the state transition graph, and is a portion indicated by a link structure 32b. If there is no unselected edge and the selection cannot be made, the verification item creation unit 37 returns to step S202 and repeats the same processing as described above.

  On the other hand, if an unselected edge can be selected, the verification item creation unit 37 executes verification item creation processing for the edge selected in step S207 described in FIG. 12 by the edge part verification item creation unit 39 (step S209). ) The verification item creation unit 37 returns to step S202 and repeats the same processing as described above. In step S209, verification items are created for edges with no contradiction.

  FIG. 11 is a flowchart for explaining verification item creation processing using the contradiction information structure by the contradiction portion verification item creation unit in step S206 of FIG. In FIG. 11, the contradiction part verification item creation unit 38 selects an unselected link structure (A) in order from the link structure 32b pointed to by the contradiction information structure 34a, and the selected link structure (A). Whether one of the transition structures having the same state as the transition source (B) whose transition condition includes the transition condition of the link structure (A) is selected from the link structure (B) (step S221). Is determined (step S222). Even when the transition condition of the link structure (A) matches the transition condition of the link structure (B), the transition condition is included.

  When an unprocessed link structure (B) exists and can be selected, the contradiction part verification item creation unit 38, for the link structure (A), a value assigned to the process and a link structure ( The logical product of the values assigned to the process of B) is calculated (step S223).

  For example, an edge 61p indicated by a dotted line in a state transition graph 61 shown in FIG. 13 described later is one of the inconsistent transition states indicated by the link structure 32b pointed from the contradiction information structure 34a. The edge 61p indicating the state transition from the state A indicates that “the process (β) is executed when the mark B is input in the state A”, and the value “100” is assigned to execute the process (β). It is. The value “011” is obtained by inverting the value “100” at the edge 61p.

  On the other hand, an edge 61q indicating another state transition from the same state A indicates that “when state A is entered, a process (α) is executed when a mark (mark B) other than A is input”. The value “010” is assigned to execute β).

  Accordingly, the logical product of the value “011” and the value “010” is “010”, which is a non-zero value. In that case, it considers as a description object of a verification item.

  The contradiction part verification item creation part 38 determines whether or not the value of the logical product is non-zero (zero) (step S224). When the logical product value is non-zero (zero), the contradiction part verification item creation unit 38 is a link structure (edge) to which the “not used” mark (×) is not added, or “not used”. In the case where the link structure (edge) is added with the “mark” (×) and the “do not execute” flag (black circle), the verification item structure 37a is created and stored in the storage area (step S225). Then, the process proceeds to step S221, and the same processing as described above is repeated. On the other hand, if the value of the logical product is 0 (zero), the contradiction part verification item creation part 38 proceeds to step S221 and repeats the same processing as described above.

  The verification item structure 37a includes elements that specify a combination of the state structure 32a and the link structure 32b that are associated with each other by a pointer. For example, a pointer to the state structure 32a and a pointer to the link structure 32b are set in the verification item structure 37a.

  On the other hand, in step S226, if the unprocessed link structure (B) does not exist and cannot be selected, the contradiction part verification item creation unit 38 verifies based on the verification item structure 37a stored in the storage area. The items are described and output to the verification item file 37f (step S226), and the verification item creation process using the contradiction information structure is terminated. After the verification item is described, the verification item structure 37a stored in the storage area is deleted.

  In step S226, the verification item is written in the following description format, for example. A value acquired from the verification item structure 37f is written in ().

  When the “do not execute process” flag is not added, “input (transition condition) and (process content) when (state name)” is described. On the other hand, when the “do not execute processing” flag is added, “input (transition condition) when (state name), (do not process)” is described. By describing in this way, it is explicitly checked whether to check whether it is processed or not to be processed for the edge in the state transition graph that was originally determined to be inconsistent Can be shown as

  FIG. 12 is a flowchart for explaining verification item creation processing for consistent edges by the edge portion verification item creation unit 39 in step S209 of FIG. In FIG. 12, the edge verification item creation unit 39 is based on the state structure 32a indicating the “state” selected in step S202 of FIG. 10 and the link structure 32b indicating the “edge” selected in step S207. Then, the verification item structure 37f is created and stored in the storage area (step S241).

  The edge verification item creation unit 39 describes the verification items based on the verification item structure 37a stored in the storage area and outputs the verification items to the verification item file 37f (step S243). End the process.

  In step S243, the verification item is written in a description format, for example, “when (state name), (transition condition) input, (processing content)”. A value acquired from the verification item structure 37f is written in ().

  FIG. 13 is a diagram illustrating a description example of verification items created from the state transition graph including contradiction. In FIG. 13, a state transition graph 61 shows a state in which the contradictions 58 and 59 included in the state transition graph 53 of FIG. 8 are corrected by the verification engineer 2. Therefore, in the state transition graph 61, the “not used” mark (×) is given to the edge 61m detected as the contradiction 58 and the edge 61p detected as the contradiction 59. In addition, an edge 61 a is added by the verification engineer 2. Further, the “do not execute processing” flag (black circle) is given to the edge 61 p detected as the contradiction 59 by the verification item creation unit 37.

  Such verification items based on the state transition graph 61 are written in the verification item file 37f. For example, the verification item “input other than mark A and other than mark B during normal processing and normal processing is executed for the edge 61a. ”Is described, the verification item“ execute mark B input and processing (β) during normal processing ”is described for the edge 61n, and the verification item“ mark A input and processing (α) is performed for the edge 61c. ) And transition to the state A ”is described, and the verification item“ execution of input other than the mark A in state A, processing (α) ”is described for the edge 61q. The verification item “in the state A, the mark B input and processing (β) is not executed” is described, and the verification item “in the state A, the mark A input and the processing (α) is executed. Processing "Transition to state" is described.

  Here, the edge 61p is not used due to the modification by the verification engineer 2, but it is explicitly indicated by the description that “the mark B is input and the process (β) is not executed in the state A”. As a result, more reliable verification can be performed.

  As described above, in this embodiment, in general, when understanding the standard and use, logic faults increase in places that are often misinterpreted. Therefore, the logic verification support system 100 has inconsistent specifications. Accept and point out the contradiction, and save all the information of the contradicted part as a point to be noted in the logic verification.

  Even when the specification description data 10a finally having no contradiction is obtained by the verification engineer 2 who has received the indication, in order to generate the state transition graph and the content of the contradiction previously saved, The verification item is described using the state structure 32a, the link structure 32b, and the contradiction information structure 34a.

  The verification engineer creates a test pattern for logic verification based on the verification item file 37f and outputs test data 80a including the test pattern. A logic simulation is executed using the test data 80a, and it is confirmed from the execution result whether the expected operation is consistent with each verification item.

  In the embodiment described above, for example, “C-data structure and program”, Leendert Ammerral, Ohm, 1990, and “Lex” are used for the usage description analysis method (Parser implementation method) and the state transition graph generation. & Yacc ", JRLevine, Oreilly Associates Inc., 1992.

Regarding the above description, the following items are further disclosed.
(Appendix 1)
A logic verification support system for creating a verification item for verifying a logic circuit,
When the transition condition indicated by the state transition information indicating the transition from the transition source state to the transition destination state is included in the transition condition of the other state transition information for each state information indicating the state of the logic circuit in the operation of the logic circuit A logic verification support system having a contradiction extraction means for extracting as a contradiction portion.
(Appendix 2)
The logic verification according to appendix 1, wherein the contradiction extraction means creates a contradiction item using the contradiction information and notifies the verification engineer the state information and the state transition information that have become the contradiction part. Support system.
(Appendix 3)
3. The logic verification support system according to appendix 1 or 2, wherein the contradiction extraction unit stores the state information and the state transition information as the contradiction portion in a contradiction information storage area as contradiction item information.
(Appendix 4)
The logic verification support system according to claim 1, further comprising verification item creation means for creating a verification item using the state information and the state transition information including the contradiction part extracted by the contradiction extraction means. .
(Appendix 5)
In accordance with the specification description data that defines the operation of the logic circuit, the state information and the transition condition information related to the creation of the state transition graph are created, and the state information and the transition condition information that are no longer used due to the modification of the specification description data The logic verification support system according to claim 4, further comprising state transition graph creation means for adding a mark that is not used to and storing the mark without deleting it.
(Appendix 6)
The verification item creation means adds a flag that does not execute the process to the state transition information when it is determined that the process indicated by the state transition information to which the unused mark is added is not executed. The logic verification support system according to appendix 5.
(Appendix 7)
The verification item creation means includes a verification item that explicitly indicates that the process indicated by the state transition information is not executed for the state transition information to which the unused mark and the flag that does not execute the process are added. The logic verification support system according to appendix 6, which is created.
(Appendix 8)
The verification item creation means includes:
First verification item creating means for creating a first verification item to be verified with respect to the contradictory portion using the state information and the state transition information relating to the contradictory portion;
Any one of appendixes 4 to 8, further comprising second verification item creating means for creating a second verification item to be verified using the state information and the state transition information in which the contradiction is not detected. The described logic verification support system.
(Appendix 9)
A logic verification support method for creating a verification item for a computer to verify a logic circuit, the computer comprising:
When the transition condition indicated by the state transition information indicating the transition from the transition source state to the transition destination state is included in the transition condition of the other state transition information for each state information indicating the state of the logic circuit in the operation of the logic circuit A logic verification support method characterized by executing a contradiction extraction procedure for extracting as a contradiction portion.
(Appendix 10)
A program for causing a computer to execute a logic verification support process for creating a verification item for verifying a logic circuit,
When the transition condition indicated by the state transition information indicating the transition from the transition source state to the transition destination state is included in the transition condition of the other state transition information for each state information indicating the state of the logic circuit in the operation of the logic circuit A logic verification support method characterized by executing a contradiction extraction procedure for extracting as a contradiction portion.

It is a figure for demonstrating the conventional verification item creation method. It is a figure which shows the function structure of the logic verification system which concerns on one Example of this invention. It is a figure which shows the hardware constitutions of the computer apparatus which implement | achieves the logic verification assistance system which concerns on one Example of this invention. It is a figure which shows the example of specification description data. It is a flowchart figure for demonstrating a state transition graph creation process. It is a flowchart for demonstrating a contradiction extraction process. It is a figure which shows the example of a contradiction information storage part. It is a figure which shows the process until contradictory item extraction. It is a flowchart figure for demonstrating a verification item creation process. It is a flowchart figure for demonstrating the outline | summary of a verification item table | surface preparation process. FIG. 11 is a flowchart for explaining verification item creation processing using a contradiction information structure by a contradiction portion verification item creation unit in step S206 of FIG. FIG. 11 is a flowchart for explaining a verification item creation process for edges with no contradiction by the edge verification item creation unit 39 in step S209 of FIG. 10. It is a figure which shows the example of a description of the verification item produced from the state transition graph containing a contradiction.

Explanation of symbols

2 Verification Engineer 10 Specification Description Creation Unit 10a Specification Description Data 11 CPU
12 memory unit 13 display unit 14 output unit 15 input unit 16 communication unit 17 storage device 18 driver 19 storage medium 20 LSI
DESCRIPTION OF SYMBOLS 30 Verification item extraction part 31 Specification description analysis part 31a State list 31b Input data list 32 State transition graph creation part 32a State structure 32b Link structure 34 Contradiction extraction part 34f Specification contradiction item file 35 Contradiction information creation part 37 Verification item creation part 37a Verification item structure 37f Verification item file 38 Contradictory part verification item creation part 39 Edge part verification item creation part 80 Test data creation part 80a Test data 90 Logic simulator

Claims (5)

A logic verification support system for creating a verification item for verifying a logic circuit,
When the transition condition indicated by the state transition information indicating the transition from the transition source state to the transition destination state is included in the transition condition of the other state transition information for each state information indicating the state of the logic circuit in the operation of the logic circuit A logic verification support system having a contradiction extraction means for extracting as a contradiction portion.   The logic according to claim 1, wherein the contradiction extraction unit creates a contradiction item using the contradiction information for the state information and the state transition information which are the contradiction part, and notifies a verification engineer of the logic. Verification support system.   2. The logic verification support according to claim 1, further comprising verification item creation means for creating a verification item using the state information and the state transition information including the inconsistency extracted by the contradiction extraction means. system.   According to the specification description data defining the operation of the logic circuit, the state information and the transition condition information relating to the state transition graph creation are created, and the state information and the transition condition information that are no longer used due to the modification of the specification description data 4. The logic verification support system according to claim 3, further comprising state transition graph creation means for adding and saving a mark that is not used for the data without deleting it.   The verification item creation means adds a flag that does not execute processing to the state transition information when it is determined that the processing indicated by the state transition information to which the unused mark is added is not executed. The logic verification support system according to claim 4.

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