JP2007086979A - Test pattern editing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a test pattern by measuring the distance between intended figures or the like so as to be easily obtained with less operations. <P>SOLUTION: In the test pattern editing device for displaying a dimension line from a reference pattern to a target pattern in a layout verification pattern, when a measuring position in the reference pattern is designated, an actual measuring position is selected based on the relative position relation of the designated measuring position in the reference pattern, a shape of the target pattern adjacent to the selected measuring position is acquired, the dimension between the acquired dimension measuring object and the selected measuring position is measured, and the dimension line and dimensional value of the measured dimension are displayed. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit design CAD apparatus, and more particularly to a test pattern editing apparatus.

  Conventionally, in CAD work for designing a semiconductor integrated circuit, when a test pattern for layout verification is created, it is created manually (manually) using a layout editor or the like. The layout verification here is a design process for checking whether or not a mask pattern (layout) created in the design of a semiconductor integrated circuit satisfies a design rule defined in the manufacturing process.

  There are certainly tools that automatically generate test patterns. However, quality and management problems may arise in the test patterns using these tools. In other words, there may be a problem that the expected pattern does not occur and the accuracy is insufficient. Further, in management, there may be a problem that the arrangement state of the generated pattern cannot be controlled as desired, and the arrangement and the hierarchical structure are not easy to manage. If it does so, the process which corrects by hand work (manual) with respect to the test pattern automatically generated with the tool, or inspects for accuracy improvement will arise. Therefore, even in the present situation, a pattern is often created (corrected) manually while using an automatic generation tool.

  By the way, this layout verification has a verification rule. In the verification rule, a command or the like that can be verified by the tool in accordance with the design rule is described. There are tools that automatically create verification rules, but in most cases they are created manually. Moreover, even with the automatic generation tool, it is not possible to create a complete verification rule at present, and manual correction is still necessary.

  A layout verification test pattern is used to check whether the above-described verification rules are correctly created. Regardless of whether the verification rule is automatically created or manually created, there is always a possibility that a mistake will occur. Therefore, it is necessary to check the verification rule and verify the accuracy using a test pattern.

  When creating a test pattern, you can check whether the verification targets such as the width of the figure, the interval between figures, and the overlap are correctly created according to the design rule to be checked and the validation rule that reflects it. Create a pattern. An example of this pattern creation will be given (see FIG. 3). In the interval check between figures, if it is correct that the distance between two figures is A or more, create a basic pattern such as “less than A”, “A exactly”, and “greater than A”. become.

  Further, considering the dependency between figures, the function of the verification tool, the specification of the verification rule description command, etc., between the edges (301, 305 in FIG. 3), between the corner vertices (also 302), the target If the target side is parallel (same 301, 305), if the target side is not parallel (same 303, 304), if it is a 90 ° unit side (same 302), there is a side other than 90 ° There are many possible combinations to check, such as the case (also 303, 304).

  The extent to which test patterns for checking the above combinations should be created is greatly influenced by the specification of the verification tool. However, the basis is a check of the interval value. Even in the above example, the creation of three distance patterns “less than A”, “A just”, and “greater than A” is indispensable to check the dependency between any figures. It is necessary to create without leaking.

  In order to measure the distance between the created figures as a test pattern, a distance measurement function usually mounted in a layout editor or the like is used. However, when there are a large number of objects to be measured like the above test pattern, there is a problem that a lot of time is spent on the coordinate designation work to be performed accurately.

In Patent Document 1, a dimension element is extracted from CAD data, an actual dimension is calculated from the extracted dimension element, and the difference between the calculated actual dimension and the dimension value indicated by the corresponding dimension numerical data is within an allowable error. If not, a dimension chuck method in a CAD system is disclosed in which error information is displayed on the screen display unit. The present invention does not consider the shape of the designated position for selection of the target graphic.
Patent Document 2 discloses a graphic processing apparatus having a function of automatically adding a dimension line by designating a designated figure or area and changing the line type and color. This graphic processing apparatus is intended only for dimension lines.
Patent Document 3 discloses a graphic editing apparatus used when designing a mask pattern of a semiconductor integrated circuit.
Further, Patent Document 4 discloses a static timing analysis means for searching for a critical path of a circuit from transistor connection information.
Japanese Patent No. 2526092 Japanese Patent Laid-Open No. 9-120411 JP-A-8-96159 Japanese Patent Laid-Open No. 8-6988

  It is an object of the present invention to create a test pattern so that the distance between the intended figures can be accurately measured with a small number of operations.

The present invention has been made to achieve the above object. A test pattern editing apparatus according to claim 1 according to the present invention,
A test pattern editing apparatus for displaying a dimension line from a reference graphic to a target graphic in a layout verification pattern,
When the measurement position in the reference figure is specified,
Select the actual measurement position from the relative positional relationship in the reference figure of the specified measurement position,
Get the shape of the nearby target figure from the selected measurement position,
Measure the dimensions of the measurement target determined by the shape of the acquired nearby target figure and the selected measurement position,
A test pattern editing apparatus that displays a dimension line and a dimension value of a measured dimension.

A test pattern editing apparatus according to claim 2 according to the present invention,
2. The test pattern editing apparatus according to claim 1, wherein the adjacent target graphic includes the reference graphic itself.

A test pattern editing apparatus according to claim 3 according to the present invention,
2. The test according to claim 1, wherein the selected measurement position is a side or a corner, and the dimension measurement target determined by the shape of the acquired adjacent target graphic is a side or a corner. This is a pattern editing device.

A test pattern editing apparatus according to claim 4 according to the present invention,
Verification dimension values are entered and stored in advance,
4. The test pattern editing apparatus according to claim 1, wherein the dimension line and the dimension value are displayed by changing the color according to the verification dimension value and the size of the measured dimension. 5. .

A test pattern editing apparatus according to claim 5 according to the present invention,
5. The test pattern editing apparatus according to claim 4, wherein the dimension value and the dimension line are displayed only when the measured dimension value is smaller than a predetermined constant multiple of the verification dimension value.

A test pattern editing method according to claim 6 according to the present invention,
A test pattern editing method for displaying a dimension line from a reference graphic to a target graphic in a layout verification pattern,
When the measurement position in the reference figure is specified,
Select the actual measurement position from the relative positional relationship in the reference figure of the specified measurement position,
Get the shape of the nearby target figure from the selected measurement position,
Measure the dimensions of the acquired dimension measurement target and the selected measurement position,
A test pattern editing method characterized by displaying a dimension line and a dimension value of a measured dimension.

The test pattern editing method according to claim 7 according to the present invention,
The test pattern editing method according to claim 6, wherein the close target graphic includes the reference graphic itself.

The test pattern editing method according to claim 8 according to the present invention includes:
The test pattern editing method according to claim 1, wherein the selected measurement position is a side or a corner, and the acquired dimension measurement target is a side or a corner.

A method of manufacturing a semiconductor device according to claim 9 according to the present invention is as follows.
A method for manufacturing a semiconductor device designed by a CAD device for designing a semiconductor integrated circuit, using the test pattern editing method according to claim 6.

  By utilizing the present invention, it becomes possible to easily measure the distance between the intended figures accurately with a small number of operations. As a result, the man-hours for creating the test pattern can be reduced, and mistakes in creating the test pattern can also be reduced. Further, it becomes possible to visually grasp the magnitude relation of the numerical values related to the dimensions, and it becomes unnecessary to compare the numbers themselves, so that the working efficiency is improved. Furthermore, there are not more than necessary displays of locations to be checked when confirming the test pattern, and the display screen is easy to see.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments according to the invention will be described with reference to the drawings.

<< First Embodiment >>
FIG. 1 is a schematic configuration diagram of a test pattern editing apparatus 1 according to the first embodiment of the present invention. The test pattern editing device 1 according to the present invention is one of semiconductor integrated circuit design CAD devices, and the semiconductor integrated circuit design CAD device is usually composed of a computer and its peripheral devices. Therefore, the test pattern editing apparatus 1 according to the present invention is also composed of a general computer and its peripheral devices.

  That is, the test pattern editing device 1 includes a processing device 2 that performs test pattern editing processing, a display device 10 that displays CAD data including the test pattern, a storage device 8 that stores data related to the test pattern, and inputs of numerical values and the like. And a pointing device 6 for inputting a command for graphic designating operation and inputting an instruction by GUI. Here, the input means 4 may be a keyboard, for example. The pointing device 6 may be a mouse, a tablet, or a trackball.

  FIG. 2 is a flowchart of the dimension measurement process in the test pattern editing apparatus 1 according to the first embodiment of the present invention. Note that the test pattern graphic editing is performed using a conventional layout editor or the like. Therefore, the following description will be given specifically for the test pattern dimension measurement processing.

  First, verification dimension values are input (S02). It is input from the input means 4 to the processing device 2 by the operation of the operator.

  Next, the measurement position in the reference graphic is designated (S04). Here, FIG. 3 shows an example of a layout in which a rectangle in the center is a reference graphic. For example, in the reference graphic shown in FIG. 3, any of 311, 312, 313, 314, and 315 can be a measurement position to be designated. The designation is performed using the pointing device 6 or the input unit 4 by the operation of the operator.

  Next, it is identified from the relative positional relationship of the designated measurement position in the reference graphic whether the designated intention is directed to the side or the corner (corner) (S06). As the identification standard, the closest one of the sides and corners closest to the designated position is selected and set as the selected measurement position.

  Next, an adjacent figure is searched from the selected measurement position in the reference figure (S08). The search range is the display range of the screen of the display device 10 of the test pattern editing device 1. That is, if a part of a figure is included in the screen, it is a search target.

  Next, the shape of the target graphic obtained by the search in S08 is recognized (S10). Here, if the selected measurement position in S06 is “side”, the dimension measurement target is the side or corner in the target graphic in the region translated by the width of the side. If the selected measurement position in S06 is “corner”, the target of dimension measurement is the nearest corner or side in the target graphic. However, the object of dimension measurement may be limited depending on the relationship between the reference graphic and the target graphic.

  Next, the dimensions of the selected measurement position obtained in S06 and the dimension measurement target obtained in S10 are measured (S12). Here, in the case of a line between sides, if it is a parallel line, the distance between both becomes a dimension. If it is not a parallel line, the closest distance between them is the dimension. In the case of between the side and the point, the distance closest to the side as seen from the position of the point is the dimension.

  Next, the measured dimension value is compared with the verification dimension value (set in S02) (S14). If the measured dimension value is less than twice the verification dimension value, the measured dimension value is measured on the display device 10. The measured dimension value is displayed (S16). At this time, a dimension line is displayed between the selected measurement position obtained in S06 and the dimension measurement target obtained in S10. The dimension value is preferably displayed in the vicinity of the dimension line. If the measured dimension value is twice or more the verification dimension value, nothing is displayed. The magnification of “2 times” here may be another number.

In S16, when the dimension line crosses another figure (including the reference figure specified in S04), the dimension value and the dimension line may not be displayed in consideration of the visibility. Furthermore, in S16, the dimension value and the dimension line may be displayed by changing the display color separately in the following cases (1), (2), and (3).
(1) The measured dimension value is smaller than the verification dimension value.
(2) When the measured dimension value is equal to the verification dimension value.
(3) The measured dimension value is larger than the verification dimension value.

  Further, it is confirmed whether or not there is a target graphic (S18). If there is, the processes of S10 to S16 are performed for the target graphic. If not, the entire process ends.

  Subsequently, the operation of the dimension measurement process in the test pattern editing apparatus 1 according to the first embodiment of the present invention will be described with some graphic examples.

  First, FIG. 3 is taken up. In FIG. 3, a plurality of figures are arranged without overlapping. In FIG. 3, the dimension between the central reference graphic and another graphic is displayed.

  When the designated measurement position (see FIG. 2, S04) is the location “311” (the middle of the side), the selected measurement position (see FIG. 2, S06) is a side. Accordingly, the measurement targets (see FIG. 2, S12) are “301” and “305”, and the dimension line and the dimension value are displayed for these. When the designated measurement position is “315”, it is determined that it is near the end of the side but closer to the side than the corner (see FIG. 2 06), and the selected measurement position is also a side. Accordingly, the measurement target, the dimension line to be displayed, and the dimension value are the same as in the case of “311”.

  In FIG. 3, when the designated measurement position is “312” (near the corner), the selected measurement position is a corner. Accordingly, the measurement targets are two corners indicated by “302”, and a dimension line and a dimension value are displayed for these corners. At this time, the corner indicated by “316” is certainly likely to be the target in FIG. 2 and S10, but is not displayed because the dimension line crosses another figure (see FIG. 2 and S16). There are many other dimension lines that are not displayed because they cross another figure, but the description is omitted.

  Further, in FIG. 3, when the designated measurement position is “313”, the selected measurement position is a side, and the measurement target is a corner. When the designated measurement position is “314”, the selected measurement position is a corner, and the measurement target is a side.

  Next, FIG. 4 will be taken up. In FIG. 4, the width of the figure is displayed.

  When measuring the width of a figure, the same processing is performed except that the object to be measured is the same figure compared to the case of measuring the dimension between the reference figure and another figure as shown in FIG. It becomes. However, even if the designated measurement position is in the vicinity of the corner, the selected measurement position is the closest side and does not become a corner.

  In FIG. 4, when the designated measurement position is “411”, the dimension lines and dimension values “401”, “402”, and “403” are displayed as a result. When the designated measurement position is “414”, the dimension lines and dimension values “404” and “405” are displayed as a result.

  Next, FIG. 5 is taken up. In FIG. 5, two figures are arranged so as to overlap (overlap).

  When measuring the dimension of the interval between overlapping figures, the process is almost the same as when measuring the dimension between the reference figure and another figure as shown in FIG. Is different in that it is only a figure that overlaps the reference figure (see FIG. 2, S04).

  In FIG. 5, when the designated measurement position is “511”, the selected measurement position is a side, the measurement target is “501”, and a dimension line and a dimension value are displayed. When the designated measurement position is “513”, the selected measurement position is a side, the measurement target is “503”, and a dimension line and a dimension value are displayed. Further, when the designated measurement position is “512”, the selected measurement position is a corner, the measurement target is “502”, and a dimension line and a dimension value are displayed.

  Next, FIG. 6 will be taken up. FIG. 6 can be said to be a comprehensive view of FIGS. When the designated measurement position is “611”, the selected measurement position is a side, and the measurement targets are “601”, “602”, “603”, “604”, “605”, and “ 606 ", and the dimension line and the dimension value are displayed for these.

  Incidentally, in FIG. 3, it is assumed that the verification dimension value (see FIG. 2, S02) is the same as the dimension of “301”. At this time, when the location “311” is designated as the measurement position (see S04 in FIG. 2) and the dimension lines and dimension values “301” and “305” are displayed, the dimension “301” is the verification dimension value. They may be displayed in a color indicating that they are the same, and may be displayed in a color indicating that the dimension of “305” is larger than the verification dimension value.

  By doing so, since the magnitude relationship between the numerical values of the dimensions can be visually grasped, work efficiency is improved.

  In FIG. 4, the verification dimension value (see FIG. 2, S02) is “A”, the dimension values of “401” and “403” are smaller than “A × 2”, and the dimension value of “402” is “A”. It is assumed that it is larger than “× 2”. At this time, the dimension value and the dimension line may be displayed for “401” and “403”, and the dimension value and the dimension line may not be displayed for “402”. By doing so, it is possible to reduce the display of locations to be checked when confirming the test pattern and to make the screen display easier to see.

  In addition, by preparing commands with limited functions for each object to be measured, such as the interval, width, and overlap, it is possible to suppress the display of many dimension lines and eliminate the difficulty of viewing.

1 is a schematic configuration diagram of a test pattern editing apparatus according to a first embodiment of the present invention. It is a flowchart of the dimension measurement process in the test pattern editing apparatus which concerns on the 1st Embodiment of this invention. It is a figure for demonstrating operation | movement of the dimension measurement process in the test pattern editing apparatus which concerns on the 1st Embodiment of this invention. It is a figure for demonstrating operation | movement of the dimension measurement process in the test pattern editing apparatus which concerns on the 1st Embodiment of this invention. It is a figure for demonstrating operation | movement of the dimension measurement process in the test pattern editing apparatus which concerns on the 1st Embodiment of this invention. It is a figure for demonstrating operation | movement of the dimension measurement process in the test pattern editing apparatus which concerns on the 1st Embodiment of this invention.

Explanation of symbols

2... Processing device, 4... Input means, 6. Pointing device, 8 ... storage device, 10 ... display device.

Claims (9)

A test pattern editing apparatus for displaying a dimension line from a reference graphic to a target graphic in a layout verification pattern,
When the measurement position in the reference figure is specified,
Select the actual measurement position from the relative positional relationship in the reference figure of the specified measurement position,
Get the shape of the nearby target figure from the selected measurement position,
Measure the dimensions of the measurement target determined by the shape of the acquired nearby target figure and the selected measurement position,
A test pattern editing apparatus for displaying a dimension line and a dimension value of a measured dimension.   The test pattern editing apparatus according to claim 1, wherein the close target graphic includes the reference graphic itself.   2. The test according to claim 1, wherein the selected measurement position is a side or a corner, and the dimension measurement target determined by the shape of the acquired adjacent target graphic is a side or a corner. Pattern editing device. Verification dimension values are entered and stored in advance,
The test pattern editing apparatus according to any one of claims 1 to 3, wherein a color is changed according to the verification dimension value and the measured dimension, and the dimension line and the dimension value are displayed.   5. The test pattern editing apparatus according to claim 4, wherein the dimension value and the dimension line are displayed only when the measured dimension value is smaller than a predetermined constant multiple of the verification dimension value. A test pattern editing method for displaying a dimension line from a reference graphic to a target graphic in a layout verification pattern,
When the measurement position in the reference figure is specified,
Select the actual measurement position from the relative positional relationship in the reference figure of the specified measurement position,
Get the shape of the nearby target figure from the selected measurement position,
Measure the dimensions of the measurement target determined by the shape of the acquired nearby target figure and the selected measurement position,
A test pattern editing method, wherein a dimension line and a dimension value of a measured dimension are displayed.   The test pattern editing method according to claim 6, wherein the adjacent target graphic includes the reference graphic itself.   2. The test according to claim 1, wherein the selected measurement position is a side or a corner, and the dimension measurement target determined by the shape of the acquired adjacent target graphic is a side or a corner. Pattern editing method. A method of manufacturing a semiconductor device designed by a CAD device for designing a semiconductor integrated circuit, using the test pattern editing method according to claim 6.

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