JPH0547926A - Layout pattern verification equipment - Google Patents

Abstract

PURPOSE:To make it possible to verify cells and regions of layout pattern data having hierarchical structure, by a verification rule having a plurality of reference values. CONSTITUTION:On the basis of control data 2 wherein cells and regions are selected and defined by a verification judgement module 3 so as to correspond with previously determined reference values for verification, a selection method of layout pattern data 1 is determined. By a layout division module 4, the layout pattern data 1 are selected for every cells and regions which can correspond with the respective reference values for verification. By a layout pattern expansion module 5, the layout pattern data of each cell and region are expanded so as to become the same hierarchy, thus obtaining layout pattern data 6 for verification. Said data 6 are verified on the basis of a verification rule 8 by a layout pattern verification module 7, and error data 9 are obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout pattern verification device for verifying whether or not layout pattern data created in the process of designing a semiconductor circuit is correct.

[0002]

2. Description of the Related Art FIG. 6 is a schematic view showing each means constituting a device for verifying a layout pattern data having a hierarchical structure and input / output data thereof, which is shown in FIG.
Indicates layout pattern data having a hierarchical structure. Such layout pattern data 1 is first input to the layout pattern expansion module 5, expands its hierarchical structure, and generates verification layout pattern data 6 composed of layout pattern data of the same hierarchy.
This is output to the layout pattern verification module 7.

The layout pattern verification module 7 verifies the verification layout pattern data 6 on the basis of a verification rule 8 which defines a verification reference value, and outputs error data 9 which is the verification result to the display module 10. Is displayed.

FIG. 7 is a flow chart showing a verification process by the conventional layout pattern verification device described above.
First, the layout pattern data 1 having a hierarchical structure is expanded by the layout pattern expansion module 5 so as to be layout pattern data of the same hierarchy (step T
1) Generate verification layout pattern data 6 (step T2).

The layout pattern verification module 7 verifies the verification layout pattern data 6 with the verification rule 8
Is used to verify (step T3), and the presence or absence of an error is determined (step T4). If there is no error, the verification ends, and if there is an error, error data 9 is generated (step T5), and this is output to the display module 10 to display the error data (step T6), and the verification is performed. finish.

[0006]

In such a conventional apparatus, the verification layout pattern data 6 is used.
The verification rule 8 is used for verifying, but the verification standard value defined in the verification rule 8 is only a single verification standard value corresponding to a certain design rule. Although correct verification is possible for the area designed by, the pseudo error occurs frequently for the area designed by different design rules. Moreover, since a true error and a pseudo error are mixed in this error, there is a problem that the determination is extremely troublesome and the processing takes a long time.

The present invention has been made in view of the above circumstances, and an object thereof is to enable verification for each cell in a semiconductor integrated circuit, or for each reference value set in advance for each region, and a pseudo error occurs. Another object of the present invention is to provide a layout pattern verification device capable of preventing the occurrence of

[0008]

A layout pattern verification apparatus according to the present invention associates layout pattern data including cells and regions designed by different design rules with a plurality of reference values defined in the verification rules. And a means for classifying the layout pattern data of each classified cell and area to generate verification layout pattern data consisting of cells and areas of the same layer.

[0009]

According to the present invention, the cells and regions of the layout pattern data that are hierarchically represented are used by using the control data that describes the cells and regions corresponding to each of the plurality of reference values defined in the verification rule. Based on the verification rule having the plurality of reference values corresponding to each cell and area, the layout pattern data for each cell and area is classified and expanded so that the layout pattern data is expanded to have the same hierarchy. Can be verified.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments. FIG. 1 is a schematic diagram showing the means constituting the layout pattern verification device according to the present invention and its input and output data. In the figure, 1 is the LSI layout pattern data, 2 is the control data, and 3 is the verification judgment module. ing.

The layout pattern data 1 includes cells and regions designed based on different design rules, and is expressed in a hierarchical structure as in the conventional case. The control data 2 includes a verification rule 8 described later. When a plurality of reference values for verification, such as design rules, are defined, each definition is made for each cell and area designed by each design rule. Based on the control data 2, the verification judgment module 3 determines a classification method for the cells and regions of the layout pattern data 1 that correspond to the classification value, and outputs the classification method to the layout division module 4. The layout division module 4
The layout pattern data 1 is sorted for each verification reference value, for example, for each design rule.

FIG. 3 is an explanatory view showing an example of the layout pattern data, and AREA A, Cell as an area designed by the rule A in the layout pattern data 1 now.
A, Cell A, and C as an area designed by Rule B
ell B is AREA as an area designed by rule C
If C is present, the control data 2 corresponding to it is constructed as shown in FIG. 4, for example.

FIG. 4 is an explanatory diagram showing an example of the control data, in which areas classified for each rule, cell names and their coordinate positions, and areas and cell names for each design rule are defined. AREA A 10.0 10.0 25.0 30.0 in Fig. 4 is
AREA A and the coordinate position that identifies it are shown.
It shows that the coordinates of the lower left corner of is (10.0, 10.0) and the coordinates of the upper right corner of AREA A is (25.0, 30.0). The same applies to AREA B.

Rule A = AREA A, Cell A is AREA A,
Each cell Cell A indicates that it is an area or cell designed under Rule A (Rule A). Rule B (Rul
The same applies to e B) and Rule C. When the layout pattern data is sorted into areas and cells for each design rule based on such control data 2,
It will be classified as shown by the hatched lines and dots in FIG. 3, respectively. That is, cells and regions that are separated by attaching a diagonal line to the right are marked according to design rule A, and cells and regions that are separated by attaching a diagonal line to the left are marked according to design rule B. It is indicated that the areas classified by the above are cells and areas designed according to the design rule C.

Next, the layout pattern data for each cell and area sorted by the layout pattern developing module 5 are developed up to the same layer, and this is input to the layout pattern verifying module 7 as verification layout pattern data 6. .. The layout verification module 7 verifies the input verification layout pattern data 6 based on a verification rule 8 as shown in FIG. 5, outputs an error data 9 if an error exists, and displays this error data. Display to 10.

FIG. 5 is an explanatory diagram showing an example of the verification rule. For example, regarding the width WIDTH, the width verification for Layer A is 1.2 in Layer A, which is designed based on rule A (Rule A). (μm), Rule B (Rule
The part designed based on B) is 1.5 (μm), and the part designed based on Rule C (Rule C) is 1.7 (μm)
Are the verification reference values, and parts designed based on rules other than these rules A, B, and C are LT 2.0, that is, 2.0.
This means that (μm) is used as the reference value for verification.

Further, in FIG. 5, the layer spacing of the layer A (Layer A)
Regarding (SPACE), the part designed based on Rule A (Rule A) is 2.5 (μm), the part designed based on Rule B (Rule B) is 2.8 (μm), based on Rule C (Rule C) Designed parts have 3.0 (μm) as the verification reference value,
For the part designed based on other rules, 2.7 (μm) is used as the verification reference value.

FIG. 2 is a flow chart showing the processing steps of the layout pattern verification apparatus described above. The verification judgment module 3 judges the method for separating layout pattern data based on the verification reference value (step S1).
Layout pattern data 1 based on the determined classification method
Are divided into blocks such as cells and regions (step
S2). The layout pattern data for each separated block is expanded to the same level (step S3), and verification layout pattern data is generated (step S4).

Verification is performed for each block or each block and other cells and regions (step S5), and it is judged whether or not there is an error (step S6). If there is no error, the verification is terminated, and there is an error. In this case, error data is generated (step S7), and the error data is displayed (step S8). In the above-described embodiment, the case where the verification reference value is set corresponding to each design rule has been described, but one verification reference value may be set for each of a plurality of design rules.

[0020]

As described above, in the device of the present invention, the verification reference value defined according to each design rule is defined by classifying cells and areas having different verification reference values of the layout pattern. The present invention has excellent effects such that the verification can be performed according to the rule and the verification can be performed without the occurrence of the pseudo error.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing each unit that constitutes a layout pattern verification device according to the present invention and its input and output data.

FIG. 2 is a flowchart showing a process of a layout pattern verification device according to the present invention.

FIG. 3 is an explanatory diagram showing an example of layout pattern data according to the present invention.

FIG. 4 is an explanatory diagram showing an example of control data used in the layout pattern verification device according to the present invention.

FIG. 5 is an explanatory diagram showing an example of a verification rule used in the layout pattern verification device according to the present invention.

FIG. 6 is an explanatory view showing each means constituting the conventional device and its input and output data.

FIG. 7 is a flowchart showing a processing process of a conventional device.

[Explanation of symbols]

 1 Layout pattern data 2 Control data 3 Verification judgment module 4 Layout division module 5 Layout pattern expansion module 6 Verification layout pattern data 7 Layout pattern verification module 8 Verification rules 9 Error data 10 Display module

Claims (1)

[Claims] 1. A layout pattern verification device for developing verification layout pattern data by expanding hierarchically represented layout pattern data so as to have the same hierarchy, and verifying the layout pattern data based on a verification rule. Means for classifying cells and areas of the layout pattern data based on control data describing cells and areas corresponding to a plurality of reference values defined in the verification rule, and layout of each classified cell and area A means for expanding pattern data to generate verification layout pattern data that is layout pattern data on the same layer, and a means for verifying based on each of a plurality of reference values in a verification rule having the verification layout pattern data. A layout pattern verification device, comprising: