JPH03227047A - Layout formation - Google Patents

Abstract

PURPOSE:To make possible a shortening in a verification time and a reduction in the amount of data to be verified by a method wherein at the time of correction of the layout graphic form of an integrated circuit, an input available region is specified and at the time of a layout verification, a verification on the input available region only is performed. CONSTITUTION:A layout verification on the whole layout 21 is performed to detect an error graphic form 22 and this error graphic form 22 is decided as an error graphic form because error sides 23 and 24 have not a regular interval or wider between them. There, an input available region on a layout graphic form of a layout input device is specified as an input available region 25, the region 25 on the the layout graphic form is projected on the whole screen on a screen, correction is made in data only within the screen and the layout graphic form is added to layout data as part of the data. Then, the interval between the sides 23 and 24 is widened and is fitted to the regular interval, the graphic form 22 is drawn into a correction finished graphic form 26 and a verification n the layout only of the region 25 is performed on the basis of coordinate information on the region 25 on the layout graphic form added top the layout data as part of the data.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for creating a layout for inputting, modifying, and verifying the layout of a semiconductor integrated circuit. This will be explained with reference to FIG.

FIG. 4 shows a flowchart of a conventional layout creation method. First, in step 41, a layout is input, and in step 42, the layout is verified. If there is no error in step 43, the layout creation is finished in step 45. If there is an error, proceed to step 44 to correct the layout. Step 4 again.
Verification is performed using 2. Do this until there are no more errors.

Specifically, the work shown in Fig. 5 (A
), first, in step 41, a layout figure is input using the layout input device. In FIG. 5A, the entire layout 21 is an area in which layout figures can be input. Next, step 4 as shown in Figure 5(B)
2, the entire layout 21 is verified and error graphics 22 are detected. This error figure 22 has side 2
3 and the side 24 do not have an interval greater than the rule, so an error is determined in step 43. Therefore, as shown in FIG. 5(C), in step 44, the error figure 22 is corrected using the layout input device to create a figure 31 that conforms to the rules. Also in FIG. 5(C), the entire layout 21 is an area in which layout figures can be input. The revised layout is the entire layout 2 as shown in Figure 5 (D).
1, the layout is verified in step 42, and if no error is determined in step 43, the layout creation is completed in step 45.

Problem to be Solved by the Invention When correcting errors detected in this way and performing verification again, it is necessary to perform verification over all areas, not just the part where the error was corrected. This is because it is not guaranteed that only the layout of the error part has been changed, and other parts may also be changed by mistake. If there is an error in even one part of the layout, it is necessary to re-verify the entire area of the layout, which is extremely inefficient in terms of the amount of data that must be handled and the processing time. Powerful and strong with the concept of design
In recent years, semiconductor integrated circuits have become more highly integrated, and the problem of a large amount of data and long processing time also exists in the layout of the lowest layer blocks. -Large If the number of layers is increased, the amount of data in the blocks at the bottom layer can be reduced, but the number of blocks increases, leading to data management problems and increased wiring between blocks, which increases the ratio of the wiring area to the overall chip area. There are problems such as complicate calculation of capacity values between blocks and between layers.

The present invention (L) An object of the present invention is to provide a layout creation method that can improve the efficiency of layout verification.

Means for Solving the Problems The present invention defines an area in which input can be made when modifying a layout figure of an integrated circuit, and when verifying the layout, only the area in which input is possible is verified.

Effects of the present invention By the means described above, it is guaranteed that the IL and layout have not been changed in areas other than the input-enabled area, and layout verification only needs to be performed in the input-enabled area, thereby increasing the efficiency of verification.

EXAMPLES Examples of the present invention will be described below with reference to FIGS. 1 to 3.

A flowchart of the present invention is shown in FIG. First, in step 1, a layout is input, and in step 2, the layout is verified. If there is no error in step 3, the layout creation is finished in step 6. If there is an error, specify the layout input area in step 4 and correct the layout in step 5. X. Verify again in step 2. In the present invention, verification is performed only in the input possible area. Repeat these steps until the error disappears. When creating a new layout, the input area is the entire layout, and verification is performed on the entire layout.

A specific example will be described with reference to FIGS. 2 and 3.

First, as shown in FIG. 2(A), in step 1, a layout is input using a layout input device.

In FIG. 2(A), the entire layout 21 is an area in which layout figures can be input. Next, as shown in FIG. 2(B), in step 2, the entire layout 21 is verified and error graphics 22 are detected. This error figure 22 is determined to be an error by the steering knob 3 because the sides 23 and 24 do not have a distance greater than the rule. Therefore, first, as shown in FIG. 2(C), in step 4, the layout figure inputtable area of the layout input device is changed to area 2.
Specify 5. The area 25 is designed to include all error figures. Then, as shown in FIG. 2(D), the layout figure input possible area 25 of the layout input device
is displayed on the screen in full screen, and in step 5 it is possible to modify only the data number on the screen. It becomes impossible to modify data outside the screen, and it is guaranteed that the data outside the screen remains unchanged. Since the coordinate information of this input possible area 25 is necessary during layout verification 2, it is added to the layout data as part of the data. Next, as shown in FIG. 2(E), the error figure 22 is expanded in step 5 to form a figure 26 that complies with the rule by increasing the distance between the error sides 23 and 24. In FIG. 2(E), an input possible area 25 is an input possible area for layout figures. As shown in FIG. 2(F), the corrected layout is verified in step 2 based on the coordinate information of the inputtable area of the layout figure added as part of the layout data. conduct.

Next, the input possible area is verified using the following method. Third
In order to verify the layout of the input possible area 25 in FIG. 3(A), first, as shown in FIG.
is enlarged to form a verification region 31. This is to verify data near the boundary of the input possible area 25. Third
As shown in Figure (C), the error 32 is verified in the incorrectly corrected figure 33 by widening the interval between the error sides 23 and 24 and expanding the upper side of the error figure 22 upward. Also the third
As shown in FIG. 3(D), a narrow figure 34 is verified within the verification area 31, and an error 35 occurs on the boundary of the enlarged area as shown in FIG. 3(E). This error 35 is not an error (pseudo error) when viewed from the layout as a whole. Therefore, as shown in FIG. 3(F), the enlarged area is reduced and only the error 32 within this reduced area 36 is displayed. Furthermore, the layout is completed by repeating correction and verification for the detected error 32 until the error disappears.

Effects of the Invention By applying the method of the present invention, it is possible to define an input-enabled area for modifying layout figures, and to verify only the input-enabled area during layout verification. By specifying the input possible area, it is guaranteed that the layout has not been changed outside the input possible area, and layout verification only needs to be performed in the input possible area.By reducing the verification area in this way,
Shorter verification time The amount of data to be verified can be reduced. In the future, the scale of LSI will continue to increase, and the time and disk space required to create a layout will increase. This method is effective because it improves the efficiency of verification.

[Brief explanation of drawings]

FIG. 1 is a flowchart of an embodiment of the present invention. FIG. 2 is a schematic explanation of an embodiment of the present invention. FIG. 3 is a flow chart of an embodiment of the present invention. 2... Layout verification means, 4... Long-term possible area setting means, 5... Layout correction already completed 21...
All layout &22...Error diagram i 23,24・
... Error side 25 ... Input possible area 26 ... Error corrected figure 31 ... Verification range [32, 35 ...
・Error, 33... Erroneously corrected figure 34... Narrow width figure 36... Reduced verification raft

Claims (1)

[Claims] 1. A layout creation method, characterized in that, when modifying a layout figure of an integrated circuit, an input possible area is defined, and layout verification is performed only on layout data of the input possible area.