JPH04111447A - Processing device for data on mask pattern of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To make it possible to process easily a notch part at the time of a design rule check on the mask pattern of a semiconductor integrated circuit having a graphic patter, which is complicated in shape, by a method wherein a third graphic pattern for covering the notch part is formed by a formation-of- rectangle processing, an undersize processing and an oversize processing. CONSTITUTION:A formation-of-rectangle processing is performed on a first graphic pattern 1 in a formation-of-rectangle processing means 20 and a normal rectangular pattern 3 is formed. Then, the four sides of the pattern 3 are moved to the inner side by a length L in an undersize processing means 30 to obtain a reduced rectangular pattern 4. Subsequently, a design rule check is performed between the pattern 4 and a second graphic pattern 2 in a design rule checking means 40 and an error graphic pattern 5 is formed. Subsequently, the outline of the pattern 5 is moved by the prescribed length L to the outer side to the pattern 5 in an oversize processing means 50 to form a third graphic pattern 6. Lastly, data on a new mask pattern formed by adding the pattern 6 to the patterns 1 and 2 is produced in a mask pattern update means 60.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a mask pattern data processing device for semiconductor integrated circuits, and in particular, a device for processing notches that violate design rules in mask pattern data consisting of a large number of figures. Regarding.

[Conventional technology]

In recent years, with the advancement of CAD technology, the layout design of mask patterns for semiconductor integrated circuits has been increasingly performed using automatic layout systems using computers. In such a system, a computer can perform an optimal layout design based on a logic circuit diagram, and this technology is becoming increasingly important in the design of semiconductor integrated circuits whose degree of integration tends to increase year by year.

A design rule check is normally performed on the mask pattern whose layout has been designed in this manner. In this check, it is determined whether the arrangement distance between one pattern and another pattern is maintained at a predetermined distance or more. If a plurality of different patterns are arranged within a specified distance, phenomena such as current leakage may occur in actual semiconductor devices, which is undesirable. This design rule check is also performed using graphical calculations using a computer, and if multiple patterns are found to be placed close to each other within a specified distance, the computer generates an error and corrects this. The designer is informed. However, in such computer-based design rule checking, pseudo errors may occur when they are not originally errors. For example, the graphic pattern of a contact cell and the graphic pattern of a wiring layer to be connected to it are
placed in partially overlapping positions. Since the shapes of both graphic patterns are different from each other, a notch portion (a concave concave portion) may occur near the overlapping portion. At this notch part, it is determined that both graphic patterns are arranged close to each other within a prescribed distance, and the computer generates an error when checking the design rule.

Since the contact cell and the wiring layer are originally electrically connected, problems such as current leakage do not occur even if both graphic patterns are arranged close to each other within a prescribed distance.

However, in normal design rule checking, the electrical connection relationships of each pattern are not taken into account, so pseudo errors occur in such notch portions.

When designing a layout manually, the layout was designed with consideration given to preventing such notches from occurring, but in recent years automatic layout systems have been designed to prevent such notches from occurring. It is very difficult to do.

Therefore, conventionally, when a pseudo error based on a notch occurs in a design rule check, a designer manually processes the notch each time. That is, a graphic pattern that embeds this notch is added, and a design rule check is performed to prevent pseudo errors from occurring.

[Problem to be solved by the invention]

However, for highly integrated mask patterns,
It takes a lot of effort and time to process the notches manually. If the notch has a simple rectangular shape, it is possible to generate a rectangular figure corresponding to the notch using a conventional design rule checking system. By performing the process of embedding the notch part using this rectangular figure, it is possible to deal with pseudo errors in design rule checking. However, in recent years, complex graphic patterns in which the corners of rectangles are cut out have come to be used for contact cells and the like. Therefore, the graphic calculation function of the conventional design rule checking system cannot generate graphics for embedding processing.

SUMMARY OF THE INVENTION Therefore, the present invention provides a mask pattern data processing device for a semiconductor integrated circuit that can easily process a notch portion during design rule checking for a mask pattern for a semiconductor integrated circuit having a graphic pattern with a complicated shape. The purpose is to

[Means to solve the problem]

The present invention provides a mask pattern data processing device for a semiconductor integrated circuit that processes a notch portion that violates a design rule in mask pattern data consisting of a large number of shapes. and,
a second graphic pattern that forms a notch portion by overlapping with the first graphic pattern; rectangularization processing means for generating a pattern; undersize processing means for generating a reduced rectangular pattern by moving the outline of the pattern inward by a predetermined distance ML with respect to the regular rectangular pattern; and a reduced rectangular pattern. a design rule checking means for performing a design rule check with a second graphic pattern to generate an error graphic pattern corresponding to a notch portion existing between the two; oversize processing means for generating a third graphic pattern by moving a predetermined distance to the first graphic pattern and the second graphic pattern;
mask pattern updating means for generating new mask pattern data to which the figure pattern of is added;

[For production]

In the processing device according to the present invention, the first graphic pattern and the second
A third graphic pattern that can cover up the notch formed between the third graphic pattern and the third graphic pattern is automatically generated.

This third graphic pattern can be generated by basic graphic logical operations such as rectangularization processing, undersize processing, and oversize processing. By adding this third graphic pattern to the first and second graphic patterns, the notch portion will not be detected in the design rule check. In this way, with respect to a mask pattern of a semiconductor integrated circuit having a graphic pattern having a complicated shape, it is possible to easily process the notch portion during design rule checking.

〔Example〕

The present invention will be described below based on illustrated embodiments. 1st
FIG. 1 is a block diagram showing the basic configuration of a mask pattern data processing device for a semiconductor integrated circuit according to the present invention. This device has a function of processing notches that violate design rules in mask pattern data consisting of a plurality of figures. This device is actually composed of a computer, but it is shown here divided into blocks for each function. That is, this apparatus includes processing object recognition means 10, rectangularization processing means 20, undersize processing means 30, design rule checking means 40, oversize processing means 50, mask pattern updating means 60,
It consists of six blocks.

Hereinafter, the operation of this apparatus will be explained by taking processing for a specific graphic pattern as an example. Now, it is assumed that the first graphic pattern 1 and the second graphic pattern 2 as shown in FIG. 2 have caused a pseudo error in the design rule check. Here, the first graphic pattern 1 is a contact cell, and the second graphic pattern 2 is a wiring layer that electrically contacts this contact cell. The first graphic pattern has a rectangular shape with the corners cut out, and the second graphic pattern has an L-shaped belt shape. When a design rule check is performed on such two graphic patterns, a pseudo error will occur if the distance between the figures is less than the prescribed distance of the design rule due to the presence of the notch N.

The processing target recognition means 10 has a function of recognizing two patterns that have caused pseudo errors based on notches as a result of such a design rule check. The process for the design rule checking system to recognize which of the errors that have occurred are pseudo errors based on the notch part is relatively complicated. Therefore, in the apparatus of this embodiment, this recognition is performed based on input from the designer. That is, the processing object recognition means 10 notifies the designer of all errors generated by the design rule checking system by displaying them on the display. The designer selects a pseudo error based on the notch portion suitable for processing by the apparatus of the present invention from among these, and manually inputs the selection result to the processing target recognition means 10. In this way, the processing target recognition means 10 can recognize the graphic pattern to be processed. In the example described here, the first graphic pattern 1 and the second graphic pattern 2 shown in FIG. 2 are recognized as processing targets. In this way, as shown in FIG. 1, the processing target recognition means 10 supplies the first graphic pattern having a notch to the rectangularization processing means 20 and the mask pattern updating means 60, and designs the second graphic pattern. It is applied to the rule checking means 40 and the mask pattern updating means 60.

Subsequently, the rectangularization processing means 20 performs rectangularization processing on the first graphic pattern 1 to generate a regular rectangular pattern without corner notches.

That is, as shown in FIG.
A regular rectangular pattern 3 is generated based on. This process may be performed by extending the four sides of the first graphic pattern and generating a new rectangle whose four vertices are the intersections of the extended lines.

Next, the undersize processing means 30 performs undersize processing on the regular rectangular pattern 3 to generate a reduced rectangular pattern by moving the outline of the pattern inward by a predetermined distance ML. That is, the third
Each of the four sides of the regular rectangular pattern 3 shown in the figure is a distance ML
If the pattern is moved inward by the same amount, a reduced rectangular pattern 4 as shown in FIG. 4 is obtained. This undersize processing is a well-known process that is included in conventional general mask pattern data processing devices for semiconductor integrated circuits.

Note that the predetermined distance fiL is set to a predetermined value such that a≦L≦b in FIG. 4.

Subsequently, the design rule checking means 40 performs a design rule check between the reduced rectangular pattern 4 and the second graphic pattern 2, and generates an error graphic pattern corresponding to the notch portion existing between the two. That is, as shown in FIG. 5, an error graphic pattern 5 (indicated by hatching) is generated. This error figure pattern 5 is composed of the reduced rectangular pattern 4 and the second figure pattern 2.
This is a pattern that corresponds to the notch part that exists between
Conventional general design rule checking systems include:
A function is provided to generate a figure corresponding to such a notch part as an error figure.

Therefore, the design rule checking means 40 may use a conventional general system as is. In this example, for two sides (each belonging to a different figure pattern) that are less than or equal to the length (L+D),
A design rule check regarding spacing may determine that the rule is violated, and an error figure may be generated based on the edge that violates the rule.

Subsequently, the oversize processing means 50 performs an oversize process on the error graphic pattern 5 by moving the outline of the pattern outward by a predetermined distance to generate a third graphic pattern. That is, as shown in FIG. 6, a third graphic pattern 6 is generated. This oversize processing is also a well-known process that is included in conventional general mask pattern data processing devices for semiconductor integrated circuits. Here, the predetermined distance is equal to the predetermined distance used in the undersize process described above.

Finally, the mask pattern updating means 60 generates new mask pattern data in which the third graphic pattern 6 is added to the first graphic pattern 1 and the second graphic pattern 2. That is, the mask pattern data as shown in FIG. 2 is updated to the mask pattern data as shown in FIG.

Since the notch portion N has been embedded using the third graphic pattern 6, when a design rule check is performed on this new mask pattern data, no pseudo error occurs. Furthermore, in an actual semiconductor integrated circuit, a logical OR operation is performed on the first graphic pattern 1, the second graphic pattern 2, and the third graphic pattern 3 to form an actual pattern layer. Therefore, no problem will occur even if the third graphic pattern 6 is added.

Although the present invention has been described above using the specific graphic pattern shown in FIG. 2 as the processing target, the present invention is not limited to such a pattern, but can also be applied to various other patterns. For example, in the above-described embodiment, the first graphic pattern is a pattern in which the corner is cut out by a straight line, but the present invention is also applicable to a pattern in which the corner is cut out by a curved line. .

[Effects of the Invention] As described above, according to the mask pattern data processing device for a semiconductor integrated circuit according to the present invention, it is possible to cover up the notch formed between the first graphic pattern and the second graphic pattern. Since the third graphic pattern is generated by graphic calculation and the embedding process is automatically performed, the notch part is processed when checking design rules for mask patterns of semiconductor integrated circuits that have graphic patterns with complex shapes. can be easily done.

Figure 3 is a diagram showing an example of the pattern shown in Figure 2 after rectangularization processing is performed, and Figure 4 is a diagram showing an example of the pattern shown in Figure 3 subjected to undersize processing. Figure 5 is a diagram showing a state in which the pattern shown in Figure 4 has been subjected to a design rule check and an error figure pattern has been generated. FIG. 7 is a diagram showing a state where the size processing has been performed. FIG. 7 is a diagram showing a pattern finally obtained by performing a series of processing by the apparatus of the present invention on the pattern shown in FIG. 2.

1... First figure pattern, 2... Second figure pattern, 3... Regular rectangular pattern, 4... Reduced rectangular pattern, 5... Error figure pattern, 6... Third figure pattern. 3
shape pattern.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the basic configuration of a mask pattern data processing device for a semiconductor integrated circuit according to the present invention, and FIG. 2 is a block diagram showing the basic configuration of a mask pattern data processing device for a semiconductor integrated circuit according to the present invention, and FIG. 2 is a block diagram showing the processing target of the device shown in FIG. Agent Patent Attorney Hiroshi Shimura Figure 1

Claims (1)

[Claims] An apparatus for processing notch portions that violate design rules in mask pattern data consisting of a large number of figures, comprising: a rectangular first figure pattern having notched corners;
a second graphic pattern that forms a notch by overlapping with the first graphic pattern; rectangularization processing means that generates a rectangular pattern; undersize processing means that generates a reduced rectangular pattern by moving the outline of the pattern inward by a predetermined distance L with respect to the regular rectangular pattern; a design rule checking means for performing a design rule check between the rectangular pattern and the second graphic pattern to generate an error graphic pattern corresponding to a notch portion existing between the two; an oversize processing means for generating a third graphic pattern by moving the contour line outward by a predetermined distance L;
A mask pattern data processing device for a semiconductor integrated circuit, comprising: mask pattern updating means for generating new mask pattern data to which the third graphic pattern is added.