JP2009194315A - Layout verification apparatus and layout verification method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a layout verification apparatus capable of performing layout verification without defining a voltage that is finally applied to a pad. <P>SOLUTION: The layout verification apparatus includes: a voltage potential recognition processing section that recognizes the voltage potential of a conductive layer based on graphic data of a layout; and a reference verification section of voltage potential dependence design that verifies the layout of the semiconductor apparatus based on the recognized potential of the conductive layer. A design rule may be verified even in a state that a layout up to the pad is not designed. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a layout verification apparatus and a layout verification method, and more particularly to a layout verification apparatus and a layout verification method for verifying design rules in a semiconductor device.

  A semiconductor device using a plurality of power supply voltages is known. In such a semiconductor device, the layout standard (design rule) may differ depending on the power supply voltage used for each element. Patent Document 1 discloses a layout verification method and a layout verification apparatus in such a semiconductor device.

In the technique described in Patent Document 1, a semiconductor integrated circuit is designed, and a design rule check is performed at each power supply voltage from the voltage finally applied to the pad.
JP 2000-124320 A

  However, in the conventional layout verification method and layout verification apparatus, the design rule check can be performed only when the layout is designed to the pad. In addition, since the power supply voltage is set for each pad or the like, an accurate design rule check may not be performed due to an artificial setting error.

One embodiment of the present invention provides:
A potential recognition processing unit for recognizing the potential of the conductive layer based on the graphic data of the layout of the semiconductor device;
The layout verification apparatus includes a potential-dependent design reference verification unit that verifies a layout reference of the semiconductor device based on the recognized potential of the conductive layer.

Another aspect of the present invention is:
Recognize the potential of the conductive layer based on the layout data of the semiconductor device,
In this layout verification method, the layout reference of the semiconductor device is verified based on the recognized potential of the conductive layer.

  According to the present invention, the design rule can be verified even when the layout is not designed to the pad.

Embodiment 1
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram schematically showing a semiconductor device 100 to which the layout verification method of the present invention is applied. FIG. 2 is a diagram schematically showing a cross section taken along line II-II in FIG. In the semiconductor device 100, regions 10, 20, and 30 that operate with different power supply voltages are formed.

  In the following description, it is assumed that the semiconductor device 100 is a P-type substrate, the N-type MOS transistor is formed on a P-type substrate, and the P-type MOS transistor is formed on an N-well formed on the P-type substrate. . However, the semiconductor device 100 is not limited to that shown in FIG. 1, and an N-type substrate may be used. Even if a P-type substrate is used, the N-type MOS transistor is not necessarily provided on the P-type substrate, but may be provided on a P-well using a multilayer well structure such as a twin well or a triple well.

  The first region 10 formed in the semiconductor device is an N well. In the first region 10, for example, a PMOS transistor that operates with a power supply voltage of 1.8V is formed. The second region 20 is an N well. In the second region 20, a PMOS transistor that operates with a power supply voltage of 3.3V, for example, is formed. The third region 30 corresponds to a P-type substrate, and an NMOS transistor that operates with a power supply voltage of 1.8 V, for example, is formed.

  In general, a substrate terminal of a PMOS transistor formed on a semiconductor device is connected to a power supply potential (first power supply voltage). That is, the N well or N type substrate in which the PMOS transistor is formed is set to the power supply potential at which the transistor operates. The substrate terminal of the NMOS transistor formed on the semiconductor device is connected to the ground potential (second power supply voltage) of the transistor. That is, the P well or P type substrate in which the NMOS transistor is formed is set to the ground potential.

  Therefore, in the first region 10 and the second region 20 which are N wells shown in FIGS. 1 and 2, regions called taps for supplying power supply voltages of transistors formed in the regions are formed. . When a potential is applied to the N well, this tap is usually formed of an N-type high concentration diffusion layer (N + region). The tap areas 11 and 21 correspond to the hatched areas in FIGS. Similarly, a tap for applying a ground potential is also formed on the P-type substrate of the semiconductor device 100 in which the NMOS transistor is formed. A P-type high-concentration diffusion layer 31 corresponding to this tap is shown in FIGS.

  In a semiconductor device, design rules are set according to a circuit to be designed. Here, the design rule is a rule defined for each layer. The design rule may be set so that the standard value that is a standard changes depending on the potential difference between the structures. In the case where a plurality of types of power supply voltages exist, such as when a plurality of types of transistors having different power supply voltages are formed, the design rule is further set in consideration of each power supply voltage.

  For example, 12 diffusion layers of source and drain formed in the first region 10, 22 diffusion layers of source and drain formed in the second region 20, and source and drain diffusion layers formed in the third region 30. The diffusion layer is 32. In this case, as shown in FIG. 1, the distance between the diffusion regions (indicated by FIGS. 1, A, B, and C) is determined by design rules such as an allowable distance according to each power supply voltage and conductivity type. Yes. Since only the substrate of the semiconductor device 100 is shown in FIGS. 1 and 2, an example of the design rule is described based on the distance between the diffusion layers, but in reality, the wiring layer connected to each transistor and the tap region 11. Design rules that are standards such as allowable values are also set for the polysilicon layer, the transistor, and the well existing under the tap region 11. For example, an allowable value is defined by a design rule for the interval and width between wirings.

  In the example shown in FIGS. 1 and 2, 1.8 V is applied to the tap region 11 of the first region 10, and a voltage of 0 to 1.8 V is applied to the source / drain region 12. The tap region 21 of the second region 20 is supplied with 3.3 V, and the source / drain region 22 is supplied with a voltage of 0 to 3.3 V. A ground potential GND is applied to the high concentration diffusion layer 31 in the third region 30, and a voltage of 0 to 1.8 V is applied to the source / drain region 32.

  That is, the element formed on the semiconductor substrate, the diffusion layer corresponding to the element, and the voltage applied to the diffusion layer can be determined when the layout on the semiconductor substrate is determined.

  This embodiment uses the point that the range of potentials applied to the diffusion layer can be determined at the stage when the layout of the elements formed on the semiconductor substrate and the diffusion layer is determined. The design rule is checked such as a wiring layer connected to the diffusion layer.

  The present embodiment relates to a layout verification apparatus and layout verification method for checking design rules as described above. FIG. 3 shows a layout verification apparatus according to the present embodiment.

  The layout verification apparatus according to the present embodiment includes a first verification unit (DRC verification unit) 312. The first verification unit 312 is a part that recognizes the voltage applied to each diffusion layer from the graphic data of the layout of the diffusion layer and performs layout verification based on the voltage. That is, the first verification unit 312 checks the design rule when the layout of the diffusion layer is determined.

  The layout verification apparatus further includes a layout data holding unit 301, a mask creation processing unit 302, and mask data 303. The first verification unit 312 includes a potential recognition processing unit 304, a potential propagation processing unit 305, a potential dependent design reference verification unit 306, an error location display unit 307, and a layout reference data holding unit 314.

  The layout data holding unit 301 is a part that holds layout data of the semiconductor device. The layout data held here includes a layout related to the arrangement of diffusion layers, wells, etc. on the semiconductor substrate as shown in FIGS. Further, layout data relating to a plurality of wiring layers formed on the semiconductor substrate when formed as an integrated circuit is also included.

  The layout reference data holding unit 314 records rules for recognizing conductivity types and voltage systems such as wells and diffusion layers from the data recorded in the layout data holding unit 301 and layout references such as the minimum wiring interval of each voltage system. ing.

  The mask creation processing unit 302 is a part that creates a mask for each layer from the layout data held in the layout data holding unit 301 and outputs the mask data. The mask data holding unit 303 is a part that holds the mask data created by the mask creation processing unit.

  The potential recognition processing unit 304 is a part that recognizes the design voltage of each well and the diffusion layer formed in each well from the layout data of the semiconductor device that forms the elements having a plurality of power supply voltages as described above. Specifically, the design voltage of each well and the diffusion layer formed in each well can be recognized by performing the mask layer synthesis process using the graphic data of the layout based on the recognition rule.

  If the diffusion layer formed in the well corresponds to the source or drain, it is recognized that the power supply voltage signal applied to the element is supplied to the diffusion layer (exactly from GND to the power supply voltage). A voltage signal between the two is provided, but it is preferable that the check is performed under stricter conditions in the design rule check. Therefore, the voltage applied to the diffusion layers such as the source and drain is a power supply voltage signal).

  For reference, FIG. 4 shows the relationship between the power supply voltage of the element formed in the well and the voltage applied to the diffusion layer formed in the well. As shown in the figure, the voltage of the diffusion layer can be determined by the conductivity type and voltage system of the well and the conductivity type of the diffusion layer formed thereon. Note that FIG. 4 shows an example, and it goes without saying that when the power supply voltage or the like changes, the applied voltage also changes.

  The potential propagation processing unit 305 is a part that tracks the propagation path of the potential applied to the diffusion layer recognized by the potential recognition processing unit 304. The tracking of this propagation path starts from the lower layer wiring closest to the diffusion layer and gradually goes up to the upper layer wiring. The pattern of tracking the propagation path is schematically shown in cross-sectional views in FIGS.

  5 to 7, unlike the cross-sectional view shown in FIG. 2, an N well 401 is an N well region for forming an element that operates with a 1.8 V power source, and a P well (P substrate) 402 is a source / source for NMOS. It is assumed that the drain diffusion and P + tap forming region, the N well 403 is an N well region for forming an element that operates with a 3.3 V power supply. The diffusion layers 404, 405, and 406 formed in the well may be the tap described above or a diffusion layer having a conductivity type opposite to that of the well.

  5 (a), 6 (a), and 7 (a) are plan layout views, and FIGS. 5 (b), 6 (b), and 7 (b) are perspective layout views from the lateral direction. . 5B, 6B, and 7B, the solid line on the potential propagation path indicates a wiring layer, and the broken line indicates a path between wiring layers such as contacts.

  As shown in FIG. 5, the potential propagation processing unit 305 first starts from the design potentials of the N wells 401 and 403 and the P well 402 recognized by the potential recognition processing unit 304 from the layout data to the first layer wirings M11 to M13. Obtain the propagation path of each potential. Thereafter, as shown in FIG. 6, a potential propagation path from the potential propagation path obtained for the first layer wirings M11 to M13 to the second layer wirings M21 to M23 is obtained. Similarly, as illustrated in FIG. 7, the potential propagation processing unit 305 acquires a potential propagation path from the third-layer wirings M31 to M33. That is, the potential propagation processing unit 305 acquires a potential propagation path in order from the lower layer side to the upper layer side based on the well design potential recognized by the potential recognition processing unit 304 from the layout data.

  The potential-dependent design reference verification unit 306 verifies the layout based on the layout reference from the propagation path for each power supply voltage acquired by the potential propagation processing unit 305 and the power supply voltage corresponding to each propagation path, and determines the design rule. It is a part to check whether it meets. The error location display unit 307 combines the error location that does not satisfy the design rule verified by the potential dependent design reference verification unit 306 with the layout data and displays it. This error location is fed back to the layout data.

  Next, a layout verification method will be described in detail with reference to FIG. FIG. 8 is a flowchart showing the layout verification method of the first verification unit. First, the potential recognition processing unit 304 recognizes a design potential of a well or a substrate from layout data of a semiconductor device in which a plurality of elements having different power supply voltages are formed based on a recognition rule (S1).

  Next, in step 1, the potential propagation processing unit 305 recognizes the potential of the conductive layer connected to the well or the substrate based on the design potential of the well or the substrate (S2). For example, referring to the table of FIG. 4, if the diffusion layer 404 formed in the 1.8V N-WELL 401 in FIG. 5 is N-type, the diffusion layer 404 is a 1.8V power supply layer. . If the diffusion layer 404 is P-type, it can be recognized that the diffusion layer 404 is a 1.8V signal. Furthermore, a contact C11 that connects the base and the first wiring layer and a first wiring M11 are provided so as to overlap the diffusion layer 404. Therefore, the diffusion layer 404 and the first wiring M11 are connected via the contact C11. Accordingly, it can be recognized that the first wiring M11 is a 1.8V power supply wiring or a 1.8V signal wiring.

  Similarly, it can be recognized that the P + diffusion layer 405 provided in the P-WELL and the first wiring M12 connected to the P + diffusion layer 405 via the contact C12 are ground wirings. Furthermore, the diffusion layer 406 provided in the 3.3V N-WELL 403 is a 3.3V system power layer or a 3.3V system signal depending on the power supply type, and is connected to this via a contact C13. It can be recognized that the first wiring M13 to be used is a 3.3V power supply wiring or a 3.3V signal wiring.

  Then, the potential-dependent design reference verification unit 306 verifies the layout reference of the semiconductor device based on the recognized potential of the conductive layer (S3). That is, the layout determines whether the distance d11 between the 1.8V power supply or signal wiring M11 and the ground wiring M12 and the distance d12 between the ground wiring M12 and the 3.3V power supply or signal wiring M13 satisfy the design criteria. You can check against the standard. Thereby, the potential of each wiring can be recognized, and the design rule can be checked based on the potential of each wiring. In FIG. 5, the layout is completed only up to the first wiring layer. Thus, even if the layout of the second wiring layer and the third wiring layer shown in FIG. 6 and FIG. 7 is in an incomplete state, the design rule check of the layers below the first wiring layer can be performed.

  Furthermore, when the layout is completed up to the second wiring layer as shown in FIG. 6, the design rule of the layers up to the second wiring layer can be checked. For example, a contact C21 that connects the first wiring layer and the second wiring layer is provided so as to overlap the first wiring M11 and the second wiring M21. Therefore, it can be recognized that the second wiring M21 is connected to the first wiring M11, and the second wiring M21 is a 1.8V system power wiring or a 1.8V system signal wiring like the first wiring M11. Can be recognized.

  Similarly, a contact C22 is provided so as to overlap the first wiring M12 and the second wiring M22, and C23 is provided so as to overlap the first wiring M13 and the second wiring M23. Therefore, the potentials of the second wirings M22 and M23 can be recognized. Based on the potentials of the second wirings M21, M22, and M23, the design rule check can also be performed for the distances d21 and d22 between the second wirings.

  Furthermore, as shown in FIG. 7, if the layout is completed up to the third wiring layer, the potentials of the third wirings M31, M32, and M33 are similarly recognized from the connection to the lower wiring, A design rule check can be performed for the distances d31 and d32 between the potential and the third wiring.

  Note that the potential is first recognized from the layout data is not limited to the potential of the well or the substrate, but may be any component having a different layout layer and shape depending on the design potential. For example, if a gate oxide film having a different data thickness depending on the gate voltage applied to the gate oxide film is used, the data layer of the gate oxide film can be recognized, The potential can also be recognized.

  Thus, according to the layout verification apparatus according to the present embodiment, the first verification unit 312 recognizes the potential with reference to the device structure (FEOL: Front End Of the Line) until the transistor is formed. Layout verification can be performed without individually defining voltages applied to a wiring structure (BEOL: Back End Of Line) forming a multilayer wiring.

  Conventionally, the voltage applied to the wiring is defined by inputting text data as character information for each wiring. Since this text data is generally defined for the pad metal that supplies power, the text data cannot be verified unless the layout up to the pad metal is completed. On the other hand, in the present embodiment, since definition by text data is not necessary, verification can be performed when the structure of the FEOL device is determined. Further, in this embodiment, since the potential can be recognized without inputting text data, it is possible to prevent the potential from being misidentified due to an input error of the text data.

Embodiment 2
Next, another embodiment of the present invention will be described. FIG. 9 shows a layout verification apparatus according to the present embodiment. The same circuit components as those of the first embodiment are denoted by the same reference numerals, and the description thereof is omitted as appropriate. The layout verification apparatus according to the second embodiment includes a second verification unit (LVS verification unit) 313 in addition to the first verification unit (DRC verification unit) 312. The second verification unit 313 is a part that recognizes a voltage applied to the pad and performs layout verification based on the voltage.

  The power information 308, the layout data 309 with power information, and the power connection verification unit 310 perform verification by LVS (Layout Versus Schematic). LVS is a comparison between a circuit restored from layout data using a circuit extraction system and a sample circuit at the time of design. Matching with the sample circuit or shorting of wiring between power supplies and between power supply and GND This is a system for detecting connection errors such as opening.

  The power supply information 308 is a part that holds information on the power supply voltage applied to the pad. The layout data 309 with power supply information is a portion that holds the layout data to which the power supply information input from the power supply information 308 is added to the layout data, and the potential information of the wiring and the region is recognized from the pad. The power connection verification unit 310 performs layout verification from the pad side by recognizing the semiconductor element and tracking the potential with respect to the layout data to which the power supply information recognized from the pad is added. The error location display unit 311 combines the error location verified by the power connection verification unit 310 with the layout data and displays it. This error location is fed back to the layout data.

  Next, the LVS verification method will be described. First, in the power supply information 308, a power supply potential or a signal potential connected to the wiring layer of the semiconductor device is set. Next, in the layout data with power supply information 309, the potentials of the wiring layer and the conductive layer are recognized based on the potential set in the wiring layer of the semiconductor device and associated with the layout data. Then, the power connection verification unit 310 verifies the layout reference of the semiconductor device based on the recognized wiring layer and the potential of the conductive layer.

  The first verification unit 312 performs layout verification by verifying the design rule with reference to the maximum value to which the potential is applied, whereas the second verification unit 313 performs verification with reference to the potential applied to the pad. Do. Therefore, the layout data to which the potential information obtained by the first verification unit 312 is added may not match the layout data to which the potential information obtained by the second verification unit 313 is added.

  Therefore, the layout data to which the potential information held in the layout data 309 with power supply information of the second verification unit 313 is added may be input to the first verification unit 312. Thus, the layout data to which the potential information obtained by the second verification unit 313 is added may be fed back to the first verification unit 312.

  Needless to say, the layout verification apparatus according to the first and second embodiments can be configured by a computer such as EWS and a program that causes the computer to function as the layout verification apparatus according to the first and second embodiments.

It is the figure which showed typically the semiconductor device 100 with which the layout verification method of this invention is applied. It is the figure which showed typically the cross section on the II-II line in FIG. 1 is a diagram illustrating a layout verification apparatus according to a first embodiment. It is a figure which shows the relationship between the power supply voltage of the element formed in a well, and the voltage applied to the diffusion layer formed in a well. It is a figure which shows the pattern of the tracking of a propagation path. It is a figure which shows the pattern of the tracking of a propagation path. It is a figure which shows the pattern of the tracking of a propagation path. It is a flowchart which shows the layout verification method of a 1st verification part. It is a figure which shows the layout verification apparatus of Embodiment 2. FIG.

Explanation of symbols

10 First region 11, 21 Tap region 12, 22, 32 Source / drain region 20 Second region 30 Third region 31 High concentration diffusion layer 100 Semiconductor device 301 Layout data holding unit 302 Mask creation processing unit 303 Mask data 303 Mask Data Holding Unit 304 Potential Recognition Processing Unit 305 Potential Propagation Processing Unit 306 Potential Dependent Design Criteria Verification Unit 307 Error Location Display Unit 308 Power Supply Information 309 Power Supply Information Layout Data 310 Power Connection Verification Unit 311 Error Location Display Unit 312 First Verification Unit 313 second verification unit 314 layout reference data holding unit 401, 403 N-type well 402 P-type well 404, 405, 406 Diffusion layer

Claims (6)

A potential recognition processing unit for recognizing the potential of the conductive layer based on the graphic data of the layout of the semiconductor device;
A layout verification apparatus comprising: a potential-dependent design standard verification unit that verifies a layout standard of the semiconductor device based on the recognized potential of the conductive layer.   The layout verification apparatus according to claim 1, wherein the potential recognition processing unit recognizes the potential of the conductive layer based on a substrate or well potential determined from the graphic data of the layout.   The layout verification apparatus according to claim 2, wherein the potentials of the plurality of conductive layers formed in an upper layer than the substrate or well are recognized in order from the lower conductive layer based on the potential of the substrate or well. Recognize the potential of the conductive layer based on the layout data of the semiconductor device,
A layout verification method for verifying a layout reference of the semiconductor device based on the recognized potential of the conductive layer.   5. The layout verification method according to claim 4, wherein the potential of the conductive layer is recognized based on the potential of the substrate or well determined from the graphic data of the layout.   The layout verification method according to claim 5, wherein the potentials of the plurality of conductive layers formed in an upper layer than the substrate or well are recognized in order from the lower conductive layer based on the potential of the substrate or well.

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