JP4787110B2 - Semiconductor device layout verification method - Google Patents

Description

  The present invention relates to a layout verification of a semiconductor device, and more particularly to a method for verifying wiring connection to a multi-layer well region in LVS verification (Layout Versus Chemical Consistency Check).

  Conventionally, when a semiconductor integrated circuit having a CMOS structure is formed on a silicon substrate, for example, when a P-type substrate is used, an N-type impurity is ion-implanted into a region where a P-channel transistor is to be formed. A mold region (N well region) is formed. In addition to the N-type region, a semiconductor device having a twin well structure in which an independent P-type region (P well region) is formed by introducing P-type impurities at different positions in the silicon substrate is also used. ing. Furthermore, in recent years, with the increasing functionality of devices, the need to form an independent P-well region has increased, so that in addition to an independent N-type region, the P-well region is electrically isolated from the P-type substrate. Thus, a semiconductor device having a triple well structure that obtains an independent P well region by forming a double well region having a two-layer structure formed by forming an N well region that surrounds the substrate has been increasingly used. In the triple well structure semiconductor device using an N-type substrate, in addition to an independent P-type region, a P-well region surrounding the N-well region so as to be electrically isolated from the N-type substrate is formed. Yes.

  When an element constituting a semiconductor integrated circuit is formed in a silicon substrate and a well region formed thereon, in order to stabilize the electrical operation of each element, the substrate voltage of the semiconductor substrate and the well voltage of each well region Must be fixed to an appropriate value. However, when designing a large-scale semiconductor integrated circuit in which the number of elements exceeds several million, there is a problem that the substrate voltage and well voltage are not fixed due to human error, or a problem that the voltage is fixed to the wrong voltage, etc. Is likely to occur. For this reason, conventionally, it is generally verified whether or not the substrate voltage and the well voltage are correctly fixed by a computer program.

  As a verification method that is generally used, there is LVS verification (see Layout Versus Chemical Consistency Check) (see, for example, Patent Document 1). LVS verification refers to an operation of checking whether or not a layout pattern has been created according to a circuit diagram by comparing a circuit diagram designed in consideration of electrical characteristics with a layout pattern. Specifically, LVS verification is performed by firstly netlist data obtained by extracting element information and net information from a circuit diagram, and netlist data obtained by extracting element information and net information from a layout pattern created based on the circuit diagram. And prepare. Then, the two data are compared using an LVS verification program to check the connection relationship. To create netlist data from a layout pattern, prepare a rule file that defines and describes the structure of each element such as an NMOS transistor, a PMOS transistor, a capacitor, a resistor, and a diode in advance, Each element is discriminated and extracted by calculation of a graphic identified by the layer described in the rule file. Then, net list data is created based on the element information and net information of the extracted elements.

  Here, FIG. 7 shows a partial circuit diagram of an integrated circuit including one P-channel transistor and one N-channel transistor. Specifically, the gate terminal PG of the P-channel transistor 21 is connected to the IN terminal, the source terminal PS and the back gate terminal PB are connected to the VDD terminal, the drain terminal PD is connected to the OUT terminal, and the gate terminal of the N-channel transistor 22 NG is connected to the IN terminal, the source terminal NS and the back gate terminal NB are connected to the GND / VSS terminal, and the drain terminal ND is connected to the OUT terminal. Note that the voltage at the VDD terminal is fixed to the power supply voltage. The voltage of the GND / VSS terminal is fixed to the ground voltage when the GND / VSS terminal functions as the GND terminal, and is fixed to the voltage VSS when the GND / VSS terminal functions as the VSS terminal. These voltages are defined in circuit diagram data and a verification rule file. In this integrated circuit, the configuration of the conventional circuit diagram is the same when the P-channel transistor 21 and the N-channel transistor 22 are formed using the twin well structure and when the triple channel structure is formed using the triple well structure. The layout pattern and the cross-sectional view thereof are different.

  First, LVS verification when forming an integrated circuit having a twin well structure based on the circuit diagram shown in FIG. 7 will be described with reference to FIGS. Here, FIGS. 8 and 9 show a layout pattern of an integrated circuit having a twin well structure generated from the circuit diagram shown in FIG. 7 and a cross-sectional view thereof. Note that the GND / VSS terminal in FIG. 7 functions as a GND terminal here.

  As shown in the layout pattern of FIG. 8 and the cross-sectional view of FIG. 9, an integrated N-well region WN is formed in the integrated circuit here. An N channel transistor is formed in the semiconductor substrate Psub as a P well region, and a P channel transistor is formed in the N well region WN formed on the semiconductor substrate Psub. The gate terminal NG, the source terminal NS, and the drain terminal ND of the N-channel transistor are formed in the P well region, and are connected to the IN terminal, the GND terminal, and the OUT terminal through the VIA and the metal wiring, respectively. The back gate terminal NB of the N-channel transistor formed of the P + diffusion region formed in the P well region is connected to the GND terminal via the VIA and the metal wiring. A gate terminal PG, a source terminal PS, and a drain terminal PD of the P-channel transistor are formed in the N well region WN, and are connected to the IN terminal, the VDD terminal, and the OUT terminal through the VIA and the metal wiring, respectively. . The back gate terminal PB of the P-channel transistor formed of the N + diffusion region formed in the N well region WN is connected to the VDD terminal via the VIA and the metal wiring. The voltage at the VDD terminal is fixed at the power supply voltage, and the voltage at the GND terminal is fixed at the ground voltage.

  In the above integrated circuit, LVS verification as to whether or not the voltage of each P well region and N well region is correctly fixed is performed by using netlist data extracted from the circuit diagram shown in FIG. The net list data extracted from the layout pattern shown and the cross-sectional view shown in FIG. 9 are compared.

  Specifically, in the circuit diagram shown in FIG. 7, since the back gate terminal NB of the N-channel transistor 22 is connected to the GND / VSS terminal, the voltage of the P well region is fixed to the ground voltage. Further, since the back gate terminal PB of the P-channel transistor 21 is connected to the VDD terminal, the voltage of the N well region WN is fixed to the power supply voltage. On the other hand, in FIGS. 8 and 9, since the back gate terminal NB of the N-channel transistor 22 is connected to the GND terminal via the VIA and the metal wiring, the voltage of the P well region is fixed to the ground voltage. I understand that. Further, since the back gate terminal PB of the P-channel transistor 21 is connected to the VDD terminal via the VIA and the metal wiring, it can be seen that the voltage of the N well region WN is fixed to the power supply voltage.

  Accordingly, the voltage values of the respective well regions in the circuit diagram shown in FIG. 7 are the same as the voltage values of the respective well regions in the layout pattern shown in FIG. 8 and the cross-sectional view shown in FIG. It can be verified from the circuit diagram that the layout pattern shown in FIG. 8 and the cross-sectional view shown in FIG. 9 are correctly generated.

JP 2002-343866 A

  Next, LVS verification in the case of forming an integrated circuit having a triple well structure (two-layer structure) will be described based on FIG. 2 and FIG. 3 based on the same circuit diagram of FIG. 2 and 3 show a layout pattern of an integrated circuit having a triple well structure generated from the circuit diagram of FIG. 7 and a cross-sectional view thereof. Note that the GND / VSS terminal in FIG. 7 functions as a VSS terminal here.

  As shown in the layout pattern of FIG. 2 and the cross-sectional view of FIG. 3, in the integrated circuit here, one independent N well region WN2 is formed on the semiconductor substrate Psub, and further formed on the semiconductor substrate Psub. A P well region WP is formed in the N well region WN1 so as to be electrically isolated from the semiconductor substrate by the N well region WN1. An N channel transistor is formed in the P well region WP formed in the N well region WN1, and a P channel transistor is formed in the N well region WN2. A gate terminal NG, a source terminal NS, and a drain terminal ND of the N-channel transistor are formed in the P well region WP, and are connected to the IN terminal, the VSS terminal, and the OUT terminal through the VIA and the metal wiring, respectively. . The back gate terminal NB of the N-channel transistor which is a P + diffusion region formed in the P well region WP is connected to the VSS terminal via the VIA and the metal wiring. Further, a well terminal NW composed of an N + diffusion region is formed in the N well region WN1, and is connected to the VCC terminal via the VIA and the metal wiring. A semiconductor substrate terminal BS composed of a P + diffusion region is formed on the semiconductor substrate Psub, and is connected to the GND terminal via the VIA and the metal wiring. The gate terminal PG, source terminal PS, and drain terminal PD of the P-channel transistor are formed in the N well region WN2, and are connected to the IN terminal, the VDD terminal, and the OUT terminal through the VIA and the metal wiring, respectively. ing. The back gate terminal PB of the P-channel transistor formed of the N + diffusion region formed in the N well region WN2 is connected to the VDD terminal via the VIA and the metal wiring. The voltage at the VDD terminal is fixed at the power supply voltage, the voltage at the VCC terminal is fixed at the voltage VCC, the voltage at the GND terminal is fixed at the ground voltage, and the voltage at the VSS terminal is fixed at the voltage VSS.

  In the integrated circuit having the triple well structure, LVS verification as to whether or not the voltage fixing of each P well region and the N well region is correctly performed is similar to the case of the integrated circuit having the twin well structure in FIG. The net list data extracted from the circuit diagram shown is compared with the net list data extracted from the layout pattern shown in FIG. 2 and the cross-sectional view shown in FIG.

  However, since the well terminal NW and the semiconductor substrate terminal BS are not shown in the circuit diagram of FIG. 7, LVS verification is performed to check whether the voltage of the N well region WN1 constituting the double well structure is correctly fixed. There is a problem that a mismatch error is output when LVS verification cannot be performed.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a circuit design method capable of verifying that voltage fixing of each well region is correctly performed in a semiconductor device having a multi-well structure. The point is to provide.

In order to achieve the above object, a circuit design method for a semiconductor device according to the present invention includes a first conductivity type semiconductor substrate, a second conductivity type first well region, and the first well region in the first well region. A circuit design method for a semiconductor device having a multi-well structure formed by forming a second well region of the first conductivity type formed so as to be electrically insulated and separated from the semiconductor substrate by a well region, In the circuit diagram of the semiconductor device, a first diode is provided between a well terminal provided in the first well region and a back gate terminal of the multi-well structure transistor with respect to the multi-well structure transistor provided in the second well region. was added and the second diode is added to the semiconductor substrate terminals provided on the semiconductor substrate between the well terminal, the multi-well structure transistor of drawing the circuit Is expressed using a 6-terminal structure cell having the well terminal, the semiconductor substrate terminal, the gate terminal, the source terminal, the drain terminal, and the back gate terminal, and the multi-well structure transistor is expressed using the 6-terminal structure cell. The 6-terminal structure cell extracting step for extracting the 6-terminal structure cell from the circuit diagram, and the extracted 6-terminal structure cell, the gate terminal, the source terminal, the drain terminal, and the back gate terminal, respectively. Replacing the first diode connected between the well terminal and the back gate terminal, and replacing the second diode connected between the well terminal and the semiconductor substrate terminal; It is characterized by performing.

  In order to verify the voltage fixation of each well region constituting a double well region having a two-layer structure, a diode is added to the circuit diagram, and a node indicating the double well region is represented on the circuit diagram, thereby The connection relation of each well region constituting the double well region can be expressed by. As a result, it becomes possible to verify the connection relation to each well region constituting the double well region between the circuit diagram and the layout pattern generated from the circuit diagram, and each well region constituting the two-layer structure. It is possible to correctly determine a wiring connection error for LVS verification.

  Further, when creating a circuit diagram, a circuit diagram is distinguished from a multi-well structure transistor formed in a double well region having a two-layer structure and a four-terminal transistor formed in a well region having a single layer structure or outside the well region. Once created, it becomes possible to automatically incorporate the nodes and diodes of each well region constituting the double well region into the circuit diagram without manual labor for the multi-well structure transistor, thereby reducing the labor and time required for adding the diode. This can reduce the time required for LVS verification.

  Embodiments of a circuit design method for a semiconductor device according to the present invention (hereinafter abbreviated as “method of the present invention” as appropriate) will be described below with reference to the drawings.

<First Embodiment>
A first embodiment of the method of the present invention will be described with reference to FIGS. The method of the present invention is formed on a semiconductor substrate of the first conductivity type so as to be electrically insulated from the semiconductor substrate by the first well region in the first well region and the first well region of the second conductivity type. In a semiconductor device having a multi-well structure formed by forming a second well region of the first conductivity type, the first well is compared with the multi-well structure transistor provided in the second well region on the circuit diagram of the semiconductor device. A first diode is added between the well terminal provided in the region and the back gate terminal of the multi-well structure transistor, and a second diode is added between the semiconductor substrate terminal provided on the semiconductor substrate and the well terminal. In the present embodiment, the case where the first conductivity type is P-type and the second conductivity type is N-type will be described.

  FIG. 1 shows a partial circuit diagram of an integrated circuit composed of one P-channel transistor and one N-channel transistor. Here, it is assumed that the P-channel transistor 21 is formed in the P-well region on the semiconductor substrate and the N-channel transistor 22 is formed in the double-well region. A diode P (corresponding to the first diode) and a diode N (corresponding to the second diode) indicating the connection relationship of the well regions constituting the structure are added. Specifically, the gate terminal PG of the P-channel transistor 21 is connected to the IN terminal, the source terminal PS and the back gate terminal PB are connected to the VDD terminal, the drain terminal PD is connected to the OUT terminal, and the gate terminal of the N-channel transistor 22 NG is connected to the IN terminal, the source terminal NS and the back gate terminal NB are connected to the VSS terminal, and the drain terminal ND is connected to the OUT terminal. Further, the anode of the diode P is connected to the back gate terminal NB of the N-channel transistor 22 and the cathode is connected to the well terminal NW formed on the N well region (corresponding to the first well region) constituting the double well region. The anode of the diode N is connected to the semiconductor substrate terminal BS and the cathode is connected to the well terminal NW. The well terminal NW is connected to the VCC terminal, and the semiconductor substrate terminal BS is connected to the GND terminal. The voltage at the VDD terminal is fixed at the power supply voltage, the voltage at the VCC terminal is fixed at the voltage VCC, the voltage at the GND terminal is fixed at the ground voltage, and the voltage at the VSS terminal is fixed at the voltage VSS.

  In the present embodiment, a diode P and a diode N indicating a connection relationship of each well region constituting the double well region are indicated on the circuit diagram, so that the connection relationship between the N well region WN1 and the semiconductor substrate Psub, and The connection relationship between the N well region WN1 and the adjacent P well region WP is shown in a circuit diagram, and the connection relationship between the well regions constituting the double well region can be verified by LVS.

  Next, a layout pattern generated using the circuit diagram shown in FIG. 1 and a cross-sectional view thereof will be described with reference to FIGS. Specifically, as shown in the layout pattern of FIG. 2 and the cross-sectional view of FIG. 3, one independent N well region WN2 is formed on the semiconductor substrate Psub, and further, N formed on the semiconductor substrate Psub. A P well region WP (corresponding to a second well region) formed so as to be electrically insulated from the semiconductor substrate by N well region WN1 is formed in well region WN1 (corresponding to the first well region). . An N channel transistor is formed in the P well region WP formed in the N well region WN1, and a P channel transistor is formed in the N well region WN2. A gate terminal NG, a source terminal NS, and a drain terminal ND of the N-channel transistor are formed in the P well region WP, and are connected to the IN terminal, the VSS terminal, and the OUT terminal through the VIA and the metal wiring, respectively. . The back gate terminal NB of the N-channel transistor which is a P + diffusion region formed in the P well region WP is connected to the VSS terminal via the VIA and the metal wiring. Further, a well terminal NW composed of an N + diffusion region is formed in the N well region WN1, and is connected to the VCC terminal via the VIA and the metal wiring. A semiconductor substrate terminal BS composed of a P + diffusion region is formed on the semiconductor substrate Psub, and is connected to the GND terminal via the VIA and the metal wiring. The gate terminal PG, source terminal PS, and drain terminal PD of the P-channel transistor are formed in the N well region WN2, and are connected to the IN terminal, the VDD terminal, and the OUT terminal through the VIA and the metal wiring, respectively. ing. The back gate terminal PB of the P-channel transistor formed of the N + diffusion region formed in the N well region WN2 is connected to the VDD terminal via the VIA and the metal wiring. This semiconductor device has the same configuration as the semiconductor device having the triple well structure in the LVS verification according to the prior art. The voltage at the VDD terminal is the power supply voltage, the voltage at the VCC terminal is the voltage VCC, and the voltage at the GND terminal is the ground. The voltage at the VSS terminal is fixed to the voltage VSS.

  Next, LVS verification of whether or not voltage fixing is correctly performed for each well region will be described. This LVS verification is performed by comparing the net list data extracted from the circuit diagram shown in FIG. 1 with the net list data extracted from the layout pattern shown in FIG. 2 and the cross-sectional view shown in FIG.

  Specifically, in the circuit diagram shown in FIG. 1, the back gate terminal NB of the N-channel transistor 22 is connected to the VSS terminal, so that the P well region WP is fixed to the voltage VSS. Further, since the well terminal NW is connected to the VCC terminal, the N well region WN1 is fixed to the voltage VCC. Since the back gate terminal PB of the P-channel transistor 21 is connected to the VDD terminal, the N well region WN2 is fixed to the power supply voltage. Furthermore, since the semiconductor substrate terminal BS is connected to the GND terminal, the semiconductor substrate Psub is fixed to the ground voltage.

  On the other hand, in the layout pattern shown in FIG. 2 and the cross-sectional view shown in FIG. 3, the back gate terminal NB of the N-channel transistor is connected to the VSS terminal via the VIA and the metal wiring. Is fixed at the voltage VSS. Further, since the well terminal NW formed in the N well region WN1 is connected to the VCC terminal via the VIA and the metal wiring, it can be seen that the voltage of the N well region WN1 is fixed to the voltage VCC. Since the back gate terminal PB of the P-channel transistor is connected to the VDD terminal via the VIA and the metal wiring, it can be seen that the voltage of the N well region WN2 is fixed to the power supply voltage. Furthermore, since the semiconductor substrate terminal BS is connected to the GND terminal via the VIA and the metal wiring, it can be seen that the voltage of the semiconductor substrate Psub is fixed to the ground voltage.

  Therefore, the voltage value of each well region in the circuit diagram shown in FIG. 1 is the same as the voltage value of each well region in the layout pattern shown in FIG. 2 and the cross-sectional view shown in FIG. It can be verified that the layout pattern shown in FIG. 2 and the cross-sectional view shown in FIG. If, for example, in the layout pattern shown in FIG. 2 and the cross-sectional view shown in FIG. 3, the well terminal NW formed in the N well region WN1 is connected to another terminal supplying the voltage VCC1. Since the voltage value of the N well region WN1 does not match the circuit diagram shown in FIG. 1, a mismatch error is output as a result of the LVS verification.

  2 and the cross-sectional view shown in FIG. 3, the diode P in the circuit diagram shown in FIG. 1 is located between the P well region WP and the N well region WN1, and the circuit diagram shown in FIG. It can be confirmed in the LVS verification that the diode N is located between the N well region WN1 and the semiconductor substrate Psub.

Second Embodiment
A second embodiment of the method of the present invention will be described with reference to FIGS. In the first embodiment, a circuit diagram is created without distinguishing between a multi-well structure transistor formed in a double well region and a normal four-terminal transistor, and each well region constituting the double well region is indicated. In this embodiment, a case where a multi-well structure transistor and a normal four-terminal transistor are distinguished from each other to create a circuit diagram will be described.

  In the present embodiment, the multi-well structure transistor on the circuit diagram is represented by using a six-terminal structure cell having a well terminal, a semiconductor substrate terminal, a gate terminal, a source terminal, a drain terminal, and a back gate terminal. Here, FIG. 4 is a schematic circuit diagram showing an example of a four-terminal transistor (N-channel transistor), and FIG. 5 is a schematic circuit diagram showing an example of a six-terminal structure cell (N-channel transistor). More specifically, the four-terminal transistor shown in FIG. 4 includes a gate terminal G, a source terminal S, a drain terminal D, and a back gate terminal B. The 6-terminal structure cell shown in FIG. 5 includes a well terminal W and a semiconductor substrate terminal BW in addition to the 4-terminal transistor shown in FIG. FIG. 6 is a partial circuit diagram showing an example of an integrated circuit using the four-terminal transistor 21 and the six-terminal structure cell 31.

  Next, a procedure for adding the first diode and the second diode when a circuit diagram is created using a 6-terminal structure cell and a 4-terminal transistor will be described. In the present embodiment, the method of the present invention is configured to be executed by application software executed on computer hardware, and a program for realizing each processing step of the method of the present invention by software processing. Is executed on the computer.

  In the method of the present invention, first, a 6-terminal structure cell is extracted from the circuit diagram shown in FIG. 6 in which a multi-well structure transistor is represented using a 6-terminal structure cell (6-terminal structure cell extraction step). Subsequently, the extracted 6-terminal structure cell includes a 4-terminal transistor having a gate terminal, a source terminal, a drain terminal, and a back gate terminal, a first diode connected between the well terminal and the back gate terminal, Replacement with a second diode connected between the well terminal and the semiconductor substrate terminal (replacement step). Here, the six-terminal structure cell 31 shown in FIG. 6 is replaced with a four-terminal transistor 22, a diode P, and a diode N. By performing this replacement step, the circuit diagram shown in FIG. 1 is generated from the circuit diagram shown in FIG. When a plurality of transistors are formed in the same double well region, the back gate terminals B of the plurality of transistors formed in the double well region are connected to one electrode of a common first diode, and the first The other terminal of one diode and the well terminal W are connected. A second diode is connected between the well terminal W and the semiconductor substrate. As a result, a plurality of diodes are described for the well regions constituting the same double well region, thereby preventing an error from being detected.

  Subsequently, a circuit diagram (FIG. 1) in which the 6-terminal structure cell 31 is replaced with a 4-terminal transistor 22, a diode P and a diode N, the layout pattern shown in FIG. 2, and the cross-sectional view shown in FIG. LVS verification is performed to determine whether the voltage is fixed correctly. The LVS verification procedure is the same as that in the first embodiment.

<Another embodiment>
In the first and second embodiments, the case where the first conductivity type is P type and the second conductivity type is N type has been described. However, the first conductivity type is N type and the second conductivity type is P type. The method of the present invention may be applied to a semiconductor device.

1 is a partial circuit diagram illustrating an example of a circuit diagram created by a circuit design method for a semiconductor device according to the present invention; Schematic showing an example of the layout pattern of a semiconductor device having a triple well structure Sectional drawing which shows an example of the semiconductor device of a triple well structure FIG. 1 is a schematic circuit diagram showing a schematic configuration of a four-terminal transistor used in a circuit design method for a semiconductor device according to the present invention and a circuit design method for a semiconductor device according to the prior art. 1 is a schematic circuit diagram showing a schematic configuration of a 6-terminal structure cell used in a circuit design method for a semiconductor device according to the present invention. The partial circuit diagram which shows an example of the circuit diagram produced using the 6 terminal structure cell in the circuit design method of the semiconductor device which concerns on this invention Partial circuit diagram showing an example of a circuit diagram used in a circuit design method for a semiconductor device according to the prior art Schematic showing an example of the layout pattern of a semiconductor device having a twin well structure Sectional drawing which shows an example of the semiconductor device of a twin well structure

Explanation of symbols

21 P-channel transistor 22 N-channel transistor 31 6-terminal structure cell P, N diodes NG, PG, G gate terminals NS, PS, S source terminals ND, PD, D drain terminals NB, PB, B back gate terminal NW, W well terminal BS Semiconductor substrate terminal WP P well region WN N well region

Claims (1)

The first conductivity type semiconductor substrate is formed on the second conductivity type first well region, and is electrically isolated from the semiconductor substrate by the first well region in the first well region. A circuit design method for a semiconductor device having a multi-well structure formed by forming a second well region of the first conductivity type,
In the circuit diagram of the semiconductor device, with respect to the multi-well structure transistor provided in the second well region, a first is provided between the well terminal provided in the first well region and the back gate terminal of the multi-well structure transistor. Adding a diode, adding a second diode between a semiconductor substrate terminal provided on the semiconductor substrate and the well terminal ;
The multi-well structure transistor on the circuit diagram is represented using a 6-terminal structure cell having the well terminal, the semiconductor substrate terminal, the gate terminal, the source terminal, the drain terminal, and the back gate terminal,
A 6-terminal structure cell extracting step for extracting the 6-terminal structure cell from the circuit diagram representing the multi-well structure transistor using the 6-terminal structure cell;
The extracted 6-terminal structure cell is connected to the 4-terminal transistor having the gate terminal, the source terminal, the drain terminal, and the back gate terminal, and the well terminal and the back gate terminal, respectively. A circuit design method comprising: performing a first diode and a replacement step of replacing with the second diode connected between the well terminal and the semiconductor substrate terminal .