JP2009146054A - Layout creation device and layout creation method for semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a layout creation device and layout creation method of a semiconductor integrated circuit for changing the process of layout verification processing for verifying a plurality of layered layout data as necessary, and for reducing the labor of layout verification processing, and for improving the quality of layout data based on a manufacturing process for manufacturing a semiconductor device with a multi-layered structure. <P>SOLUTION: The layout creation device of a semiconductor integrated circuit is provided with: a logic circuit diagram designing part; a layout data creation part; a logical connection verification part; a design rule verification part; an inter-layer layout verification part; a data output part for outputting layout data; and a verification process setting part for setting a process for verification processing to be executed by the logic connection verification part, the design rule verification part and the inter-layer layout verification part based on a manufacturing process in the case of integrating the semiconductor integrated circuit with a multi-layered structure into chips. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a layout creation apparatus and layout creation method for creating a layout of a semiconductor integrated circuit.

  At the design stage of the semiconductor integrated circuit, a logic circuit diagram is designed based on the circuit specification information, and layout data is created based on the logic circuit diagram. The created layout data is verified (hereinafter referred to as “layout check”) as to whether or not it has been correctly designed according to the design rule intended by the designer.

The layout check is a DRC (Design Rule Checking) that verifies whether or not a geometric design rule determined by the constraints of the manufacturing equipment is violated. Using an EDA (Electronic Design Automation) tool such as LVS (Layout Versus Schematic) for verifying whether information is correctly realized in layout data or ERC (Electronic Rule Check) for verifying the electrical connection of a logic circuit diagram Done. The layout data is completed only when no error is detected in the verification by DRC, LVS or the like.
JP-A-3-171648

  The present invention appropriately changes the layout verification process for verifying layout data of a plurality of layers based on a manufacturing process for manufacturing a semiconductor device having a multilayer structure, reduces the burden of layout verification processing, and improves the quality of layout data. A semiconductor integrated circuit layout creation apparatus and layout creation method are provided.

A semiconductor integrated circuit layout creating apparatus according to an embodiment of the present invention includes:
A logic circuit diagram design unit for designing a logic circuit diagram based on specification information of a semiconductor integrated circuit;
A layout data creation unit for creating layout data for each layer of a semiconductor integrated circuit having a multilayer structure based on the designed logic circuit diagram;
Information on the connection between the elements is extracted from the created layout data for each layer, and whether or not the information on the logic circuit diagram matches the information on the extracted elements and the information on the connections between the elements. A logical connection verification unit that verifies and generates the result;
Whether the created layout data for each layer violates the design rule extracted from the specification information of the semiconductor integrated circuit based on the information extracted in the logical connection verification unit and the connection between the elements And a design rule verification unit that generates the verification result,
The position of the element and the connection position between the elements are compared between the layout data of different layers among the plurality of layout data for each layer, and the positional deviation of the position of the element and the connection position between the elements is verified. An interlayer layout verification unit that generates the verification result,
A data output unit for outputting layout data created by the layout data creation unit;
A verification process for setting a verification process executed in the logical connection verification unit, the design rule verification unit, and the interlayer layout verification unit based on a manufacturing process when the semiconductor integrated circuit having the multilayer structure is formed into a chip. A setting unit.

A method for creating a layout of a semiconductor integrated circuit according to an embodiment of the present invention includes:
Designing a logic circuit diagram based on the specification information of the semiconductor integrated circuit;
Creating layout data for each layer of a semiconductor integrated circuit having a multilayer structure based on the designed logic circuit diagram;
Information on the connection between the elements is extracted from the created layout data for each layer, and whether or not the information on the logic circuit diagram matches the information on the extracted elements and the information on the connections between the elements. Verifying and generating the results;
Whether the created layout data for each layer violates the design rule extracted from the specification information of the semiconductor integrated circuit based on the information extracted in the logical connection verification unit and the connection between the elements And generating the verification result,
The position of the element and the connection position between the elements are compared between the layout data of different layers among the plurality of layout data for each layer, and the positional deviation of the position of the element and the connection position between the elements is verified. Generating the verification result, and
Outputting layout data created by the layout data creation unit;
Setting a process of verification processing executed in the logical connection verification unit, the design rule verification unit, and the interlayer layout verification unit based on a manufacturing process when the semiconductor integrated circuit having the multilayer structure is formed into a chip; and Have.

  According to the present invention, when manufacturing a semiconductor device having a multilayer structure, in addition to layout verification processing by DRC and LVS applied to layout data of each layer, layout by LVL is applied to mask creation data of adjacent layers. By applying the verification process, it is possible to provide a layout creation apparatus for a semiconductor integrated circuit that improves the accuracy of the layout verification process and further improves the quality of the layout design data.

  Hereinafter, a layout creation apparatus and a layout creation method for a semiconductor integrated circuit according to an embodiment of the present invention will be described in detail with reference to the drawings. In the embodiment, an example of a layout creation apparatus and layout creation method for a semiconductor integrated circuit according to the embodiment of the present invention is shown, and a layout creation apparatus and layout creation for a semiconductor device according to the embodiment of the present invention are shown. The method is not limited to those embodiments.

(First embodiment)
In the first embodiment, in the manufacture of a semiconductor device having a multi-layer structure, layout verification processing by LVL (Layout Versus Layout) is performed on layout data of two adjacent layers among layout data created for each layer. A case will be described in which the layout verification processing by the DRC and the LVS is executed on the layout data after the layout verification, and the layout verification processing is executed for each of a plurality of layers.

  FIG. 1 is a block diagram showing a configuration example of a layout creating apparatus according to the first embodiment of the present invention. As shown in FIG. 1, the layout creating apparatus 20 according to the first embodiment includes a logic circuit diagram design unit 30 that designs a logic circuit diagram based on specification information 10 of a semiconductor integrated circuit, and a logic circuit diagram design unit. 30, a layout data creation unit 40 that creates layout data based on information of the logic circuit diagram designed by 30, a layout data verification unit 50, a verification process setting unit 80, a data input / output unit (data output unit) 90, . Also, outside the layout creation apparatus 20, an LVL verification unit (interlayer layout verification unit) 100 that executes LVL between the layout data of two adjacent layers, and mask creation data for photomask manufacturing are created from the layout data A mask creation data creation unit 110 for manufacturing, a photomask manufacturing apparatus 120 for manufacturing a photomask for each layer based on the mask creation data for each layer after execution of LVL, and a semiconductor device based on the manufactured photomask for each layer And a semiconductor device manufacturing apparatus 130.

  The layout data verification unit 50 includes an LVS verification unit (logical connection verification unit) 60 and a DRC verification unit (design rule verification unit) 70.

  The LVS verification unit 60 executes LVS, restores the gate level connection information from the layout data, further converts the gate level connection information into the transistor level connection information, and then converts the transistor level connection information and the logic circuit diagram. Check whether or not the information matches.

  The DRC verification unit 70 executes DRC, the width of the graphic to be verified from the layout data, the distance between the two graphics, and the standard value (allowable minimum / maximum) when a certain graphic is included in another graphic. A design rule such as (interval value) is recognized, and it is determined whether or not the figure width and space of the layout data satisfy the design rule.

  The verification process setting unit 80 sets a process of verification processing executed in the LVS verification unit 60, the DRC verification unit 70, and the LVL verification unit 100 based on a manufacturing process when a semiconductor device having a multilayer structure is formed into a chip. The setting information is set in the LVS verification unit 60, the DRC verification unit 70, and the LVL verification unit 100. For example, the verification process setting unit 80 sets a layer that divides layout data for each of a plurality of layers to be verified, and sets a verification process according to the divided layer. Set the output timing of the error location report to be extracted.

  The LVL verification unit 100 outputs an error location report to the data input / output unit 90 when an error location is extracted when executing LVL between the layout data of two adjacent layers. The data input / output unit 90 outputs the layout data input from the layout data creation unit 40 to the LVL verification unit 100, and outputs the error location report input from the LVL verification unit 100 to the layout data creation unit 40. Execute.

  Next, the layout data creation processing executed in the layout creation device 20 of the first embodiment will be described with reference to the flowchart shown in FIG. 2 and the layout examples shown in FIGS. In the flowchart shown in FIG. 2, each layout verification process (including the error location report output timing) executed by the LVS verification unit 60, the DRC verification unit 70, and the LVL verification unit 100 includes a verification process setting unit. This is based on the setting information set in advance by 80.

  First, the specification of the semiconductor integrated circuit is determined based on the semiconductor integrated circuit specification information (step S101), and the logic circuit diagram design unit 30 creates a circuit diagram based on this specification (step S102). Next, the layout data creation unit 40 creates layout data N corresponding to each layer (where N = 1, 2, 3,...) In order to create the created circuit diagram as chip data of an actual multilayer structure N. , N-1, and N) (step S103). The layout data creation unit 40 includes a layout of a plurality of layers including up to the first layer (for example, up to the first layer including the poly layer 11 and the diffusion layer 12 shown in FIG. 3) among the created layout data for N layers. Data is output to the data input / output unit 90. The layout data up to the first layer is output from the data input / output unit 90 to the LVL verification unit 100.

  In this case, the first layer including the poly layer 11 and the diffusion layer 12 shown in FIG. 3 is used as the first layer for dividing the verification process based on the manufacturing process when the semiconductor integrated circuit is formed into a chip. Yes. The layer that divides the verification process is set by the verification process setting unit 80. That is, if at least an LVL verification process between the poly layer 11 and the diffusion layer 12 and a DRC verification process are performed in advance for each layer of the poly layer 11 and the diffusion layer 12 and an error part is extracted, the layer related to the wiring Is not included in the layout verification target, the LVS verification processing and the wiring layer DRC verification processing can be omitted.

  An example of the layout of the multi-layered semiconductor integrated circuit created in step S103 is shown in FIG. FIG. 3 is a plan view showing a layout of a memory transistor region when a flash memory is applied as a semiconductor integrated circuit. In this memory transistor region, the first layer layout (solid line) including the poly layer 11 and the diffusion layer 12, the second layer including the wiring layer A 13, the wiring layer B 14, and the contact layer 15. Layout (solid and dotted lines). In this case, using the first layer mask creation data 1 created based on the first layer layout and the second layer mask creation data 2 created based on the second layer layout, A second semiconductor integrated circuit and a second semiconductor integrated circuit are manufactured. Thereafter, the second semiconductor integrated circuit is overlaid on the upper layer of the first semiconductor integrated circuit, and the wiring layer A13, the wiring layer B14, and the contact layer 15 are connected to the position where the diffusion layer 12 is formed. FIG. 3 shows an image of the layout data of the second layer to be created next after completing the layout data up to the poly layer 11 and the diffusion layer 12 based on the layout of the first layer.

  FIG. 4 shows layout data obtained by completing the wiring layer A13, the wiring layer B14, and the contact layer 15 based on the layout of the second layer, and an image of the layout data of the first layer of FIG. ing. As shown in FIGS. 3 and 4, when a semiconductor integrated circuit having a multilayer structure is completed from a lower layer mask, the lower layer mask creation data created earlier is compared with the adjacent upper layer mask creation data. Therefore, it is necessary to confirm that the position of the lower layer has not moved. For this reason, in the first embodiment, a layout verification process using LVL, which will be described later, is executed in the LVL verification unit 100 in FIG.

  In the example in which the layouts of the first layer and the second layer shown in FIG. 4 are overlapped, the layout of the first layer is different from the layout of the first layer shown in FIG. In this case, it is impossible to connect the second wiring layer A13, the wiring layer B14, and the contact layer A15 with the layout of the first layer in FIG. In other words, in the layout of the first layer and the layout of the second layer, when only the layout in each layer is checked for layout by DRC and LVS, the error part is not extracted, and the error part is connected to the interlayer connection when each layer is overlaid. This suggests that there is a possibility of occurrence. For this reason, in the first embodiment, it is necessary to execute an LVL process to be described later between layout data of adjacent layers.

  Next, returning to FIG. 2, the processing after step S104 will be described. In step S104, the LVL verification unit 100 holds the layout data of the first layer input from the layout data creation unit 40, and the layout data included in the layout data up to the first layer (up to the first layer). Determine if it is data. If the layout data is included in the first layer (step S104: Yes), the process proceeds to step S105. If the layout data is not included in the first layer (step S104: No), the process proceeds to step S109.

  In step S <b> 105, the LVL verification unit 100 executes LVL comparison processing of the lower layer layout data (poly layer 11) and the upper layer layout data (diffusion layer 12) among the stored layout data included in the first layer. . In this LVL comparison process, the difference between the lower layer layout data and the upper layer layout data is output, and whether or not the position of the layout data of the first layer has been moved is determined from this difference, and the presence or absence of an error portion is determined. To do. The layout data determined by the LVL verification unit 100 as having an error holds the error location report (step S106).

  Subsequently, in step S105, when the LVL verification unit 100 determines that there is no error in the LVL comparison processing between the layout data included in the first layer, the LVL comparison unit 100 outputs each layout data for which the LVL comparison processing is completed as data input / output. Output to the unit 90.

  Each layout data for which the LVL comparison processing has been completed in step S105 is output from the data input / output unit 90 to the layout data creation unit 40. Further, each layout data input to the layout data creation unit 40 is output to the DRC verification unit 70, and layout verification processing by DRC is executed in step S107.

  Next, in step S107, the DRC verification unit 70 first extracts a figure related to the element and the wiring from each layout data of the poly layer 11 and the diffusion layer 12 included in the first layer shown in FIG. One or more design rules are selected and DRC is executed to determine whether there is an error location.

  In step S107, the DRC verification unit 70 executes the DRC on each layout data of the first layer, and as a result, layout data (one or both of the poly layer 11 and the diffusion layer 12) determined to have an error is the error location report. Is held (step S108). In addition, the DRC verification unit 70 determines that there is no error as a result of performing DRC on each layout data included in the first layer, and when DRC ends, for each layout data included up to the last N layers. A process transition instruction signal for instructing transition to the layout verification process is output to the layout data creation unit 40.

  When the process transition instruction signal is input, the layout data creating unit 40 extends from the first layer to the final N layer (for example, up to the second layer including the wiring layers A13 and B14 and the contact layer 15 shown in FIG. 3). Each included layout data is output to the data input / output unit 90. Each layout data included in the second layer is output from the data input / output unit 90 to the LVL verification unit 100. In step S104, the LVL verification unit 100 holds each layout data of the second layer input from the layout data creation unit 40, and determines whether each layout data is layout data included up to the first layer. If the layout data is not included up to the first layer, that is, if the layout data is included from the first layer to the last N layers (step S104: No), the process proceeds to step S109.

  In step S109, the LVL verification unit 100 applies the same LVL as in step S105 to the layout data (the layout data of the wiring layers A13 and B14 and the contact layer 15 in FIG. 3) included in the held second layer. Repeat the comparison process. When the LVL verification unit 100 determines that there is an error as a result of the LVL comparison process, the LVL verification unit 100 holds an error location report (step S110), and inputs each layout data of the second layer for which the LVL comparison process is completed. Output to the output unit 90. If the LVL verification unit 100 determines that there is no error in the LVL comparison process between the layout data included in the second layer, the LVL verification unit 100 outputs each layout data for which the LVL comparison process has been completed to the data input / output unit 90. .

  Each layout data for which the LVL comparison processing has been completed is output from the data input / output unit 90 to the layout data creation unit 40. Further, each layout data input to the layout data creation unit 40 is output to the DRC verification unit 70 and the LVS verification unit 60, and layout verification processing by DRC and LVS is executed in step S111.

  Next, in step S111, the DRC verification unit 70 extracts a figure related to the element and the wiring from each layout data of the wiring layers A13 and B14 and the contact layer 15 included in the second layer shown in FIG. One or more design rules are selected and DRC is executed to determine whether there is an error location. In step S111, the LVS verification unit 60 performs LVS on each layout data. The LVS verifying unit 60 restores the gate level connection information from the layout data of the wiring layers A13, B14 and the contact layer 15, and further converts the gate level connection information into the transistor level connection information. Whether or not there is an error is determined by checking whether or not the connection information in FIG.

  In step S111, the DRC verification unit 70 and the LVS verification unit 60 execute the DRC and LVS for each layout data, and as a result of executing layout data (either of the wiring layers A13 and B14 or the contact layer 15) that both or one of them determines as having an error. 1, 2, or all) outputs an error location report output instruction to the layout data creation unit 40 together with the error location report. This error location report output instruction is output from the layout data creation unit 40 to the LVL verification unit 100 via the data input / output unit 90. When the error location report output instruction is input, the LVL verification unit 100 outputs the previously stored error location report to the data input / output unit 90. This error location report is output to the layout data creation unit 40 via the data input / output unit 90. Therefore, in the first embodiment, the error location determined by the LVL verification unit 100 and the error location determined by the DRC verification unit 70 and the LVS verification unit 60 are collectively generated as an error location report. The data is output to the unit 40 (step S112).

  Next, the layout data creation unit 40 confirms the error location report and corrects the error location of each layout data included in the first and second layers (step S113). Thereafter, the processing of step S103 to step S113 is repeatedly executed until there is no error portion. In this case, the layout data creation unit 40 confirms the error location report and corrects the layout data of the corresponding layer (step S113). Therefore, when it is determined by the LVL comparison processing that there is an error portion in the lower layer layout data, the layout data can be corrected so that the relative position with the upper layer layout data matches. That is, for example, the position of the diffusion layer 12 of the first layout data shown in FIG. 4 is corrected so as to match the positions of the wiring layer A13, the wiring layer B14, and the contact layer 15 of the second layout data. Is possible.

  Then, the processing of step S103 to step S113 is repeatedly executed until there is no error portion. When it is determined in step S105, step S107, step S109, and step S111 that the layout data of all the layers has no error, 1 Layout data for the N layers from the layer to the final N layers is completed (step S114), and chip data for the N layers is completed (step S115). The layout data creation unit 40 outputs the completed chip data for N layers to the data input / output unit 90. Chip data for N layers is output from the data input / output unit 90 to the mask creation data creation unit 110.

  Next, the mask creation data creation unit 110 creates mask creation data 1 to N corresponding to each layer based on chip data for N layers (step S116). Next, the mask creation data creation unit 100 determines whether or not creation of mask creation data for all layers has been completed (step S117). If it is determined that the creation of the mask creation data for all layers has not been completed (step S117: No), a layout data creation instruction for the next layer is output to the data input / output unit 90. This layout data creation instruction is output from the data input / output unit 90 to the layout data creation unit 40. In this case, the processes in steps S103 to S115 are executed again. Also, the mask creation data creation unit 100 outputs all the mask creation data N to the photomask manufacturing apparatus 120 when the creation of the mask creation data for all the layers has been completed (step S117: Yes). Therefore, by repeatedly executing the processes in steps S103 to S117, the layout verification process is performed by applying LVL to the layout data of adjacent layers, and then DRC, It is possible to execute layout verification processing by applying LVS. In addition, the layout verification process is executed by applying LVL to the layout data of all N layers up to the first layer (up to the first layer), and then to the first layer (the first layer). The layout verification process was executed by applying DRC to the layout data. Furthermore, after the layout verification process is executed by applying LVL to the remaining layout data up to the final N layer (up to the second layer), the layout data up to the final N layer (up to the second layer) The layout verification process is executed by applying DRC and LVS.

  Next, the photomask manufacturing apparatus 120 manufactures a photomask for each layer having a mask pattern of each layer using an EB drawing apparatus or the like based on the mask creation data 1 to N (step S118). Next, the semiconductor device manufacturing apparatus 130 forms a semiconductor integrated circuit pattern or the like on the substrate using the photomask of each layer manufactured by the photomask manufacturing apparatus 120 to manufacture the semiconductor device (step S119). After manufacturing the semiconductor device, the process of the first embodiment is finished.

  Next, a method for manufacturing the semiconductor device according to the first embodiment will be described. In the semiconductor device manufacturing method according to the first embodiment of the present invention, the mask pattern is formed based on the layout data for each layer whose layout is verified and the layout data whose relative position between adjacent layers is verified. It includes a lithography process in which a pattern is transferred onto a substrate using a photomask or a lithography process in which a layout data is directly drawn on a substrate by a processing apparatus using an electron beam or the like. In other words, in the method for manufacturing a semiconductor device according to the first embodiment of the present invention, the mask creation data creation unit 100 uses the layout data of each layer created by the layout creation device 20 to verify the layout. Mask creation data is created. The mask creation data of each layer is subjected to LVL comparison processing between layout data of adjacent layers in the LVL verification unit 100, and the relative position between the layout data is verified. Subsequently, in the mask creation data creation unit 110, mask creation data for each layer is created using the layout data for each layer whose relative position has been verified. Then, in the photomask manufacturing apparatus 120, the mask pattern of each layer is formed on the photomask using the mask creation data of each layer whose relative position has been verified. Using this photomask for each layer, the semiconductor device manufacturing apparatus 130 forms a pattern of a semiconductor integrated circuit on the substrate for each layer by exposure. Alternatively, in the method of manufacturing a semiconductor device according to the first embodiment of the present invention, the layout data of each layer may be drawn directly on the substrate by a processing device such as an electron beam to form a pattern. Good. The substrate (semiconductor substrate) used in the above steps is usually formed with functional elements such as transistors and diodes in advance. Further, a metal wiring layer such as polysilicon or tungsten is formed before or after the pattern transfer step or the processing using an electron beam or the like. A desired metal wiring can be obtained by processing this wiring layer by the above pattern transfer process or processing using an electron beam or the like. Usually, a plurality of such metal wiring layers are formed while repeating the above-described steps. Usually, an insulating film is provided between these metal wiring layers. Further, the wiring layers on both sides sandwiching the insulating film obtain a mutual electrical connection by forming a connection conductor at a desired location of the insulating film. With the above manufacturing method, a pattern can be formed on a substrate based on layout data with improved reliability. As a result, a semiconductor integrated circuit including various fine semiconductor elements incorporated in the semiconductor device can be formed with high accuracy. Therefore, according to this method for manufacturing a semiconductor device, it is possible to improve the reliability and yield of the semiconductor device.

  As described above, according to the first embodiment of the present invention, after performing layout verification processing by LVL on the layout data of adjacent layers and determining the presence / absence of an error location in the lower layer layout data, It is possible to execute layout verification processing by DRC and LVS on the layout data of each layer to determine the presence / absence of an error location, to output an error location report at once, and to re-correct the layout data did.

  Therefore, when manufacturing a semiconductor device having a multi-layer structure, in addition to layout verification processing by DRC and LVS applied to layout data of each layer, layout verification processing by LVL is applied to layout data of adjacent layers. can do. As a result, the accuracy of the layout verification process can be improved, and the quality of the layout design data can be further improved.

  Further, according to the first embodiment of the present invention, the error location determined by the layout verification processing using LVL and the error location determined by the layout verification processing using DRC and LVS are collectively processed. Since it is output as an error location report, it is possible to reduce the man-hour for correcting errors in the layout data.

  Furthermore, according to the first embodiment of the present invention, the layout data of all N layers is transferred to the first layer (first layer) based on the manufacturing process when the semiconductor integrated circuit having a multilayer structure is formed into a chip. And the remaining final N layers (up to the second layer) are divided into layout data, and the layout verification processing is executed by applying LVL to each of the divided layout data of the plurality of layers. The layout verification process is executed by appropriately applying DRC and LVS to the layout data.

  For this reason, compared with the case where the layout verification process is executed for each layer without dividing the layout data of all N layers, the processing load of the layout verification process can be reduced. That is, in the first embodiment, the wiring shown in FIG. 3 is used up to the first layer including the ply layer 11 and the diffusion layer 12 shown in FIG. 3 and up to the final N layer up to the first layer. The case where the LVL verification process, the DRC verification process, and the LVS verification process are appropriately executed by dividing into the second layer including the layer 14 and the contact layer 15 is shown. As a result, in the layout verification process up to the first layer, it is only necessary to execute the DRC verification process after executing the LVL verification process, and the processing load of the layout verification process can be reduced.

(Second Embodiment)
In the second embodiment, in manufacturing a semiconductor device having a multilayer structure, layout verification processing by DRC and LVS is performed on layout data created for each layer, and the layout data after layout verification is adjacent to the layout data. A case will be described in which layout verification processing by LVL is executed on the layout data of two layers, and these layout verification processing is executed for each of a plurality of layers.

  Since the configuration of the layout creating apparatus according to the second embodiment is the same as that shown in FIG. 1, the illustration and description of the configuration are omitted.

  Next, the layout data creation processing executed in the layout data creation device 20 of the second embodiment will be described with reference to the flowchart shown in FIG. 5 and the layout examples shown in FIGS. In the flowchart shown in FIG. 5, each layout verification process (including the output timing of the error location report) executed by the LVS verification unit 60, the DRC verification unit 70, and the LVL verification unit 100 is a verification process setting unit. This is based on the setting information set in advance by 80.

  First, the specification of the semiconductor integrated circuit is determined based on the semiconductor integrated circuit specification information 10 (step S201), and the logic circuit diagram design unit 30 creates a circuit diagram based on this specification (step S202). Next, the layout data creation unit 40 creates layout data N corresponding to each layer (where N = 1, 2, 3,...) In order to create the created circuit diagram as chip data of an actual multilayer structure N. , N-1, and N) (step S203). The layout data creation unit 40 includes a layout of a plurality of layers including up to the first layer (for example, up to the first layer including the poly layer 11 and the diffusion layer 12 shown in FIG. 3) among the created layout data for N layers. The data is output to the layout data verification unit 50. The layout data up to the first layer is input to the DRC verification unit 70 in the layout data verification unit 50.

  In this case, the first layer including the poly layer 11 and the diffusion layer 12 shown in FIG. 3 is used as the first layer for dividing the verification process based on the manufacturing process when the semiconductor integrated circuit is formed into a chip. Yes. The layer that divides the verification process is set by the verification process setting unit 80. That is, if at least the DRC verification process and the LVL verification process between the poly layer 11 and the diffusion layer 12 are performed in advance for each of the poly layer 11 and the diffusion layer 12 and the error part is extracted, the layer related to the wiring Is not included in the layout verification target, the LVS verification processing and the wiring layer DRC verification processing can be omitted.

  In step S204, the DRC verification unit 70 holds each layout data of the first layer input from the layout data creation unit 40, and each layout data is included in the layout up to the first layer (up to the first layer). Determine if it is data. If the layout data is included in the first layer (step S204: Yes), the process proceeds to step S205. If the layout data is not included in the first layer (step S204: No), the process proceeds to step S209.

  Next, in step S205, the DRC verification unit 70 executes DRC for each layout data of the first layer. In step S205, the DRC verification unit 70 first extracts a figure related to the element and the wiring from each layout data of the poly layer 11 and the diffusion layer 12 included in the first layer shown in FIG. One or more design rules are selected and DRC is executed to determine the presence or absence of an error location.

  In step S205, the DRC verification unit 70 executes the DRC on each layout data of the first layer, and as a result, layout data (one or both of the poly layer 11 and the diffusion layer 12) determined to have an error is the error location report. Is held (step S206). Also, the DRC verification unit 70 determines that there is no error as a result of performing DRC on each layout data included in the first layer. When the DRC is terminated, each layout data for which the layout verification processing has been completed is determined as layout data. The data is output to the creation unit 40.

  Each layout data for which the layout verification processing has been completed is output from the layout data creation unit 40 to the data input / output unit 90. Further, each layout data input to the data input / output unit 90 is output to the LVL verification unit 100. Each layout data of the first layer input to the LVL verification unit 100 is subjected to layout verification processing by LVL in step S207.

  In step S207, the LVL verification unit 100 executes LVL comparison processing of the lower layout data (poly layer 11) and the upper layout data (diffusion layer 12) among the stored layout data included in the first layer. . In this LVL comparison process, the difference between the lower layer layout data and the upper layer layout data is output, and whether or not the position of the layout data of the first layer has been moved is determined from this difference, and the presence or absence of an error portion is determined. To do. The layout data that the LVL verification unit 100 determines to have an error holds the error location report (step S208).

  Subsequently, in step S207, when the LVL verification unit 100 determines that there is no error in the LVL comparison processing between the layout data included in the first layer, the layout for each layout data included up to the remaining final N layers. A process transition instruction signal for instructing the transition to the verification process is output to the data input / output unit 90. This processing transition instruction signal is output from the data input / output unit 90 to the layout data creation unit 40.

  When the process transition instruction signal is input, the layout data creating unit 40 extends from the first layer to the final N layer (for example, up to the second layer including the wiring layers A13 and B14 and the contact layer 15 shown in FIG. 3). Each included layout data is output to the layout data verification unit 50. Each layout data included up to the last N layers is input to the DRC verification unit 70 and the LVS verification unit 60 in the layout data verification unit 50. In step S204, the DRC verification unit 70 and the LVS verification unit 60 hold each layout data input from the layout data creation unit 40, and determine whether the layout data is layout data included up to the first layer. If the layout data does not include the first layer, that is, if the layout data is included in the first layer to the last N layers (step S204: No), the process proceeds to step S209.

  Next, in step S209, the DRC verification unit 70 performs the above-described step S205 on each layout data (layout data of the wiring layers A13 and B14 and the contact layer 15 shown in FIG. 3) included in the held second layer. The same DRC is executed repeatedly. In step S209, the LVS verification unit 60 executes LVS for each layout data. The LVS verifying unit 60 restores the gate level connection information from the layout data of the wiring layers A13, B14 and the contact layer 15, and further converts the gate level connection information into the transistor level connection information. Whether or not there is an error is determined by checking whether or not the connection information in FIG.

  In step S209, the DRC verification unit 70 and the LVS verification unit 60 perform layout data (wiring layers A13 and B14, contact layer 15) of layers determined to have errors as a result of executing DRC and LVS on each layout data. (Any one, two, or all) hold the error location report (step S210). Further, when the DRC verification unit 70 and the LVS verification unit 60 execute DRC and LVS on each layout data, both of them determine that there is no error, and terminate DRC and LVS for each layout data included in the second layer Outputs the layout data for which the layout verification processing has been completed to the layout data creation unit 40.

  Each layout data for which the layout verification processing has been completed is output from the layout data creation unit 40 to the data input / output unit 90. Further, each layout data input to the data input / output unit 90 is output to the LVL verification unit 100. Each layout data input to the LVL verification unit 100 is subjected to layout verification processing by LVL in step S211.

  In step S211, the LVL verification unit 100 performs the same LVL comparison process as in step S207 on each layout data included in the held second layer. The layout data (any one, two, or all of the wiring layers A13 and B14 and the contact layer 15) determined as having an error as a result of the LVL comparison process is sent to the LVL verification unit 100 as the error location report. At the same time, an error location report output instruction is output to the data input / output unit 90. These error location reports and error location report output instructions are output from the data input / output unit 90 to the layout data creation unit 40. Further, the error location report output instruction is output from the layout data creation unit 40 to the DRC verification unit 70 and the LVS verification unit 60. When the error location report output instruction is input, the DRC verification unit 70 and the LVS verification unit 60 output the previously stored error location report to the layout data creation unit 40. Therefore, in the second embodiment, the error location determined by the DRC verification unit 70 and the LVS verification unit 60 and the error location determined by the LVL verification unit 100 are collectively generated as an error location report. The data is output to the unit 40 (step S212).

  Next, the layout data creation unit 40 confirms the error location report and corrects the layout data (step S213). Thereafter, the processing of step S203 to step S213 is repeatedly executed until there is no error portion. In this case, the layout data creation unit 40 confirms the error location report and corrects the layout data of the corresponding layer (step S213). Therefore, when it is determined by the LVL comparison processing that there is an error portion in the lower layer layout data, the layout data can be corrected so that the relative position with the upper layer layout data matches. That is, for example, the position of the diffusion layer 12 of the first layout data shown in FIG. 4 is corrected so as to match the positions of the wiring layer A13, the wiring layer B14, and the contact layer 15 of the second layout data. Is possible.

  Then, the processing of step S203 to step S213 is repeatedly executed until there is no error portion. When it is determined in step S205, step S207, step S209, and step S211 that the layout data of all the layers has no error, 1 Layout data for N layers from the layer to the last N layers is completed (step S214), and chip data for N layers is completed (step S215). The layout data creation unit 40 outputs the completed chip data for N layers to the data input / output unit 90. Chip data for N layers is output from the data input / output unit 90 to the mask creation data creation unit 110.

  Since each process of step S216 to step S219 is the same as step S116 to step S119 described in the first embodiment, the description thereof is omitted.

  As described above, according to the second embodiment of the present invention, after performing layout verification processing on the layout data of each layer by DRC and LVS to determine the presence or absence of an error location, between adjacent layers It is possible to perform layout verification processing using LVL on layout data to determine whether there is an error location in the layout data in the lower layer, to output an error location report in a batch, and to recorrect the layout data did.

  Therefore, when manufacturing a semiconductor device having a multi-layer structure, in addition to layout verification processing by DRC and LVS applied to layout data of each layer, layout verification processing by LVL is applied to layout data of adjacent layers. can do. As a result, the accuracy of the layout verification process can be improved, and the quality of the layout design data can be further improved.

  Further, according to the second embodiment of the present invention, the error location determined by the layout verification processing using DRC and LVS and the error location determined by the layout verification processing using LVL are collectively processed. Since it is output as an error location report, it is possible to reduce the man-hour for correcting errors in the layout data.

  Furthermore, according to the second embodiment of the present invention, the layout data of all N layers up to the first layer (first layer) based on the manufacturing process when a semiconductor integrated circuit having a multilayer structure is formed into a chip. And the remaining final N layers (up to the second layer) are divided into layout data, and DRC and LVS are appropriately applied to each of the divided layout data of the plurality of layers. The layout verification process is executed by applying LVL to the layout data after layout verification.

  For this reason, compared with the case where the layout verification process is executed for each layer without dividing the layout data of all N layers, the processing load of the layout verification process can be reduced. That is, in the second embodiment, the wiring shown in FIG. 3 is used up to the first layer including the ply layer 11 and the diffusion layer 12 shown in FIG. 3 and up to the final N layer up to the first layer. The case where the LVL verification process, the DRC verification process, and the LVS verification process are appropriately executed by dividing into the second layer including the layer 14 and the contact layer 15 is shown. As a result, in the layout verification process up to the first layer, it is only necessary to execute the LVL verification process after executing only the DRC verification process, and the processing load of the layout verification process can be reduced.

(Third embodiment)
In the third embodiment, in the manufacture of a semiconductor device having a multilayer structure, layout verification processing by LVL is executed on layout data of two adjacent layers among layout data created for each layer, and layout verification is performed. A case will be described in which layout verification processing by DRC and LVS is performed on subsequent layout data, and an error location report can be output in each layout verification processing.

  Since the configuration of the layout creating apparatus according to the third embodiment is the same as that shown in FIG. 1, the illustration and description of the configuration are omitted.

  Next, the layout data creation process executed in the layout data creation device 20 of the third embodiment will be described with reference to the flowchart shown in FIG. 6 and the layout examples shown in FIGS. In the flowchart shown in FIG. 6, each layout verification process (including the error location report output timing) executed by the LVS verification unit 60, the DRC verification unit 70, and the LVL verification unit 100 includes a verification process setting unit. This is based on the setting information set in advance by 80.

  First, the specification of the semiconductor integrated circuit is determined based on the semiconductor integrated circuit specification information 10 (step S301), and the logic circuit diagram design unit 30 creates a circuit diagram based on this specification (step S302). Next, the layout data creation unit 40 creates layout data N corresponding to each layer (where N = 1, 2, 3,...) In order to create the created circuit diagram as chip data of an actual multilayer structure N. , N-1, and N) are created (step S303). The layout data creation unit 40 outputs the created layout data corresponding to the first layer to the data input / output unit 90. This layout data is output from the data input / output unit 90 to the LVL verification unit 100.

  Next, when the layout data is input, the LVL verification unit 100 holds the layout data and determines whether the layout data is the first layer (N = 1?) (Step S304). When it is determined that the layout data is the first layer (step S304: Yes), a layout data creation instruction for the next layer is output to the data input / output unit 90. The next layer layout data creation instruction is output from the data input / output unit 90 to the layout data creation unit 40. In step S304, the layout data creation unit 40 executes layout data creation processing for the second layer in response to a layout data creation instruction for the next layer.

  Next, when the layout data of the second layer is input from the layout data creation unit 40, the LVL verification unit 100 holds the layout data and determines whether it is the layout data of the first layer (step S304). It is determined that the layout data is not the first layer (step S304: No), and the process proceeds to step S305.

  In step S <b> 305, the LVL verification unit 100 executes LVL comparison processing of the held first layer layout data (lower layer layout) and second layer layout data (upper layer layout). In this LVL comparison process, the difference between the layout data of the first layer and the layout data of the second layer is output, and it is verified whether the position of the layout data of the first layer has moved from this difference. The presence or absence of is determined. If the LVL verification unit 100 determines that there is an error, the LVL verification unit 100 outputs the error location report to the data input / output unit 90 (step S306). In addition, the LVL verification unit 100 outputs the first layer layout data and the second layer layout data after the LVL comparison processing to the data input / output unit 90. The error location report and the layout data of the first layer and the layout data of the second layer after completion of the LVL comparison processing are output from the data input / output unit 90 to the layout data creation unit 40.

  Next, the layout data creation unit 40 confirms the error location report and corrects the first layer layout data (step S307). Thereafter, the processing of step S303 to step S307 is repeatedly executed until there is no error portion. In this case, the layout data creation unit 40 confirms the error location report and corrects the first layer layout data (step S307). Therefore, when it is determined by the LVL comparison processing that there is an error portion in the lower layer layout data, the layout data can be corrected so that the relative position with the upper layer layout data matches. That is, for example, the position of the diffusion layer 12 of the first layout data shown in FIG. 4 is corrected so as to match the positions of the wiring layer A13, the wiring layer B14, and the contact layer 15 of the second layout data. Is possible.

  When the LVL verification unit 100 determines that there is no error, the LVL verification unit 100 outputs the first layer layout data and the second layer layout data after the LVL comparison processing to the data input / output unit 90. The first layer layout data and the second layer layout data are output from the data input / output unit 90 to the layout data creation unit 40. Further, the layout data of the first layer and the layout data of the second layer input to the layout data creation unit 40 are output to the DRC verification unit 70 and the LVS verification unit 60, and layout verification processing by DRC and LVS in step S308 Is executed.

  Next, in step S308, the DRC verification unit 70 first extracts a figure related to elements and wiring from the layout data of the first layer shown in FIG. 3, and sets one or more design rules for each figure. Select and execute DRC to determine whether there is an error. In step S308, the LVS verification unit 60 executes LVS, restores the gate level connection information from the layout data of the first layer shown in FIG. 3, and further converts the gate level connection information into the transistor level connection information. After the conversion to information, whether or not the transistor level connection information matches the logic circuit diagram information, and further, the potential information and logic circuit diagram information input to the element node and the connection node between the elements Is checked to see if there is an error location. Subsequently, DRC and LVS are executed similarly for the layout data of the second layer to verify the layout.

  If both or one of the DRC verification unit 70 and the LVS verification unit 60 determines that there is an error in step S308, the error location report is output to the layout data creation unit 40 in step S306.

  Next, the layout data creation unit 40 confirms the error location report and corrects the layout data (step S307). Thereafter, the processing of step S303 to step S307 is repeatedly executed until there is no error portion. In this case, the layout data creation unit 40 confirms the error location report and corrects the first layer layout data (step S307).

  In step S308, when both the DRC verification unit 70 and the LVS verification unit 60 determine that there is no error, the creation of the layout data for the first layer and the layout data for the second layer is completed (step S309). Creation of the chip data of the layer and the chip data of the second layer is completed (step S310). Next, the layout data creation unit 40 outputs the first layer chip data and the second layer chip data to the data input / output unit 90. The first layer chip data and the second layer chip data are output from the data input / output unit 90 to the mask generation data generation unit 110.

  Next, the mask creation data creation unit 110 creates the first layer mask creation data 1 and the second layer mask creation data 2 based on the first layer chip data and the second layer chip data (step S311). ). Next, the mask creation data creation unit 110 determines whether or not creation of mask creation data for all layers has been completed (step S312). If it is determined that the creation of the mask creation data for all layers has not been completed (step S312: No), the layout data creation instruction for the next layer is output to the data input / output unit 90. This layout data creation instruction is output from the data input / output unit 90 to the layout data creation unit 40. In this case, the processes in steps S303 to S311 are executed again. Further, when the creation of mask creation data for all layers has been completed (step S312: Yes), the mask creation data creation unit 110 outputs all the mask creation data N to the photomask manufacturing apparatus 120. Therefore, by repeatedly executing the processing of step S303 to step S312 above, after performing layout verification processing by applying LVL to the layout data of adjacent layers, DRC, It is possible to execute layout verification processing by applying LVS. Note that the LVL verification unit 100 holds the layout data on the upper layer side of the two layout data subjected to the LVL comparison processing before the LVL comparison processing for the layout data of all layers is completed, and is created next. Further, the LVL comparison processing with the layout data of the upper layer is possible.

  Since each process of step S313 and step S314 is the same as that described in step S118 and step S119 in the first embodiment, description thereof will be omitted.

  As described above, according to the third embodiment of the present invention, after performing layout verification processing by LVL on the layout data of adjacent layers and determining the presence / absence of an error location in the lower layout data, The layout data of each layer is subjected to layout verification processing by DRC and LVS to determine the presence / absence of an error location, and an error location report can be output for each layout verification processing, and the layout data can be recorrected. It was possible.

  Therefore, when manufacturing a semiconductor device having a multi-layer structure, in addition to layout verification processing by DRC and LVS applied to layout data of each layer, layout verification processing by LVL is applied to layout data of adjacent layers. can do. As a result, the accuracy of the layout verification process can be improved, and the quality of the layout design data can be further improved.

  Further, according to the third embodiment, the timing for outputting the error location report is set in the layout verification processing by LVL, DRC and LVS based on the manufacturing process when the semiconductor integrated circuit having the multilayer structure is made into a chip. did. According to the output timing of the error location report, it is possible to output an error location report in each layout verification process by LVL, DRC, and LVS. Therefore, it is possible to create mask creation data corresponding to each layer while correcting the error location between the layout data of adjacent layers and the error location of the layout data of each layer, and improve the reliability of the photomask Can do. As a result, it is possible to reduce the correction process in the manufacturing process due to the photomask error in the manufacturing process when the semiconductor integrated circuit having the multilayer structure is made into a chip.

(Fourth embodiment)
In the fourth embodiment, in manufacturing a semiconductor device having a multilayer structure, layout verification processing by DRC and LVS is executed on layout data created for each layer, and the layout data after layout verification is adjacent to the layout data. A case will be described in which layout verification processing by LVL is performed on layout data of two layers, and an error location report can be output in each layout verification processing.

  Since the configuration of the layout creating apparatus according to the fourth embodiment is the same as that shown in FIG. 1, the illustration and description of the configuration are omitted.

  Next, the layout data creation process executed in the layout data creation device 20 of the fourth embodiment will be described with reference to the flowchart shown in FIG. 7 and the layout examples shown in FIGS. In the flowchart shown in FIG. 7, each layout verification process (including the output timing of the error location report) executed by the LVS verification unit 60, the DRC verification unit 70, and the LVL verification unit 100 is a verification process setting unit. This is based on the setting information set in advance by 80.

  First, the specification of the semiconductor integrated circuit is determined based on the semiconductor integrated circuit specification information 10 (step S401), and the logic circuit diagram design unit 30 creates a circuit diagram based on this specification (step S402). Next, the layout data creation unit 40 creates layout data N corresponding to each layer (where N = 1, 2, 3,...) In order to create the created circuit diagram as chip data of an actual multilayer structure N. , N-1, and N) are created (step S403). The layout data creation unit 40 outputs the created layout data corresponding to the first layer to the DRC verification unit 70 and the LVS verification unit 60.

  When the layout data is input, the DRC verification unit 70 holds the layout data and determines whether the layout data is the first layer (N = 1?) (Step S404). When it is determined that the layout data is the first layer (step S404: Yes), a layout data creation instruction for the next layer is output to the layout data creation unit 40. In step S403, the layout data creation unit 40 executes a layout data creation process for the second layer in response to a layout data creation instruction for the next layer.

  Next, when the second layer layout data is input from the layout data creation unit 40, the LVL verification unit 100 holds the layout data and determines whether the layout data is the first layer (step S404). It determines with layout data not being the 1st layer (step S404: No), and transfers to step S405.

  In step S405, the DRC verification unit 70 first extracts a figure related to the element and wiring from the layout data of the first layer shown in FIG. 3, and selects one or a plurality of design rules for each figure. DRC is executed to determine the presence or absence of an error location. In step S405, the LVS verification unit 60 executes LVS, restores the gate level connection information from the layout data of the first layer shown in FIG. 3, and further converts the gate level connection information into the transistor level connection information. After the conversion to information, whether or not the transistor level connection information matches the logic circuit diagram information, and further, the potential information and logic circuit diagram information input to the element node and the connection node between the elements Is checked to see if there is an error location. Subsequently, DRC and LVS are executed similarly for the layout data of the second layer to verify the layout.

  If it is determined in step S405 that either or both of the DRC verification unit 70 and the LVS verification unit 60 have an error, the error location report is output to the layout data creation unit 40 in step S406.

  Next, the layout data creation unit 40 confirms the error location report and corrects the layout data (step S407). Thereafter, the processing of step S403 to step S407 is repeatedly executed until there is no error portion. In this case, the layout data creation unit 40 confirms the error location report and corrects the first layer layout data (step S407).

  If the DRC verification unit 70 and the LVS verification unit 60 determine that there is no error, the first layer layout data and the second layer layout data after the completion of the layout verification process are output to the layout data creation unit 40. The layout data on the first layer and the layout data on the second layer after the layout verification process are output from the layout data creation unit 40 to the data input / output unit 90. Further, the layout data of the first layer and the layout data of the second layer input to the data input / output unit 90 are output from the data input / output unit 90 to the LVL verification unit 100, and layout verification processing by LVL is performed in step S408. Executed.

  In step S <b> 408, the LVL verification unit 100 executes LVL comparison processing between the input first layer layout data (lower layer layout) and second layer layout data (upper layer layout). In this LVL comparison process, the difference between the layout data of the first layer and the layout data of the second layer is output, and it is verified whether the position of the layout data of the first layer has moved from this difference. The presence or absence of is determined. If the LVL verification unit 100 determines that there is an error, the LVL verification unit 100 outputs the error location report to the data input / output unit 90 (step S406). In addition, the LVL verification unit 100 outputs the first layer layout data and the second layer layout data after the LVL comparison processing to the data input / output unit 90. The error location report and the layout data of the first layer and the layout data of the second layer after completion of the LVL comparison processing are output from the data input / output unit 90 to the layout data creation unit 40.

  Next, the layout data creation unit 40 confirms the error location report and corrects the first layer layout data (step S407). Thereafter, the processing of step S403 to step S408 is repeatedly executed until there is no error portion. In this case, the layout data creation unit 40 confirms the error location report and corrects the first layer layout data (step S307). Therefore, when it is determined by the LVL comparison processing that there is an error portion in the lower layer layout data, the layout data can be corrected so that the relative position with the upper layer layout data matches. That is, for example, the position of the diffusion layer 12 of the first layout data shown in FIG. 4 is corrected so as to match the positions of the wiring layer A13, the wiring layer B14, and the contact layer 15 of the second layout data. Is possible.

  If the LVL verification unit 100 determines that there is no error, the creation of the layout data for the first layer and the layout data for the second layer is completed (step S409). Creation of chip data is completed (step S410). Next, the LVL verification unit 100 outputs the first layer chip data and the second layer chip data to the mask generation data generation unit 110.

  Next, the mask creation data creation unit 110 creates the first layer mask creation data 1 and the second layer mask creation data 2 based on the first layer chip data and the second layer chip data (step S411). ). Next, the mask creation data creation unit 110 determines whether or not creation of mask creation data for all layers has been completed (step S412). If it is determined that the creation of mask creation data for all layers has not been completed (step S412: No), a layout data creation instruction for the next layer is output to the data input / output unit 90. This layout data creation instruction is output from the data input / output unit 90 to the layout data creation unit 40. In this case, the processes in steps S403 to S411 are executed again. Further, when the creation of mask creation data for all layers has been completed (step S412: Yes), the mask creation data creation unit 110 outputs all the mask creation data N to the photomask manufacturing apparatus 120. Therefore, by repeatedly executing the processing of step S403 to step S412 above, the layout verification processing is performed by applying DRC and LVS to the layout data, and then the layout data of adjacent layers after the layout verification is performed. It is possible to execute the layout verification process by applying LVL. Note that the LVL verification unit 100 holds the layout data on the upper layer side of the two layout data subjected to the LVL comparison processing before the LVL comparison processing for the layout data of all layers is completed, and is created next. Further, the LVL comparison processing with the layout data of the upper layer is possible.

  Since each process of step S413 and step S414 is the same as that described in step S118 and step S119 in the first embodiment, the description thereof is omitted.

  As described above, according to the fourth embodiment of the present invention, after performing layout verification processing on the layout data of each layer by DRC and LVS to determine the presence / absence of an error location, between adjacent layers It is possible to execute layout verification processing by LVL on layout data to determine whether or not there is an error location in the lower layout data, and to output an error location report for each layout verification processing, and to re-correct the layout data It was possible.

  Therefore, when manufacturing a semiconductor device having a multi-layer structure, in addition to layout verification processing by DRC and LVS applied to layout data of each layer, layout verification processing by LVL is applied to layout data of adjacent layers. can do. As a result, the accuracy of the layout verification process can be improved, and the quality of the layout design data can be further improved.

  Further, according to the fourth embodiment, the timing for outputting the error location report in the layout verification processing by DRC, LVS, and LVL is set based on the manufacturing process when the semiconductor integrated circuit having the multilayer structure is made into a chip. did. According to the output timing of the error location report, it is possible to output an error location report in each layout verification process by DRC, LVS, and LVL. Therefore, it is possible to create mask creation data corresponding to each layer while correcting the error location of the layout data of each layer and the error location between the layout data of adjacent layers, and improve the reliability of the photomask Can do. As a result, it is possible to reduce the correction process in the manufacturing process due to the photomask error in the manufacturing process when the semiconductor integrated circuit having the multilayer structure is made into a chip.

(Fifth embodiment)
In the fifth embodiment, in the manufacture of a semiconductor device having a multilayer structure, layout verification processing by LVL is executed on layout data of two adjacent layers among layout data created for each layer, and layout verification is performed. It is possible to execute layout verification processing by DRC and LVS for the subsequent layout data, execute these layout verification processing by dividing into multiple layers, and output an error location report for each layout verification processing The case where it makes is explained.

  Since the configuration of the layout creating apparatus according to the fifth embodiment is the same as that shown in FIG. 1, the illustration and description of the configuration are omitted.

  Next, the layout data creation processing executed in the layout data creation device 20 of the fifth embodiment will be described with reference to the flowchart shown in FIG. 8 and the layout examples shown in FIGS. In the flowchart shown in FIG. 8, each layout verification process executed by the LVS verification unit 60, the DRC verification unit 70, and the LVL verification unit 100 (including the output timing of the error location report) is a verification process setting unit. This is based on the setting information set in advance by 80.

  First, the specification of the semiconductor integrated circuit is determined based on the semiconductor integrated circuit specification information 10 (step S501), and the logic circuit diagram design unit 30 creates a circuit diagram based on this specification (step S502). Next, the layout data creation unit 40 creates layout data N corresponding to each layer (where N = 1, 2, 3,...) In order to create the created circuit diagram as chip data of an actual multilayer structure N. , N-1, and N) are created (step S503). The layout data creation unit 40 outputs the created layout data corresponding to the first layer to the DRC verification unit 70 and the LVS verification unit 60. The layout data creation unit 40 includes a layout of a plurality of layers including up to the first layer (for example, up to the first layer including the poly layer 11 and the diffusion layer 12 shown in FIG. 3) among the created layout data for N layers. Data is output to the data input / output unit 90. The layout data up to the first layer is output from the data input / output unit 90 to the LVL verification unit 100.

  In this case, the first layer including the poly layer 11 and the diffusion layer 12 shown in FIG. 3 is used as the first layer for dividing the verification process based on the manufacturing process when the semiconductor integrated circuit is formed into a chip. Yes. The layer that divides the verification process is set by the verification process setting unit 80. That is, if at least an LVL verification process between the poly layer 11 and the diffusion layer 12 and a DRC verification process are performed in advance for each layer of the poly layer 11 and the diffusion layer 12 and an error part is extracted, the layer related to the wiring Is not included in the layout verification target, the LVS verification processing and the wiring layer DRC verification processing can be omitted.

  Next, in step S504, the LVL verification unit 100 holds each layout data of the first layer input from the layout data creation unit 40, and each layout data up to the first layer (up to the first layer). Determine whether it is layout data. If it is layout data up to the first layer (step S504: Yes), the process proceeds to step S505. If the layout data is not up to the first layer (step S504: No), the process proceeds to step S509.

  In step S505, the LVL verification unit 100 executes LVL comparison processing of the lower layout data (poly layer 11) and the upper layout data (diffusion layer 12) among the stored layout data included in the first layer. . In this LVL comparison process, the difference between the lower layer layout data and the upper layer layout data is output, and whether or not the position of the layout data of the first layer has been moved is determined from this difference, and the presence or absence of an error portion is determined. To do. The LVL verification unit 100 outputs the error location report of the layout data (one or both of the poly layer 11 and the diffusion layer 12) determined to have an error to the data input / output unit 90 (step S506). This error location report is output from the data input / output unit 90 to the layout data creation unit 40.

  Next, the layout data creation unit 40 confirms the error location report and corrects the layout data of the corresponding layer (step S507). Thereafter, the processing in steps S503 to S507 is repeatedly executed for each layout data included in the first layer until there is no error portion. Therefore, when it is determined by the LVL comparison processing that there is an error portion in the lower layer layout data, the layout data can be corrected so that the relative position with the upper layer layout data matches. That is, for example, the position of the first diffusion layer 12 shown in FIG. 3 can be corrected to match the position of the poly layer 11.

  In addition, when the LVL verification unit 100 determines that there is no error as a result of executing the LVL comparison process between the layout data included in the first layer, the LVL comparison unit 100 stores each layout data of the first layer for which the LVL comparison process has been completed. Output to the input / output unit 90. Each layout data of the first layer for which the LVL comparison processing has been completed is output from the data input / output unit 90 to the layout data creation unit 40. Further, each layout data of the first layer input to the layout data creation unit 40 is output to the DRC verification unit 70, and layout verification processing by DRC is executed in step S508.

  Next, in step S508, the DRC verification unit 70 first extracts a figure related to the element and wiring from the layout data of the first layer shown in FIG. 3, and sets one or more design rules for each figure. Select and execute DRC to determine whether there is an error.

  In step S508, the DRC verification unit 70 executes layout data (one or both of the poly layer 11 and the diffusion layer 12) determined to have an error as a result of executing DRC for each layout data of the first layer. Is output to the layout data creation unit 40 (step S506).

  Next, the layout data creation unit 40 confirms the error location report and corrects the layout data of the corresponding layer (step S507). Thereafter, the processes in steps S503 to S508 are repeatedly executed for each layout data included in the first layer until there is no error portion.

  Also, the DRC verification unit 70 determines that there is no error as a result of executing DRC for each layout data of the first layer. When the DRC for each layout data of the first layer is completed, the DRC verification unit 70 reaches the remaining final N layers. A process transition instruction signal for instructing transition to layout verification processing for each included layout data is output to the layout data creation unit 40.

  When the process transition instruction signal is input, the layout data creating unit 40 extends from the first layer to the final N layer (for example, up to the second layer including the wiring layers A13 and B14 and the contact layer 15 shown in FIG. 3). Each included layout data is output to the data input / output unit 90. Each layout data included in the second layer is output from the data input / output unit 90 to the LVL verification unit 100. In step S504, the LVL verification unit 100 holds each layout data of the second layer input from the layout data creation unit 40, and determines whether each layout data is layout data included up to the first layer. If the layout data is not included up to the first layer, that is, if the layout data is included from the first layer to the last N layers (step S504: No), the process proceeds to step S509.

  In step S509, the LVL verification unit 100 applies the same LVL as in step S505 to each layout data (layout data of the wiring layers A13 and B14 and the contact layer 15 in FIG. 3) included in the held second layer. Repeat the comparison process. Then, the layout data (any one, two, or all of the wiring layers A13, B14 and the contact layer 15) determined as having an error as a result of the LVL comparison process is sent to the LVL verification unit 100 as an error location report. Is output to the data input / output unit 90 (step S506). This error location report is output from the data input / output unit 90 to the layout data creation unit 40.

  Next, the layout data creation unit 40 confirms the error location report and corrects the layout data of the corresponding layer (step S507). Thereafter, the processes in steps S503 to S509 are repeatedly executed for each layout data included in the second layer until there is no error portion.

  In addition, when the LVL verification unit 100 determines that there is no error as a result of executing the LVL comparison processing between the layout data included in the second layer, the LVL comparison unit 100 stores each layout data of the second layer for which the LVL comparison processing has been completed. Output to the input / output unit 90. Each layout data of the second layer for which the LVL comparison processing has been completed is output from the data input / output unit 90 to the layout data creation unit 40. Further, each layout data of the second layer input to the layout data creation unit 40 is output to the DRC verification unit 70 and the LVS verification unit 60, and layout verification processing by DRC and LVS is executed in step S510.

  Next, in step S510, the DRC verification unit 70 repeatedly performs the same DRC as in step S508 on each layout data of the second layer. In step S510, the LVS verification unit 60 executes LVS for each layout data of the second layer. The LVS verifying unit 60 restores the gate level connection information from the layout data of the wiring layers A13, B14 and the contact layer 15, and further converts the gate level connection information into the transistor level connection information. Whether or not there is an error is determined by checking whether or not the connection information in FIG.

  In step S510, the DRC verification unit 70 and the LVS verification unit 60 perform layout data (wiring layer A13) of layers determined to have errors as a result of executing DRC and LVS on each layout data of the second layer. , B14 and any one, two, or all of the contact layers 15) output the error location report to the layout data creation unit 40 (step S506).

  Next, the layout data creation unit 40 confirms the error location report and corrects the layout data of the corresponding layer (step S507). Thereafter, the processes in steps S503 to S510 are repeatedly executed for each layout data of the second layer until there is no error portion.

  Then, the processing of step S503 to step S510 is repeatedly executed until there is no error portion. When it is determined in step S505, step S507, step S509, and step S510 that the layout data of all layers has no error, 1 Layout data for N layers from the layer to the final N layers is completed (step S511), and chip data for N layers is completed (step S512). The layout data creation unit 40 outputs the completed chip data for N layers to the data input / output unit 90. Chip data for N layers is output from the data input / output unit 90 to the mask creation data creation unit 110.

  Since each process of step S513 to step S516 is the same as that described in step S116 to step S119 in the first embodiment, the description thereof is omitted.

  As described above, according to the fifth embodiment of the present invention, after performing layout verification processing by LVL on the layout data of adjacent layers and determining the presence / absence of an error location in the lower layer layout data, The layout data of each layer is subjected to layout verification processing by DRC and LVS to determine the presence / absence of an error location, and an error location report can be output for each layout verification processing, and the layout data can be recorrected. It was possible.

  Therefore, when manufacturing a semiconductor device having a multi-layer structure, in addition to layout verification processing by DRC and LVS applied to layout data of each layer, layout verification processing by LVL is applied to layout data of adjacent layers. can do. As a result, the accuracy of the layout verification process can be improved, and the quality of the layout design data can be further improved.

  Further, according to the fifth embodiment of the present invention, the layout data of all N layers up to the first layer (the first layer) is based on the manufacturing process when the semiconductor integrated circuit having a multilayer structure is made into a chip. And the remaining final N layers (up to the second layer) are divided into layout data, and the layout verification processing is executed by applying LVL to each of the divided layout data of the plurality of layers. The layout verification process is executed by appropriately applying DRC and LVS to the layout data.

  For this reason, compared with the case where the layout verification process is executed for each layer without dividing the layout data of all N layers, the processing load of the layout verification process can be reduced. That is, in the fifth embodiment, the wiring shown in FIG. 3 is used up to the first layer including the ply layer 11 and the diffusion layer 12 shown in FIG. 3 and up to the final N layer up to the first layer. The case where the LVL verification process, the DRC verification process, and the LVS verification process are appropriately executed by dividing into the second layer including the layer 14 and the contact layer 15 is shown. As a result, in the layout verification process up to the first layer, it is only necessary to execute the DRC verification process after executing the LVL verification process, and the processing load of the layout verification process can be reduced.

  Furthermore, according to the fifth embodiment, the timing for outputting the error location report is set in the layout verification processing by LVL, DRC and LVS based on the manufacturing process when the semiconductor integrated circuit having the multilayer structure is made into a chip. did. According to the output timing of the error location report, it is possible to output an error location report in each layout verification process by LVL, DRC, and LVS. Therefore, it is possible to create mask creation data corresponding to each layer while correcting the error location between the layout data of adjacent layers and the error location of the layout data of each layer, and improve the reliability of the photomask Can do. As a result, it is possible to reduce the correction process in the manufacturing process due to the photomask error in the manufacturing process when the semiconductor integrated circuit having the multilayer structure is made into a chip.

(Sixth embodiment)
In the sixth embodiment, in manufacturing a semiconductor device having a multilayer structure, layout verification processing by DRC and LVS is performed on layout data created for each layer, and the layout data after layout verification is adjacent. It is possible to execute layout verification processing by LVL on the layout data of two layers, execute these layout verification processing divided into multiple layers, and output an error location report for each layout verification processing The case where it makes is explained.

  Since the configuration of the layout creating apparatus according to the sixth embodiment is the same as that shown in FIG. 1, the illustration and description of the configuration are omitted.

  Next, the layout data creation processing executed in the layout data creation device 20 of the sixth embodiment will be described with reference to the flowchart shown in FIG. 9 and the layout examples shown in FIGS. In the flowchart shown in FIG. 9, each layout verification process (including the error location report output timing) executed by the LVS verification unit 60, the DRC verification unit 70, and the LVL verification unit 100 is a verification process setting unit. This is based on the setting information set in advance by 80.

  First, the specification of the semiconductor integrated circuit is determined based on the semiconductor integrated circuit specification information 10 (step S601), and the logic circuit diagram design unit 30 creates a circuit diagram based on this specification (step S602). Next, the layout data creation unit 40 creates layout data N corresponding to each layer (where N = 1, 2, 3,...) In order to create the created circuit diagram as chip data of an actual multilayer structure N. , N-1, and N) are created (step S603). The layout data creation unit 40 outputs the created layout data corresponding to the first layer to the DRC verification unit 70 and the LVS verification unit 60. The layout data creation unit 40 includes a layout of a plurality of layers including up to the first layer (for example, up to the first layer including the poly layer 11 and the diffusion layer 12 shown in FIG. 3) among the created layout data for N layers. The data is output to the layout data verification unit 50. The layout data up to the first layer is input to the DRC verification unit 70 in the layout data verification unit 50.

  In this case, the first layer including the poly layer 11 and the diffusion layer 12 shown in FIG. 3 is used as the first layer for dividing the verification process based on the manufacturing process when the semiconductor integrated circuit is formed into a chip. Yes. The layer that divides the verification process is set by the verification process setting unit 80. That is, if at least the DRC verification process and the LVL verification process between the poly layer 11 and the diffusion layer 12 are performed in advance for each of the poly layer 11 and the diffusion layer 12 and the error part is extracted, the layer related to the wiring Is not included in the layout verification target, the LVS verification processing and the wiring layer DRC verification processing can be omitted.

  Next, in step S604, the DRC verification unit 70 holds each layout data of the first layer input from the layout data creation unit 40, and each layout data reaches the first layer (up to the first layer). It is determined whether the layout data is included. If the layout data is included up to the first layer (step S604: Yes), the process proceeds to step S605. If the layout data does not include the first layer (step S604: No), the process proceeds to step S609.

  Next, in step S605, the DRC verification unit 70 executes DRC for each layout data of the first layer. In step S605, the DRC verification unit 70 first extracts a figure related to the element and the wiring from each layout data of the poly layer 11 and the diffusion layer 12 included in the first layer shown in FIG. One or more design rules are selected and DRC is executed to determine the presence or absence of an error location.

  In step S605, the DRC verification unit 70 executes the DRC on each layout data of the first layer, and the layout data (one or both of the poly layer 11 and the diffusion layer 12) determined to have an error is the error location report. Is output to the layout data creation unit 40 (step S606).

  Next, the layout data creation unit 40 confirms the error location report and corrects the layout data of the corresponding layer (step S607). Thereafter, the processes in steps S603 to S607 are repeatedly executed for each layout data included in the first layer until there is no error portion.

  Further, the DRC verification unit 70 determines that there is no error as a result of executing DRC for each layout data of the first layer, and when the DRC for each layout data of the first layer is completed, the layout verification process is completed. Each layout data of the first layer is output to the layout data creation unit 40. Each layout data of the first layer for which the layout verification processing has been completed is output from the layout data creation unit 40 to the data input / output unit 90. Further, each layout data of the first layer input to the data input / output unit 90 is output to the LVL verification unit 100, and layout verification processing by LVL is executed in step S608.

  In step S608, the LVL verification unit 100 executes LVL comparison processing of the lower layout data (poly layer 11) and the upper layout data (diffusion layer 12) among the stored layout data included in the first layer. . In this LVL comparison process, the difference between the lower layer layout data and the upper layer layout data is output, and whether or not the position of the layout data of the first layer has been moved is determined from this difference, and the presence or absence of an error portion is determined. To do. The LVL verification unit 100 outputs the error location report of the layout data (one or both of the poly layer 11 and the diffusion layer 12) determined to have an error to the data input / output unit 90 (step S606). This error location report is output from the data input / output unit 90 to the layout data creation unit 40.

  Next, the layout data creation unit 40 confirms the error location report and corrects the layout data of the corresponding layer (step S607). Thereafter, the processing from step S603 to step S608 is repeatedly executed for each layout data included in the first layer until there is no error portion. Therefore, when it is determined by the LVL comparison processing that there is an error portion in the lower layer layout data, the layout data can be corrected so that the relative position with the upper layer layout data matches. That is, for example, the position of the first diffusion layer 12 shown in FIG. 3 can be corrected to match the position of the poly layer 11.

  In step S608, the LVL verification unit 100 determines that there is no error as a result of executing the LVL comparison processing for each retained layout data in the first layer, and performs the LVL comparison processing for each layout data in the first layer. When the processing is completed, a processing transition instruction signal for instructing transition to processing for the layout data up to the last final N layers is output to the data input / output unit 90. This processing transition instruction signal is output from the data input / output unit 90 to the layout data creation unit 40.

  When the process transition instruction signal is input, the layout data creating unit 40 extends from the first layer to the final N layer (for example, up to the second layer including the wiring layers A13 and B14 and the contact layer 15 shown in FIG. 3). Each included layout data is output to the layout data verification unit 50. Each layout data included up to the last N layers is input to the DRC verification unit 70 and the LVS verification unit 60 in the layout data verification unit 50. In step S604, the DRC verification unit 70 and the LVS verification unit 60 hold each layout data input from the layout data creation unit 40, and determine whether each layout data is layout data included up to the first layer. . If the layout data does not include the first layer, that is, the layout data includes from the first layer to the last N layers (step S604: No), the process proceeds to step S609.

  Next, in step S609, the DRC verification unit 70 repeatedly executes the same DRC as in step S605 described above for each layout data included in the held second layer. In step S609, the LVS verification unit 60 executes LVS for each layout data. The LVS verifying unit 60 restores the gate level connection information from the layout data of the wiring layers A13, B14 and the contact layer 15, and further converts the gate level connection information into the transistor level connection information. Whether or not there is an error is determined by checking whether or not the connection information in FIG.

  In step S609, the DRC verification unit 70 and the LVS verification unit 60 perform layout data (wiring layers A13, B14, contact layer 15) of layers determined to have errors as a result of executing DRC and LVS on each layout data. Any one, two, or all) outputs the error location report to the layout data creation unit 40 (step S606).

  Next, the layout data creation unit 40 confirms the error location report and corrects the layout data of the corresponding layer (step S607). Thereafter, the processing in steps S603 to S609 is repeatedly executed for each layout data included in the second layer until there is no error portion.

  In addition, the DRC verification unit 70 and the LVS verification unit 60 execute DRC and LVS for each layout data of the second layer, and as a result, both determine that there is no error, and end the DRC and LVS for each layout data of the second layer. In this case, each layout data of the second layer is output to the layout data creation unit 40. Each layout data of the second layer for which the layout verification processing has been completed is output from the layout data creation unit 40 to the data input / output unit 90. Further, each layout data of the second layer input to the data input / output unit 90 is output to the LVL verification unit 100, and layout verification processing by LVL is executed in step S610.

  In step S610, the LVL verification unit 100 executes the same LVL comparison process as in step S608 on the retained layout data of the second layer. The layout data (any one, two, or all of the wiring layers A13 and B14 and the contact layer 15) determined as having an error as a result of the LVL comparison process is sent to the LVL verification unit 100 as the error location report. Is output to the data input / output unit 90 (step S606). This error location report is output from the data input / output unit 90 to the layout data creation unit 40.

  Next, the layout data creation unit 40 confirms the error location report and corrects the layout data (step S607). Thereafter, the processes in steps S603 to S610 are repeatedly executed until there is no error portion. Therefore, when it is determined by the LVL comparison processing that there is an error portion in the lower layer layout data, the layout data can be corrected so that the relative position with the upper layer layout data matches. That is, for example, the position of the diffusion layer 12 of the first layout data shown in FIG. 4 is corrected so as to match the positions of the wiring layer A13, the wiring layer B14, and the contact layer 15 of the second layout data. Is possible.

  Then, the processing of step S603 to step S610 is repeatedly executed until there is no error portion. When it is determined in step S605, step S608, step S609, and step S610 that the layout data of all layers is free of errors, 1 Layout data for N layers from the layer to the last N layers is completed (step S611), and chip data for N layers is completed (step S612).

  Since each process of step S613 to step S616 is the same as that described in step S116 to step S119 in the first embodiment, the description thereof is omitted.

  As described above, according to the sixth embodiment of the present invention, the layout verification process is performed on the layout data of each layer of the multilayer structure by DRC and LVS to determine the presence / absence of an error portion, and then adjacent to the layout data. It is possible to execute layout verification processing by LVL on layout data between layers to determine whether or not there is an error location in the layout data in the lower layer, and to output an error location report for each layout verification processing. Re-correction is possible.

  Therefore, when manufacturing a semiconductor device having a multi-layer structure, in addition to layout verification processing by DRC and LVS applied to layout data of each layer, layout verification processing by LVL is applied to layout data of adjacent layers. can do. As a result, the accuracy of the layout verification process can be improved, and the quality of the layout design data can be further improved.

  In addition, according to the sixth embodiment of the present invention, the layout data of all N layers up to the first layer (first layer) based on the manufacturing process when the semiconductor integrated circuit having a multilayer structure is formed into a chip. And the remaining final N layers (up to the second layer) are divided into layout data, and DRC and LVS are applied as appropriate to each of the divided layout data of the plurality of layers, and the layout verification process is executed. The layout verification processing is executed by applying LVL to the verified layout data.

  For this reason, compared with the case where the layout verification process is executed for each layer without dividing the layout data of all N layers, the processing load of the layout verification process can be reduced. That is, in the sixth embodiment, the wiring shown in FIG. 3 is used up to the first layer including the ply layer 11 and the diffusion layer 12 shown in FIG. 3 and up to the final N layer up to the first layer. The case where the LVL verification process, the DRC verification process, and the LVS verification process are appropriately executed by dividing into the second layer including the layer 14 and the contact layer 15 is shown. As a result, in the layout verification process up to the first layer, it is only necessary to execute the DRC verification process after executing the LVL verification process, and the processing load of the layout verification process can be reduced.

  Furthermore, according to the sixth embodiment, the timing for outputting the error location report is set in the layout verification processing by DRC, LVS, and LVL based on the manufacturing process when the semiconductor integrated circuit having the multilayer structure is made into a chip. did. According to the output timing of the error location report, it is possible to output an error location report in each layout verification process by DRC, LVS, and LVL. Therefore, it is possible to create mask creation data corresponding to each layer while correcting the error location between the layout data of adjacent layers and the error location of the layout data of each layer, and improve the reliability of the photomask Can do. As a result, it is possible to reduce the correction process in the manufacturing process due to the photomask error in the manufacturing process when the semiconductor integrated circuit having the multilayer structure is made into a chip.

It is a block diagram which shows the structural example of the layout production apparatus which concerns on the 1st Embodiment of this invention. It is a flowchart which shows the layout data creation process performed in the layout creation apparatus which concerns on the 1st Embodiment of this invention. 1 is a plan view showing an example of a layout of a semiconductor integrated circuit having a multilayer structure according to a first embodiment of the present invention. 1 is a plan view showing an example of a layout of a semiconductor integrated circuit having a multilayer structure according to a first embodiment of the present invention. It is a flowchart which shows the layout data creation process performed in the layout creation apparatus which concerns on the 2nd Embodiment of this invention. It is a flowchart which shows the layout data creation process performed in the layout creation apparatus which concerns on the 3rd Embodiment of this invention. It is a flowchart which shows the layout data creation process performed in the layout creation apparatus which concerns on the 4th Embodiment of this invention. It is a flowchart which shows the layout data creation process performed in the layout creation apparatus which concerns on the 5th Embodiment of this invention. It is a flowchart which shows the layout data creation process performed in the layout creation apparatus which concerns on the 6th Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 20 ... Layout creation apparatus, 30 ... Logic circuit diagram design part, 40 ... Layout data creation part, 50 ... Layout data verification part, 60 ... LVS verification part, 70 ... DRC verification part, 80 ... Verification process setting part, 100 ... LVL Verification unit 110... Mask creation data creation unit 120... Photomask manufacturing apparatus 130 130 Semiconductor device manufacturing apparatus

Claims (5)

A logic circuit diagram design unit for designing a logic circuit diagram based on specification information of a semiconductor integrated circuit;
A layout data creation unit for creating layout data for each layer of a semiconductor integrated circuit having a multilayer structure based on the designed logic circuit diagram;
Information on the connection between the elements is extracted from the created layout data for each layer, and whether or not the information on the logic circuit diagram matches the information on the extracted elements and the information on the connections between the elements. A logical connection verification unit that verifies and generates the result;
Whether the created layout data for each layer violates the design rule extracted from the specification information of the semiconductor integrated circuit based on the information extracted in the logical connection verification unit and the connection between the elements And a design rule verification unit that generates the verification result,
The position of the element and the connection position between the elements are compared between the layout data of different layers among the plurality of layout data for each layer, and the positional deviation of the position of the element and the connection position between the elements is verified. An interlayer layout verification unit that generates the verification result,
A data output unit for outputting layout data created by the layout data creation unit;
A verification process for setting a verification process executed in the logical connection verification unit, the design rule verification unit, and the interlayer layout verification unit based on a manufacturing process when the semiconductor integrated circuit having the multilayer structure is formed into a chip. A setting section;
An apparatus for creating a layout of a semiconductor integrated circuit.   The verification process setting unit sets a layer that divides layout data for each of the plurality of layers to be verified based on a manufacturing process when the semiconductor integrated circuit having the multilayer structure is formed into a chip. 2. The semiconductor integrated circuit layout creating apparatus according to claim 1, wherein the verification process is set in accordance with the divided layers.   The verification process setting unit includes a verification process executed in the logical connection verification unit and the design rule verification unit based on a manufacturing process when the semiconductor integrated circuit having the multilayer structure is formed into a chip, and the interlayer layout verification unit. The layout creation apparatus for a semiconductor integrated circuit according to claim 1, wherein the order of the verification processing executed in step 1 is changed.   The verification process setting unit is a verification process executed in the logical connection verification unit, the design rule verification unit, and the interlayer layout verification unit based on a manufacturing process when the semiconductor integrated circuit having the multilayer structure is formed into a chip. 4. The layout creation apparatus for a semiconductor integrated circuit according to claim 1, wherein an output timing of an error location report extracted during the process is set. Designing a logic circuit diagram based on the specification information of the semiconductor integrated circuit;
Creating layout data for each layer of a semiconductor integrated circuit having a multilayer structure based on the designed logic circuit diagram;
Information on the connection between the elements is extracted from the created layout data for each layer, and whether or not the information on the logic circuit diagram matches the information on the extracted elements and the information on the connections between the elements. Verifying and generating the results;
Whether the created layout data for each layer violates the design rule extracted from the specification information of the semiconductor integrated circuit based on the information extracted in the logical connection verification unit and the connection between the elements And generating the verification result,
The position of the element and the connection position between the elements are compared between the layout data of different layers among the plurality of layout data for each layer, and the positional deviation of the position of the element and the connection position between the elements is verified. Generating the verification result, and
Outputting layout data created by the layout data creation unit;
Setting a process of verification processing executed in the logical connection verification unit, the design rule verification unit, and the interlayer layout verification unit based on a manufacturing process when the semiconductor integrated circuit having the multilayer structure is formed into a chip; and ,
A method of creating a layout of a semiconductor integrated circuit, comprising:

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