JP2015132870A - Layout verification method, verification layout data creation method, layout verification program, and verification layout data generation program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a layout verification method, verification layout data creation method, layout verification program, and verification layout data creation program, which allow efficient verification of the layout of a three-dimensional LSI chip.SOLUTION: A layout verification method for verifying the layout of a three-dimensional semiconductor includes: a virtual layer synthesis step in which the layout data of an uppermost layer in the layout data of a plurality of layers that has location information of a plurality of elements including a via and wiring pattern in a first semiconductor device and has identical node information for the plurality of elements having an identical potential is added for synthesis as the layout data of a virtual layer to the layout data of a second semiconductor device that is laminated on the first semiconductor device; and an error detection step in which an error is detected when there is different node information for the plurality of elements with an identical potential in the layout data of the second semiconductor device which includes the virtual layer.

Description

  The present invention relates to a layout verification method, a verification layout data generation method, a layout verification program, and a verification layout data generation program.

  In recent years, there is a technique for stacking another LSI chip on one LSI (Large Scale Integration) chip to generate a three-dimensional LSI chip (for example, Patent Document 1). The two LSI chips are bonded together by connecting the pads with bumps such as ball-shaped solder so that the pad surfaces of the LSI chips face each other.

  Label names are assigned to pads, vias, and the like in an LSI chip, and a plurality of pads, vias, and the like on equipotential wiring are assigned the same label name by indicating the same node. Further, in a three-dimensional LSI chip, both pads connected between the LSI chips to be bonded have the same potential, and thus indicate the same node. If the nodes of both pads to be connected do not match, the three-dimensional LSI chip does not operate correctly.

  Further, LVS (layout versus schematic) verification is performed as LSI chip layout verification. In the LVS verification, the net list extracted from the layout data of the LSI chip is compared with the net list extracted from the circuit diagram to verify that they are equivalent. Also, in the process of LVS verification, if different label names are assigned to multiple pads or vias on equipotential wiring in LSI chip layout data, netlist extraction fails due to node mismatch and an error occurs. To do.

JP-A-9-289253

  However, in conventional LVS verification, verification is performed on a single chip. That is, according to the LVS verification, verification is performed on each of the two LSI chips constituting the three-dimensional LSI chip. Therefore, according to the conventional LVS verification, it has not been verified whether different label names are assigned to both pads connected between the layout data of two LSI chips. Therefore, node mismatch in the layout data of the three-dimensional LSI chip was not detected.

  In one aspect, the present invention provides a layout verification method, a verification layout data generation method, a layout verification program, and a verification layout data generation program that enable layout verification of a three-dimensional LSI chip.

  A first aspect is a layout verification method for verifying a layout of a three-dimensional semiconductor device, comprising positional information of a plurality of elements including vias and wiring patterns in the first semiconductor device, and having the equipotential The layout data of the uppermost layer in the layout data of a plurality of layers having the same node information for a plurality of elements is used as the layout data of the virtual layer in the layout data of the second semiconductor device attached to the first semiconductor device. A virtual layer synthesis step for adding and synthesizing, and an error detection step for detecting an error in the case where the layout data of the second semiconductor device including the virtual layer has different node information for the plurality of equipotential elements And having.

  According to the first aspect, the layout data of the uppermost layer in the first semiconductor device is added to the layout data of the second semiconductor device and synthesized as the layout data of the virtual layer, and the second semiconductor including the virtual layer With respect to the layout data of the device, it is possible to verify the layout of a three-dimensional LSI chip by detecting an error when different node information is included for the plurality of equipotential elements.

It is a figure which shows an example of a three-dimensional semiconductor circuit device. It is a flowchart figure explaining the outline | summary of LVS verification. It is a figure which shows an example of a net list extracted from circuit diagram data and circuit diagram data. It is a figure which shows an example of the layout data corresponding to the circuit diagram data shown in FIG. It is a figure explaining the outline | summary of the layout verification method in the present embodiment. It is a figure explaining the structure of the layout verification apparatus in the present embodiment. It is a figure explaining the block diagram of the layout verification apparatus in the present embodiment. It is a flowchart figure explaining the layout verification process in the example of this embodiment. It is a figure which shows an example of the circuit diagram data of LSI chip A and B in a specific example. FIG. 10 is a diagram showing an example of layout data of LSI chips A and B shown in FIG. 9. It is a figure which shows an example of sectional drawing of the layout data of FIG. It is a figure explaining an example of the layout data of the virtual layer based on the layout data of FIG. It is a figure explaining another example of the layout data of the virtual layer based on the layout data of FIG. It is a figure which shows an example of another layout data of LSI chip A and B in a specific example. It is a figure which shows an example of sectional drawing of the layout data of FIG. It is a figure explaining an example of the layout data of the virtual layer based on the layout data of FIG. It is a figure explaining another example of the layout data of the virtual layer based on the layout data of FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the matters described in the claims and equivalents thereof.

[Three-dimensional semiconductor circuit device]
FIG. 1 is a diagram illustrating an example of a three-dimensional semiconductor circuit device (hereinafter referred to as an LSI (Large Scale Integration) chip). The three-dimensional LSI chip shown in FIG. 1 is bonded to the chip surface of the supporting LSI chip 1ch1 so that the chip surface of the LSI chip 2ch2 faces. The LSI chip 1ch1 and the LSI chip 2ch2 are connected via bumps BP formed on the pads P1 to P4 and P11 to P14 on the chip surface. For example, a metal plating layer is formed on the pads P1 to P4 and P11 to P14, and a bump BP is formed on the metal plating layer. In the LSI chip 1ch1, a pad PD connected to the outside is disposed on the outer peripheral portion of the LSI chip 1ch1.

  In the example of FIG. 1, the pad P1 on the LSI chip 1ch1 is connected to the pad P11 on the LSI chip 2ch2. That is, the terminal (pad P11) of the LSI chip 2ch2 is connected to the pad P1 of the LSI chip 1ch1 via the bump BP and is connected to the pad PD on the outer peripheral portion of the LSI chip 1ch1. Similarly, the pad P12 on the LSI chip 2ch2 is connected to the pad P2 on the LSI chip 1ch1, and is connected to the pad PD on the outer peripheral portion of the LSI chip 1ch1. Similarly, the pads P13 and P14 on the LSI chip 2ch2 are connected to the pads P3 and P4 on the LSI chip 1ch1.

  A label name is assigned to each pad on the LSI chip 1ch1 and the LSI chip 2ch2 shown in FIG. Further, in the layout data and circuit diagram data of the LSI chip 1ch1 and the LSI chip 2ch2, the pads and vias (not shown) connected to each other indicate the same node and are handled as assigned label name nodes. Hereinafter, the label name is referred to as node information. In the example of FIG. 1, the pad P1 on the LSI chip 1ch1 has, for example, node information n1. Similarly, the pads P2 to P4 on the LSI chip 1ch1 have node information n2 to n4. Further, the pad P11 on the LSI chip 2ch2 has, for example, node information n1 ′. Similarly, the pads P12 to P14 on the LSI chip 2ch2 have node information n2 ′ to n4 ′.

  For example, the LSI chip 1ch1 and the LSI chip 2ch2 are bonded so that the nodes of the corresponding pads coincide. In the example of FIG. 1, the node information n1 and the node information n1 ′ indicate equipotential nodes. For example, in the example of FIG. 1, when the pad P1 (node information n1) on the LSI chip 1ch1 is connected to the pad P12 (node information n2 ′) on the LSI chip 2ch2, the nodes do not match. A three-dimensional LSI chip does not operate correctly. The same applies to the other pads. Next, an outline of LVS (layout versus schematic) verification, which is one of LSI chip layout verifications, will be described.

[LVS verification]
FIG. 2 is a flowchart for explaining an outline of LVS verification. In the LVS verification, it is verified whether the elements created in the logic / circuit design stage and the connection information between the elements are properly realized in the layout design. In the example of FIG. 2, specifically, in the LVS verification, the netlist nc extracted from the circuit diagram data CD is compared with the circuit diagram ny extracted from the layout data (layout drawing) LD of the LSI chip, and equivalent. It is verified whether or not.

  First, the layout verification program PR converts the net list obtained from the circuit diagram data CD into a transistor level net list nc (S11). The layout verification program PR extracts the netlist ny by restoring the transistor connection information from the layout data LD (S12). In LSI chip layout design, transistors may be divided to improve the degree of integration, and unused transistors may be arranged to facilitate layout correction. For this reason, for example, the layout verification program PR extracts the netlist ny by omitting redundant connection information from the restored transistor connection information.

  In step S12, when a plurality of equipotential elements have different node information in the layout data LD, the layout verification program PR cannot extract the netlist ny by assigning a plurality of node information to the same node. The element is, for example, a wiring pattern or a via. For example, when one element has node information “node 1” and another element has node information “node 2” among a plurality of elements connected on the layout data, a plurality of elements constituting one node Indicates that different node information is assigned to the element. In this case, the layout verification program PR cannot extract the net list based on the layout data and detects an error.

  On the other hand, if the netlists nc and ny are successfully extracted, the layout verification program PR compares the transistor level netlist nc extracted from the circuit diagram CD with the netlist ny extracted from the layout data LD (S13). . If the netlist nc extracted from the circuit diagram CD and the netlist ny extracted from the layout data LD are not equivalent (S14), the layout verification program PR detects an error.

  Here, an example of the LSI chip circuit diagram data CD and the LSI chip layout data LD, which are input data for LVS verification, will be described.

  FIG. 3 is a diagram illustrating an example of the circuit diagram data CD and a netlist ncl extracted from the circuit diagram data CD. 3A shows circuit diagram data CD1 of the inverter IV, and FIG. 3B shows circuit diagram data CD2 including the diode 33. The inverter IV shown in FIG. 3A includes a PMOS transistor 31 and an NMOS transistor 32. The source of the PMOS transistor 31 is connected to the power supply terminal VDD. The source of the NMOS transistor 32 is connected to the ground potential terminal VSS. The gates of the PMOS transistor 31 and the NMOS transistor 32 are made common and form the input terminal IN of the inverter IV. Further, the drains of the PMOS transistor 31 and the NMOS transistor 32 are made common to form the output terminal OUT of the inverter IV.

  Further, the lower diagram in FIG. 3A is an example of the netlist nc1 extracted from the circuit diagram data CD1. The netlist nc1 in the example of FIG. 3 has, for example, element name, source, gate, drain, back gate, type, and size information regarding the transistor. Specifically, the netlist nc1 includes, for the PMOS transistor 31, an element name “M0” indicating the PMOS transistor 31, a source “VDD”, a gate “IN”, a drain “OUT”, a back gate “VDD”, and a type “PMOS”. And size information “size information”. Similarly, the netlist nc1 includes, for the NMOS transistor 32, an element name “M1” indicating the NMOS transistor 32, a source “VSS”, a gate “IN”, a drain “OUT”, a back gate “VSS”, and a type “NMOS”. And size information “size information”.

  The circuit diagram data CD2 in FIG. 3B has a diode 33, an input terminal IN ′ connected to the diode 33, and an output terminal OUT ′. The diode 33 has two terminals of an anode (anode) VSS and a cathode (cathode) OUT, and the anode is connected to the inter-ground potential terminal VSS. The cathode OUT of the diode 33 is connected to a connection point on the wiring line between the input terminal IN ′ and the output terminal OUT ′. Further, the netlist nc2 extracted from the circuit diagram data CD2 has, for example, element names, anodes, cathodes, types, and size information for the diodes 33. Specifically, the netlist nc2 has the element name “D0”, the anode “VSS”, the cathode “VDD”, the type “DIODE”, and the size information “size information” indicating the diode 33 for the diode 33.

  FIG. 4 is a diagram showing an example of layout data LD1 and LD2 corresponding to the circuit diagram data ND1 and ND2 shown in FIG. 4A is an example of layout data LD1 corresponding to the circuit diagram data ND1 of FIG. 3, and FIG. 4B is an example of layout data LD2 corresponding to the circuit diagram data ND2 of FIG. The layout data LD1 and LD2 are composed of layout data of a plurality of layers. FIG. 4 shows the layout data LD1 and LD2 as a plan view.

  In FIG. 4, the layout data is schematically described based on a plan view, but the actual layout data includes numerical data such as area coordinate information. For example, the layout data LD1 and LD2 include coordinates (α, β) such as the upper left corner of a rectangular area in the two-dimensional coordinate system, information on the length of each side, etc. for each area such as an N well area (N-well). Have Alternatively, for example, the layout data LD1 and LD2 may have coordinate information of the vertexes of a polygon indicating the area for each area.

  In the layout data LD1 in FIG. 4A, for example, the inverter IV includes an N-well region (N-well) indicating a region surrounded by a dotted line, a diffusion region (Diffusion) indicated by a short diagonal line, and a Poly region (Poly) indicated by a horizontal line. ), A first metal region (Metal1) indicated by halftone dots, a second metal region (Metal2) indicated by short vertical lines, a connection region (Contact) indicated by a notch pattern between the substrate and the first metal region, the first And a black connection region (Via) between the metal region and the second metal region. The layout data LD1 in FIG. 4A is composed of three layers including a substrate layer. The lowermost substrate layer has an N well region (N-well) and a diffusion region (Diffusion). The second layer, which is an upper layer of the substrate layer, has a Poly region (Poly), a first metal region (Metal1), and a connection region (Contact) between the substrate and the first metal region. The uppermost third layer has a second metal region (Metal2) and a connection region (Via) between the first metal region and the second metal region.

  As shown in the layout data LD1 in FIG. 4A, the gate of the PMOS transistor 31 of the inverter IV and the poly region (Poly) indicating the gate of the NMOS transistor 32 are connected to each other via the connection region (Contact) IN. To the first metal region (Metal1) of the upper layer. The drain of the PMOS transistor 31 and the drain of the NMOS transistor 32 are connected to the common first metal region (Metal1) through the connection region (Contact). The common first metal region (Metal1) is connected to the uppermost second metal region (Metal2) via the connection region (Via) OUT. In the example of FIG. 4, the metal region and the connection region that are in a connection relationship are equipotential, and thus have common node information.

  Similarly to the layout data LD1 in FIG. 4A, the layout data LD2 in FIG. 4B is also composed of three layers including the substrate layer. Regions included in each layer are the same as those in FIG. In the layout data LD2 of FIG. 4B, the diode 33 includes an N well region (N-well), a diffusion region (Diffusion), a connection region (Contact), and a first metal region (Metal1). The first metal region (Metal1) constituting the diode 33 is a first metal region (Metal1) that connects the input terminal IN ′ and the output terminal OUT ′ formed by the second metal region (Metal2). Connect to the upper connection point.

  Returning to FIG. 2, in the LVS verification, netlists nc1 and nc2 extracted from circuit diagram data CD1 and CD2 as shown in FIG. 3 and layout data LD1 as shown in FIG. Each is compared with the netlist ny extracted from LD2, and it is determined that they are equivalent. In the LVS verification, LVS verification is performed for each LSI chip constituting a three-dimensional LSI chip. That is, in the LVS verification step S12, it is verified for each LSI chip whether or not a plurality of elements on the equipotential (same node) wiring have different node information in the layout data LD.

  However, since LVS verification is performed in units of LSI chips, it is verified whether a plurality of elements on equipotential (same node) wiring have different node information between layout data of a plurality of LSI chips. Can not. For example, the pads connected between the LSI chip 1ch1 and the LSI chip 2ch2 are equipotential, but the LVS verification cannot verify whether the connected pads have the same node information. Specifically, in the example of FIG. 1, when the pad P1 of the LSI chip 1ch1 and the pad P12 of the LSI chip 2ch2 are connected, no error can be detected by LVS verification.

  Therefore, in the layout verification method according to the present embodiment, a plurality of layers having position information of a plurality of elements including vias and wiring patterns in the first semiconductor device and having the same node information for a plurality of equipotential elements. The layout data of the top layer in the layout data is added to the layout data of the second semiconductor device attached to the first semiconductor device and synthesized as the virtual layer layout data. In the layout verification method according to the present embodiment, an error is detected when the layout data of the second semiconductor device including the virtual layer has different node information for a plurality of equipotential elements.

  FIG. 5 is a diagram for explaining the outline of the layout verification method in the present embodiment. The layout verification program PR in the present embodiment generates virtual layer layout data LDv based on, for example, one LSI chip (for example, LSI chip 2ch2) among LSI chips constituting a three-dimensional LSI chip. To do. The virtual layer layout data LDv indicates, for example, the layout data of the uppermost layer of the LSI chip 2ch2, and is connected to the LSI chip 1ch1 via a pump (in the example of FIG. 4, the second metal region and the connection region). The layout data of is shown.

  Then, the layout verification program PR synthesizes and adds the virtual layer layout data LDv to the layout data of the LSI chip 1ch1. Then, the layout verification program PR extracts a node between the LSI chip ch1 and the LSI chip ch2 in the step of extracting the netlist based on the layout data including the virtual layer of the synthesized LSI chip 1ch1v (S12 in FIG. 2). Inconsistency is detected. Specifically, the layout verification program PR verifies whether the element of the virtual layer (that is, the uppermost layer of the LSI chip 2ch2) and the element of the LSI chip 1ch1 having the same potential have the same node information. When having different node information, the layout verification program PR detects an error because the nodes between the LSI chip ch1 and the LSI chip ch2 do not match.

  As a result, the layout verification program PR uses the process of extracting the net list from the layout data included in the LVS verification (S12 in FIG. 2) to detect the node failure between the LSI chips constituting the three-dimensional LSI chip. A match can be detected. That is, the layout verification program PR can perform the layout verification of the three-dimensional LSI chip according to the existing LVS verification by using the layout data of the virtual layer.

  Next, the configuration of the layout verification apparatus 10 in the present embodiment and an example of a block diagram will be described.

[Configuration of layout verification device]
FIG. 6 is a diagram for explaining the configuration of the layout verification apparatus 10 in the present embodiment. 6 includes, for example, an input device 11, a display device 12, a communication interface 13, a CPU (Central Processing Unit) 14, a storage medium 15, and a memory 16. Each unit is connected to each other via a bus 17. The input device 11 is a keyboard or a mouse, for example, and the display device 12 is a display, for example. For example, the layout verification program PR in the present embodiment is stored in the memory 16 such as a RAM. The layout verification program PR implements the layout verification processing in the present embodiment by cooperating with the CPU 14.

  In the present embodiment, the storage medium 15 is a circuit diagram data CDa of two LSI chips (in this embodiment, LSI chip AchA and LSI chip BchB) constituting a three-dimensional LSI chip to be verified. , CDb, and layout data LDa, LDb. Details of the circuit diagram data CDa and CDb of the LSI chip A and LSI chip B and the layout data LDa and LDb of the LSI chip A and LSI chip B in this embodiment will be described later.

[Block diagram of layout verification device]
FIG. 7 is a diagram for explaining a block diagram of the layout verification apparatus 10 in the present embodiment. As illustrated in FIG. 7, the layout verification program PR of the layout verification apparatus 10 includes, for example, a netlist extraction unit 21, a comparison unit 22, and a virtual layer synthesis unit 23. The net list extraction unit 21 receives the circuit diagram data CDa and CDb of the LSI chip A and LSI chip B and the layout data LDa and LDb of the LSI chip A and LSI chip B stored in the storage medium 15 of FIG. , Each extracts a netlist. The comparison unit 22 compares the netlist extracted from the circuit diagram data CDa and CDb with the netlist extracted from the layout data LDa and LDb for each LSI chip, and determines whether or not they are equivalent. To do.

  Further, the virtual layer synthesis unit 23 generates the layout data of the virtual layer generated based on one LSI chip (for example, LSI chip BchB) among the plurality of LSI chips constituting the three-dimensional LSI chip. It is synthesized and added to a chip (for example, LSI chip AchA). Then, the net list extraction unit 21 extracts a net list based on the layout data of the LSI chip after synthesis (LSI chip AchA).

  Next, the flow of processing of the layout verification program PR in the present embodiment will be described with reference to a flowchart.

[flowchart]
FIG. 8 is a flowchart for explaining the layout verification processing in the present embodiment. The virtual layer synthesis unit 23 of the layout verification program PR extracts, for example, the layout data of the uppermost layer from the layout data LDb of the LSI chip B, and generates the layout data LDv of the virtual layer. Then, the virtual layer synthesis unit 23 of the layout verification program PR adds and synthesizes the virtual layer layout data LDv to the top layer of the layout data LDa of the LSI chip A (S21). Thereby, layout data LDbv is generated. Note that the layout verification program PR may generate virtual layer layout data LDv based on the layout data LDa of the LSI chip A and add it to the layout data LDb of the LSI chip B for synthesis.

  Note that the layout verification program PR performs LVS verification of the LSI chip BchB in the same manner as in the flowchart of FIG. That is, the net list extraction unit 21 of the layout verification program PR converts the net list obtained from the circuit diagram data CDb of the LSI chip B into a transistor level net list ncb (S11). Further, the layout verification program PR restores the transistor connection information from the layout data LDb, and extracts the netlist nyb (S12). Then, the comparison unit 22 of the layout verification program PR compares the transistor level netlist ncb extracted from the circuit diagram CDb with the netlist nyb extracted from the layout data LDb to verify whether they are equivalent ( S13).

  Subsequent to step S21, the layout verification program PR performs LVS verification of the LSI chip AchA. The net list extraction unit 21 of the layout verification program PR extracts the net list nyav based on the layout data LDav of the LSI chip A to which the virtual layer layout data LDv is added (S12). At this time, the net list extraction unit 21 detects an error in the layout data LDav of the LSI chip A after synthesis when a plurality of elements on the equipotential wiring have different node information. In other words, the netlist extraction unit 21 detects an error when a plurality of elements connected between the virtual layer layout data LDv and the LSI chip A layout data LDa and having the same potential do not have the same node information. To do.

  Thus, the layout verification program PR can detect an error when the nodes of the elements connected via the pump do not match between the LSI chip AchA and the LSI chip BchB. As described above, the layout verification program PR can detect node mismatch in the three-dimensional LSI chip according to the conventional LVS verification process by using the layout data LDv of the virtual layer.

  Then, the net list extraction unit 21 converts the net list obtained from the circuit diagram data CDa of the LSI chip AchA into a transistor level net list nca (S11). Then, the comparison unit 22 of the layout verification program PR compares the transistor level netlist nca extracted from the circuit diagram CDa with the netlist nyav extracted from the layout data LDav to verify whether they are equivalent ( S13).

[Concrete example]
Next, the layout verification process in the present embodiment will be described based on a specific example. First, circuit diagram data CDa, CDb and layout data LDa, LDb of the LSI chip AchA and the LSI chip BchB constituting the specific three-dimensional LSI chip are illustrated.

  FIG. 9 is a diagram illustrating an example of circuit diagram data CDa and CDb of the LSI chip A and the LSI chip B in a specific example. Further, in the circuit diagram data CDa of the LSI chip A of FIG. 9, two inverters IV shown in FIG. 3A are arranged in the vertical direction. Therefore, the circuit diagram data CDa of the LSI chip A of FIG. 9 has two input terminals IN1, IN2 and two output terminals OUT1, OUT2. In the example of FIG. 9, for example, each element having the same potential as the output terminal OUT1 in the circuit diagram data CDa has node information n1, and each element having the same potential as the output terminal OUT2 has node information n2.

  Further, in the circuit diagram data CDb of the LSI chip B in FIG. 9, two circuit diagrams shown in FIG. 3B are arranged in the vertical direction. The circuit diagram data CDb of the LSI chip B has two input terminals IN1 ′ and IN2 ′ and two output terminals OUT1 ′ and OUT2 ′. In the example of FIG. 9, for example, each element having the same potential as the output terminal IN1 ′ in the circuit diagram data CDb has node information n1, and each element having the same potential as the output terminal IN2 ′ has node information n2.

  FIG. 10 is a diagram showing an example of layout data LDa and LDb of LSI chip A and LSI chip B shown in FIG. The layout data LDa of the LSI chip A in FIG. 10 is layout data in which two layout data LD1 shown in FIG. 4A are arranged in the vertical direction. As described with reference to FIG. 4, the layout data LDa and LDb in FIG. 10 are also composed of three-layer layout data including the substrate layer.

  The LSI chip AchA and the LSI chip BchB in the specific example are bonded so that the chip surfaces face each other as indicated by arrows. Therefore, the output terminal OUT1 (node information n1) of the LSI chip AchA is connected to the input terminal IN1 ′ (node information n1) of the LSI chip BchB. According to the layout data LDa and LDb in FIG. 10, the node information of the output terminal OUT1 of the LSI chip AchA and the input terminal IN1 ′ of the LSI chip BchB are the same. The output terminal OUT2 (node information n2) of the LSI chip AchA is connected to the input terminal IN2 ′ (node information n2) of the LSI chip BchB, and the output terminal OUT2 of the LSI chip AchA and the input terminal IN2 ′ of the LSI chip BchB. The node information is the same.

  Therefore, according to the layout data LDa and LDb in FIG. 10, a plurality of elements on the equipotential wiring connected between the LSI chip AchA and the LSI chip BchB (in this example, the output terminals OUT1, OUT2, and the input terminal IN1 ′) , IN2 ′) have the same node information. That is, according to the layout data LDa and LDb in FIG. 10, the nodes between the LSI chips are matched.

  FIG. 11 is a diagram illustrating an example of a cross-sectional view of the layout data LDa and LDb in FIG. The cross-sectional view of FIG. 11 is a cross-sectional view when the LSI chip BchB is overlaid on the LSI chip AchA so that the surfaces of both LSI chips face each other. 11 is a cross-sectional view of the lines A1 to A2 of the LSI chip AchA and the lines B1 to B2 of the LSI chip BchB in the layout data LDa and LDb of FIG.

  First, a cross-sectional view of the LSI chip AchA will be described. As described above, the LSI chip AchA in the specific example includes the three layers L0A to L2A including the substrate layer. The substrate layer L0A has an N well region (N-well) and a diffusion region (Diffusion). Accordingly, the layout data of the substrate layer L0A has an N well region Wea1 and diffusion regions Dfa1 and Dfa2. The second layer L1A includes a poly region (Poly), a first metal region (Metal1), and a connection region (Contact) between the substrate and the first metal region. Therefore, the layout data of the second layer L1A has Poly regions Pla1 and Pla2, connection regions Cna1 and Cna2, and first metal regions M1a1 and M1a2. The uppermost layer L2A has a second metal region (Metal2) and a connection region (Via) between the first metal region and the second metal region. Therefore, the layout data of the third layer L2A includes the second metal regions M2a1 and M2a2 and the connection regions OUT1 and OUT2.

  Next, a cross-sectional view of the LSI chip BchB will be described. The LSI chip BchB in the specific example is also configured by three layers L0B to L2B including a substrate layer. The layout data of the substrate layer L0B has N well regions Web1, Web2 and diffusion regions Dfb1, Dfa2. The layout data of the second layer L1B includes connection regions Cnb1 and Cnb2 and first metal regions M1b1 and M1b2. The layout data of the uppermost layer L2B has second metal regions M2b1, M2b2, and connection regions IN1 ′, IN2 ′.

  Subsequently, a layout verification process based on the LSI chip AchA and the LSI chip BchB described in FIGS. 9 to 11 will be described. As described in the flowchart of FIG. 8, the virtual layer synthesis unit 23 of the layout verification program PR in the present embodiment extracts, for example, the layout data of the uppermost layer L2B of the LSI chip BchB as the virtual layer layout data Lv. Then, it is synthesized by adding to the layout data of the uppermost layer of the LSI chip AchA (S21 in FIG. 8).

  FIG. 12 is a diagram illustrating an example of virtual layer layout data based on the layout data LDa and LDb of FIG. The virtual layer layout data LDv1 shown in FIG. 12 includes the layout data of the second metal regions M2b1 and M2b2 among the layout data of the uppermost layer L2B of the LSI chip BchB. The virtual layer synthesis unit 23 of the layout verification program PR adds and synthesizes the virtual layer layout data LDv1 to the layout data of the uppermost layer L2A of the LSI chip AchA. Therefore, the layout data of the uppermost layer L2A of the LSI chip AchA after synthesis has second metal regions M2b1 and M2b2 in addition to the second metal regions M2a1 and M2a2 and the connection regions OUT1 and OUT2.

  Then, the net list extraction unit 21 of the layout verification program PR extracts a net list based on the layout data of the uppermost layer L2A of the LSI chip AchA generated by synthesis (S21). As described above, according to the layout data LDa and LDb in FIG. 10, an element having the same potential as the output terminal OUT1 in the LSI chip AchA (for example, the second metal region M2a1), the output terminal IN1 ′ in the LSI chip BchB, and the like. A potential element (for example, the second metal region M2b1) has node information n1. Further, an element equipotential to the output terminal OUT2 in the LSI chip AchA (for example, the second metal region M2a2), and an element equipotential to the output terminal IN2 ′ in the LSI chip BchB (for example, the second metal region M2b2). Has node information n2.

  In the layout data LDav of the LSI chip AchA after synthesis shown in FIG. 12, the second metal region M2a1 and the second metal region M2b1 whose regions in the uppermost layer L2A overlap each other have the same potential. The second metal region M2a1 and the second metal region M2b1 have the same node information n1. Then, in the layout data LDav of the LSI chip AchA after synthesis, the second metal region M2a2 and the second metal region M2b2 in which regions in the uppermost layer L2A overlap each other have the same potential. The second metal region M2a2 and the second metal region M2b2 have the same node information n2. That is, the layout data LDav of the LSI chip AchA after synthesis shown in FIG. 12 has the same node information for a plurality of equipotential elements. Therefore, the net list extraction unit 21 of the layout verification program PR can extract the net list based on the layout data LDav of the LSI chip AchA after synthesis.

  As shown in FIG. 12, the layout verification program PR in the present embodiment adds, for example, the layout data of the uppermost layer L2B of the LSI chip BchB to the layout data of the uppermost layer L2A of the LSI chip AchA and synthesizes it. At this time, the layout data of the uppermost layer L2B of the LSI chip BchB includes a wiring pattern (for example, second metal regions M2b1 and M2b2). Thereby, the layout verification program PR determines whether or not the equipotential wiring pattern in the layout data LDav of the uppermost layer L2A of the LSI chip AchA after synthesis has the same node information, so that the LSI chip AchA and the LSI A node mismatch with the chip BchB can be detected.

  The layout verification program PR in the present embodiment may be synthesized by adding the layout data of the uppermost layer of the LSI chip BchB as the layout data of the upper layer of the layout data of the uppermost layer of the LSI chip AchA. At this time, the layout data of the uppermost layer L2B of the LSI chip BchB includes vias (for example, connection regions IN1 ′ and IN2 ′) and wiring patterns (for example, second metal regions M2b1 and M2b2). Here, the layout data of the virtual layer when the layout data of the uppermost layer of the LSI chip BchB is added and combined as the layout data of the upper layer of the layout data of the uppermost layer of the LSI chip AchA will be described.

  FIG. 13 is a diagram for explaining another example of the layout data of the virtual layer based on the layout data LDa and LDb of FIG. The virtual layer layout data LDv2 shown in FIG. 13 includes second metal regions M2b1 and M2b2, connection regions IN1 ′ and IN2 ′, that is, layout data of the uppermost layer L2B of the LSI chip BchB. The virtual layer synthesis unit 23 of the layout verification program PR synthesizes the virtual layer layout data LDv2 as layout data of the layer L3A above the uppermost layer L2A of the LSI chip AchA. Therefore, the layout data LDav of the LSI chip A after synthesis has a hierarchy L3A having the second metal areas M2b1, M2b2 and the connection areas IN1 ′, IN2 ′ in addition to the hierarchies L0A to L2A.

  Then, the net list extraction unit 21 of the layout verification program PR extracts a net list based on the layout data of the uppermost layer L2A of the LSI chip AchA generated by synthesis (S21). The node information included in each element of the LSI chip AchA and the LSI chip BchB is as described with reference to FIG. In the layout data LDav of the LSI chip A after synthesis shown in FIG. 13, the second metal region M2a1 of the third layer L2A, the second metal region M2b1 of the uppermost layer L3A, and the input terminal IN1 ′ are equipotential. . Further, the second metal region M2a1, the second metal region M2b1, and the input terminal IN1 ′ have the same node information n1.

  In the layout data LDav of the LSI chip A after synthesis shown in FIG. 13, the second metal region M2a2 of the third layer L2A, the second metal region M2b2 of the uppermost layer L3A, and the input terminal IN2 ′ are equipotential. Become. The second metal region M2b2, the second metal region M2a2, and the input terminal IN2 ′ have the same node information n2. That is, the layout data LDav of the LSI chip A after synthesis shown in FIG. 13 has the same node information for a plurality of equipotential elements. Therefore, the net list extraction unit 21 of the layout verification program PR can extract the net list based on the layout data LDav of the LSI chip A after synthesis.

  Subsequently, the layout verification process will be described based on a specific example illustrating the layout data LDb of the LSI chip BchB shown in FIG. 10 and another layout data LDbv having a different layout.

  FIG. 14 is a diagram illustrating an example of another layout data LDa and LDbx of the LSI chip AchA and the LSI chip BchB in the specific example. The layout data LDa of the LSI chip A is the same as in FIG. On the other hand, the layout data LDbx of the LSI chip B is different from the layout data LDb of the LSI chip B of FIG. 10 in the arrangement positions of the input terminals IN1 ′ and IN2 ′. However, in the layout data LDbx of the LSI chip B in FIG. 14, as in FIG. 10, the input terminal IN1 ′ and the output terminal OUT1 ′ are connected, and the input terminal IN2 ′ and the output terminal OUT2 ′ are connected. That is, the layout data LDbx of the LSI chip B in FIG. 14 and the layout data LDb of the LSI chip B in FIG.

  The LSI chip AchA and the LSI chip BchB in FIG. 14 are bonded together as indicated by the arrows. Therefore, the output terminal OUT1 (node information n1) of the LSI chip AchA is connected to the input terminal IN2 ′ (node information n2) of the LSI chip BchB. According to the layout data LDa and LDbx in FIG. 14, the node information of the output terminal OUT1 of the LSI chip AchA and the input terminal IN2 'of the LSI chip BchB do not match. The output terminal OUT2 (node information n2) of the LSI chip AchA is connected to the input terminal IN1 ′ (node information n1) of the LSI chip BchB, and the output terminal OUT2 of the LSI chip AchA and the input terminal IN1 ′ of the LSI chip BchB. Node information does not match. That is, according to the layout data LDa and LDbx in FIG. 14, the nodes between the LSI chips are not matched.

  FIG. 15 is a diagram illustrating an example of a cross-sectional view of the layout data LDa and LDbx in FIG. A cross-sectional view of the LSI chip AchA of FIG. 15 is the same as FIG. The cross-sectional view of LSI chip BchB in FIG. 15 is a cross-sectional view of lines B1 and B2 of LSI chip BchB in layout data LDbx in FIG. Specifically, the layout data of the substrate layer L0B has an N well region Web1 and a diffusion region Dfb1. Further, the layout data of the second layer L1B includes connection regions Cnb1, Cnb2, and a first metal region M1b1. The layout data of the uppermost layer L2B has second metal regions M2b1, M2b2, and connection regions IN1 ′, IN2 ′.

  FIG. 16 is a diagram for explaining an example of virtual layer layout data based on the layout data LDa and LDbx in FIG. The virtual layer layout data LDv3 shown in FIG. 16 includes the layout data of the second metal regions M2b1 and M2b2 among the layout data of the uppermost layer L2B of the LSI chip BchB. Similarly to FIG. 12, the virtual layer synthesis unit 23 of the layout verification program PR adds and synthesizes the virtual layer layout data LDv3 to the layout data of the uppermost layer L2A of the LSI chip AchA. Therefore, the layout data of the uppermost layer L2A of the LSI chip AchA after synthesis has second metal regions M2b1 and M2b2 in addition to the second metal regions M2a1 and M2a2 and the connection regions OUT1 and OUT2.

  According to the layout data LDa and LDb in FIG. 14, the element (for example, the second metal region M2a1) equipotential with the output terminal OUT1 in the LSI chip AchA has the node information n1, and the output terminal IN2 ′ in the LSI chip BchB. An equipotential element (for example, the second metal region M2b1) has node information n2. An element equipotential to the output terminal OUT2 in the LSI chip AchA (for example, the second metal region M2a2) has node information n2, and an element equipotential to the output terminal IN1 ′ in the LSI chip BchB (for example, the second metal region M2a2). The metal region M2b2) has node information n1.

  In the layout data LDav of the LSI chip A after synthesis shown in FIG. 16, the second metal region M2a1 (node information n1) and the second metal region M2b1 (node information n2) where the regions in the uppermost layer L2A overlap each other are Although it is equipotential, it has different node information. In the layout data LDav of the LSI chip A after synthesis, the second metal region M2a2 (node information n2) and the second metal region M2b2 (node information n1) in which the regions in the uppermost layer L2A overlap each other are equipotential. However, it has different node information. That is, the layout data LDav of the LSI chip A after synthesis shown in FIG. 16 has different node information for a plurality of equipotential elements. Therefore, the net list extraction unit 21 of the layout verification program PR cannot extract the net list based on the layout data LDav of the LSI chip A after synthesis and detects an error.

  FIG. 17 is a diagram for explaining another example of the layout data of the virtual layer based on the layout data LDa and LDb of FIG. The virtual layer layout data LDv2 shown in FIG. 17 includes the layout data of the uppermost layer L2B of the LSI chip BchB. As shown in FIG. 17, the layout data LDav of the LSI chip A after synthesis has a layer L3A having second metal regions M2b1 and M2b2 and connection regions IN1 ′ and IN2 ′ in addition to the layers L0A to L2A.

  The node information included in each element of the LSI chip AchA and the LSI chip BchB is as described with reference to FIG. In the layout data LDav of the LSI chip A after synthesis shown in FIG. 17, the second metal region M2a1 (node information n1) of the third layer L2A, the second metal region M2b1 of the uppermost layer L3A, and the input terminal IN2 ′ ( Although node information n2) is equipotential, it has different node information. Further, in the layout data LDav of the LSI chip A after synthesis, the second metal region M2a2 (node information n2) of the third layer L2A, the second metal region M2b2 of the uppermost layer L3A, and the input terminal IN1 ′ (node information) n1) is equipotential, but has different node information.

  That is, the layout data LDav of the LSI chip A after synthesis shown in FIG. 17 has different node information for a plurality of equipotential elements. Therefore, the net list extraction unit 21 of the layout verification program PR cannot extract the net list based on the layout data LDav of the LSI chip A after synthesis and detects an error.

  As described above, the layout verification method according to the present embodiment has the position information of a plurality of elements including vias and wiring patterns in the first semiconductor device, and the same node information for a plurality of equipotential elements. A virtual layer synthesizing step of adding and synthesizing the top layer layout data in the plurality of layers of layout data as virtual layer layout data to the layout data of the second semiconductor device attached to the first semiconductor device; The layout verification method includes an error detection step of detecting an error when the layout data of the second semiconductor device including the virtual layer has different node information for a plurality of equipotential elements.

  In the layout verification method according to the present embodiment, verification is performed based on the other semiconductor device synthesized by adding the layout data of the virtual layer based on the layout data of the uppermost layer of one semiconductor device constituting the three-dimensional semiconductor device. By performing the above, it is possible to detect a mismatch in the connection relationship (node) of the elements between the semiconductor devices. Further, according to the layout verification method in the present embodiment, LVS verification is performed on a single semiconductor device, but a three-dimensional semiconductor device is based on LVS verification by using virtual layer layout data. It is possible to detect inconsistencies in the connection relationship (node) of elements between semiconductor devices. That is, according to the layout verification method in the present embodiment, the layout of the three-dimensional semiconductor device can be verified efficiently without making a major change to the existing LVS verification process.

  In the virtual layer synthesis step of the layout verification method according to the present embodiment, the layout data of the top layer of the first semiconductor device is added to the layout data of the top layer of the second semiconductor device and synthesized. Thus, when the layout data of the second semiconductor device including the virtual layer has different node information for a plurality of equipotential elements, the connection relation (node) of the elements between the semiconductor devices in the three-dimensional semiconductor device Inconsistency can be detected. For example, the layout data of the uppermost layer includes layout data of the wiring pattern.

  In the layout verification method according to the present embodiment, in the virtual layer synthesis step, the layout data of the uppermost layer of the first semiconductor device is used as the layout data of the upper layer of the layout data of the uppermost layer of the second semiconductor device. Add and synthesize. Thus, when the layout data of the second semiconductor device including the virtual layer has different node information for a plurality of equipotential elements, the connection relation (node) of the elements between the semiconductor devices in the three-dimensional semiconductor device Inconsistency can be detected. For example, the layout data of the uppermost layer includes layout data of vias and wiring patterns.

  In the layout verification method according to the present embodiment, the error detection step is included in the netlist extraction step based on the layout data in the LVS verification. According to the layout verification method in the present embodiment, the layout data of the virtual layer is used to efficiently verify the layout of the three-dimensional semiconductor device without greatly changing the existing LVS verification process. Can do.

  Also, the method for creating verification layout data in this embodiment has position information of a plurality of elements including vias and wiring patterns in the first semiconductor device, and the same node information for a plurality of equipotential elements A virtual layer synthesizing step of adding and synthesizing the layout data of the uppermost layer in the layout data of a plurality of layers as virtual layer layout data to the layout data of the second semiconductor device attached to the first semiconductor device. . An error is detected when the layout data of the second semiconductor device including the virtual layer has different node information for a plurality of equipotential elements.

  According to the layout verification method in the present embodiment, the layout data of the virtual layer based on the layout data of the uppermost layer of one semiconductor device constituting the three-dimensional semiconductor device is added to the other semiconductor device and synthesized. Thus, it is possible to generate verification layout data capable of detecting a mismatch in the connection relationship (node) of elements between semiconductor devices. As a result, it is possible to efficiently verify the layout of the three-dimensional semiconductor device without greatly changing the existing LVS verification process.

  The above embodiment is summarized as follows.

(Appendix 1)
A layout verification method for verifying a layout of a three-dimensional semiconductor device,
The layout data of the uppermost layer in the layout data of a plurality of layers having position information of a plurality of elements including vias and wiring patterns in the first semiconductor device and having the same node information for the plurality of elements of equipotential. A virtual layer synthesis step of adding and synthesizing the layout data of the second semiconductor device attached to the first semiconductor device as the layout data of the virtual layer;
An error detection step of detecting an error when the layout data of the second semiconductor device including the virtual layer has different node information for the plurality of equipotential elements.

(Appendix 2)
In Appendix 1,
A layout verification method for adding and synthesizing the layout data of the top layer of the first semiconductor device to layout data of the top layer of the second semiconductor device in the virtual layer synthesis step.

(Appendix 3)
In Appendix 2,
The layout verification method, wherein the layout data of the uppermost layer includes layout data of the wiring pattern.

(Appendix 4)
In Appendix 1,
In the virtual layer synthesis step, the layout verification method for adding and synthesizing the layout data of the uppermost layer of the first semiconductor device as layout data of an upper layer of the layout data of the uppermost layer of the second semiconductor device .

(Appendix 5)
In Appendix 4,
The layout verification method, wherein the layout data of the uppermost layer includes layout data of the via and the wiring pattern.

(Appendix 6)
In any one of supplementary notes 1 to 5,
The error detection step is a layout verification method included in a netlist extraction step based on layout data in LVS verification.

(Appendix 7)
A method for creating verification layout data for verifying a layout of a three-dimensional semiconductor device,
The layout data of the uppermost layer in the layout data of a plurality of layers having position information of a plurality of elements including vias and wiring patterns in the first semiconductor device and having the same node information for the plurality of elements of equipotential. As a virtual layer layout data, a virtual layer synthesis step of synthesizing in addition to the layout data of the second semiconductor device bonded to the first semiconductor device,
A method for creating verification layout data in which an error is detected when layout data of the second semiconductor device including the virtual layer has different node information for the plurality of equipotential elements.

(Appendix 8)
A layout verification program for causing a computer to execute a layout verification process of a three-dimensional semiconductor device,
The layout verification process includes
The layout data of the uppermost layer in the layout data of a plurality of layers having position information of a plurality of elements including vias and wiring patterns in the first semiconductor device and having the same node information for the plurality of elements of equipotential. A virtual layer synthesis step of adding and synthesizing the layout data of the second semiconductor device attached to the first semiconductor device as the layout data of the virtual layer;
An error detection step of detecting an error when the layout data of the second semiconductor device including the virtual layer has different node information for the plurality of equipotential elements.

(Appendix 9)
In Appendix 8,
A layout verification program for adding and synthesizing the layout data of the top layer of the first semiconductor device to layout data of the top layer of the second semiconductor device in the virtual layer synthesis step.

(Appendix 10)
In Appendix 8,
In the virtual layer synthesis step, a layout verification program for adding and synthesizing the layout data of the uppermost layer of the first semiconductor device as layout data of an upper layer of the layout data of the uppermost layer of the second semiconductor device .

(Appendix 11)
A verification layout data creation program for causing a computer to execute a verification layout data creation process for verifying a layout of a three-dimensional semiconductor device,
The verification layout data creation process includes:
The layout data of the uppermost layer in the layout data of a plurality of layers having position information of a plurality of elements including vias and wiring patterns in the first semiconductor device and having the same node information for the plurality of elements of equipotential. As a virtual layer layout data, a virtual layer synthesis step of synthesizing in addition to the layout data of the second semiconductor device bonded to the first semiconductor device,
A verification layout data creation program for detecting an error when layout data of the second semiconductor device including the virtual layer has different node information for the plurality of equipotential elements.

10: layout verification device, 11: input device, 12: display device, 13: communication interface, 14: CPU (Central Processing Unit), 15: storage medium, 16: memory, PR: layout verification program, chA: LSI chip A ChB: LSI chip B, CDa: LSI chip A circuit diagram data, CDb: LSI chip B circuit diagram data, LDa: LSI chip A layout data, LDb: LSI chip B layout data

Claims (9)

A layout verification method for verifying a layout of a three-dimensional semiconductor device,
The layout data of the uppermost layer in the layout data of a plurality of layers having position information of a plurality of elements including vias and wiring patterns in the first semiconductor device and having the same node information for the plurality of elements of equipotential. A virtual layer synthesis step of adding and synthesizing the layout data of the second semiconductor device attached to the first semiconductor device as the layout data of the virtual layer;
An error detection step of detecting an error when the layout data of the second semiconductor device including the virtual layer has different node information for the plurality of equipotential elements. In claim 1,
A layout verification method for adding and synthesizing the layout data of the top layer of the first semiconductor device to layout data of the top layer of the second semiconductor device in the virtual layer synthesis step. In claim 2,
The layout verification method, wherein the layout data of the uppermost layer is layout data including the wiring pattern. In claim 1,
In the virtual layer synthesis step, the layout verification method for adding and synthesizing the layout data of the uppermost layer of the first semiconductor device as layout data of an upper layer of the layout data of the uppermost layer of the second semiconductor device . In claim 4,
The layout verification method, wherein the layout data of the uppermost layer is layout data including the via and the wiring pattern. In any one of Claims 1 thru | or 5,
The error detection step is a layout verification method included in a netlist extraction step based on layout data in LVS verification. A method for creating verification layout data for verifying a layout of a three-dimensional semiconductor device,
The layout data of the uppermost layer in the layout data of a plurality of layers having position information of a plurality of elements including vias and wiring patterns in the first semiconductor device and having the same node information for the plurality of elements of equipotential. As a virtual layer layout data, a virtual layer synthesis step of synthesizing in addition to the layout data of the second semiconductor device bonded to the first semiconductor device,
A method for creating verification layout data in which an error is detected when layout data of the second semiconductor device including the virtual layer has different node information for the plurality of equipotential elements. A layout verification program for causing a computer to execute a layout verification process of a three-dimensional semiconductor device,
The layout verification process includes
The layout data of the uppermost layer in the layout data of a plurality of layers having position information of a plurality of elements including vias and wiring patterns in the first semiconductor device and having the same node information for the plurality of elements of equipotential. A virtual layer synthesis step of adding and synthesizing the layout data of the second semiconductor device attached to the first semiconductor device as the layout data of the virtual layer;
An error detection step of detecting an error when the layout data of the second semiconductor device including the virtual layer has different node information for the plurality of equipotential elements. A verification layout data creation program for causing a computer to execute a verification layout data creation process for verifying a layout of a three-dimensional semiconductor device,
The verification layout data creation process includes:
The layout data of the uppermost layer in the layout data of a plurality of layers having position information of a plurality of elements including vias and wiring patterns in the first semiconductor device and having the same node information for the plurality of elements of equipotential. As a virtual layer layout data, a virtual layer synthesis step of synthesizing in addition to the layout data of the second semiconductor device bonded to the first semiconductor device,
A verification layout data creation program for detecting an error when layout data of the second semiconductor device including the virtual layer has different node information for the plurality of equipotential elements.

Images