JPH06282604A - Layout verifying device - Google Patents

Abstract

PURPOSE:To provide a layout verifying device capable of efficiently and exactly detecting nodes causing the unmatching of connection when a circuit diagram does not match with a layout. CONSTITUTION:An identification value imparting means 1 receives an inputted net list or the processing result of a node matching detection means 3 and imparts an identification value which is a kind of attributes to a matching node. A division means 2 receives the result of the identification value imparting means 1 and calculates the attributes for unmatching nodes. Based on the calculated attributes, the unmatching nodes are divided into groups. The node matching detection means 3 receives information grouped by the division means 2, detects the group in one-to-one correspondence and makes the nodes matching. The matching of two net lists is detected when no more unmatching node is present and the unmatching is detected when the unmatching node is present and the group in the one-to-one correspondence is not detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for verifying the matching of electrical connection between a designed layout and a specification such as a circuit diagram.

[0002]

2. Description of the Related Art Layout verification is a process of collating electrical connection information extracted from layout information of an LSI with electrical connection information obtained from a specification such as a circuit diagram to cause a mismatch of connection states. Is to detect a connection point that exists. This collation may be performed at the transistor level or may be performed at a higher level where the IC or the like is arranged. A netlist is used as the electrical connection information used for this verification. A netlist is a graph obtained by connecting parts connected to each other with circuit elements or the like with lines in a layout, a circuit diagram, or the like, where a part having the same potential, for example, a wired part is one node. .

FIG. 2 is a block diagram showing an example of a general layout verification apparatus. In the figure, 41 is a circuit diagram netlist extracting function, 42 is a layout netlist extracting function, and 43 is a collating function. As shown in FIG. 2, the layout verification apparatus extracts a connection information from a circuit diagram and creates a netlist, and a circuit diagram netlist extraction function 41,
The layout netlist extraction function 42 extracts the connection information from the layout and creates a netlist, and the collation function 43 collates the electrical connection information using the two netlists.

As a collation method in the conventional collation function 43, two methods are performed. One of them is to give the corresponding node as the initial corresponding node in advance,
This initial corresponding node is made to correspond, and the remaining unmatched nodes, that is, unmatched corresponding nodes are matched so that the number of unmatched nodes is minimized, and the node combination at that time is matched. The result is a method.

However, if connection verification is performed only on the basis of minimizing the number of nodes that cause a mismatch, the same circuit is repeatedly arranged like a memory, and an LSI having signal lines for controlling those circuits at once exists. However, if the connection of the signal line is wrong, there is a problem in that it is not possible to detect an essentially mismatched node between the circuit diagram and the layout when verifying the layout. In order to solve this problem, for example, in Japanese Patent Laid-Open No. 4-95168,
A method has been proposed in which a corresponding node is searched from many connected circuit elements such as the above-mentioned signal line to detect an essentially mismatched node. However, even in this method, since a node having a large number of connected circuit elements is set as a matching node, there is a problem that if this node causes a mismatch, it may not be detected.

As another method, an attribute is given to each node of the netlist, a new attribute is calculated by the attribute of the adjacent node and the given attribute, and the range to be referred to is gradually widened by repeating this. When there is a one-to-one correspondence between nodes having only one attribute in the netlist, there is a matching method in which this is a matching node. With this method, even if the last one node is reached, the matching result cannot be obtained until the attribute values match, and it also takes time because the entire netlist is always searched for a matching node. was there.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and when a circuit diagram and a layout do not match, a node causing a connection mismatch can be detected efficiently and accurately. It is an object of the present invention to provide a layout verification device that can be used.

[0008]

According to a first aspect of the present invention, a first netlist extracted from a specification such as a circuit diagram is collated with a second netlist extracted from a layout. In a layout verification device for performing a layout verification, an identification value giving means for giving an identification value as one of attributes to a matching node, and an attribute of an unmatched node adjacent to an unmatched node and an attribute of the matched node And a dividing unit that calculates a new attribute and divides the unmatched nodes into groups according to the attribute, and a node matching unit that detects a one-to-one correspondence group among the groups divided by the dividing unit and matches the nodes. , The first and second netlists have at least one initial corresponding node that is a matching node, and there are no unmatched nodes or Identification value providing means to the one-to-one correspondence of a group is no longer detected, dividing means, is characterized in that to execute a node matching means.

According to the second aspect of the invention,
2. The layout verification apparatus according to claim 1, wherein when the node matching means has an unmatched node and a group having a one-to-one correspondence is not detected, a matched node is detected for each group and is set as an unmatched node. It is characterized by further comprising a node collating means for minimizing the number of remaining nodes.

[0010]

According to the present invention, in layout verification, an identification value is given to a matching node as one of attributes, and a new attribute is created based on the attributes of the unmatching node adjacent to the unmatching node and the attributes of the matching node. It calculates and divides the unmatched nodes into groups according to the calculated attributes, detects the one-to-one correspondence group among the divided groups, and matches the nodes, so that the initial correspondence node and the match in the netlist are verified. Matching proceeds from a node connected to the node or a unique node in the netlist, so that the matching can be performed efficiently.

Further, by the above-mentioned collation, when plural nodes have the same attribute and plural corresponding node candidates exist in the same group, further collation cannot be performed, the collation is performed. For unmatched nodes that could not be matched, the node matching means selects a combination with less contradiction for each group and advances matching, so that matching is performed even if there are nodes with similar attributes. You can

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a first layout verification apparatus according to the present invention.
It is a block diagram showing an example of. Reference numeral 1 is an identification value giving means, 2 is a dividing means, and 3 is a node coincidence detecting means. Specifications such as a circuit diagram to be verified and the layout of the LSI are converted into a netlist in advance and input. At this time, at least one initial corresponding node to be the matching node is designated. Here, the netlist extracted from the circuit diagram is called a circuit diagram netlist. The netlist extracted from the layout will be called a layout netlist.

The identification value giving means 1 receives the input netlist or the processing result of the node matching detection means 3 and gives the matching node an identification value which is a kind of attribute. The dividing unit 2 receives the result of the identification value assigning unit 1, and first determines whether or not there is an unmatched node. As a result, if there is no unmatched node, it means that the two input netlists match, so a matching signal is output, and the processing ends. If there is an unmatched node, a new attribute is calculated for the unmatched node based on the attribute of the adjacent unmatched node and the attribute of the matched node. Unmatched nodes with the same calculated attributes are extracted and divided into groups. The node coincidence detection means 3 receives the information divided into groups by the division means 2 and detects a one-to-one correspondence group to make the nodes coincide. That is, one element node exists in the divided group, and 2
A node having a correspondence between two netlists is a matching node. If a matching node is found, the process returns to the identification value assigning means 1 and the matching node found is also used for matching. If there is an unmatched node but no matching node is found, the matching node is not found even if the above-mentioned matching process is repeated, and the process is terminated and the unmatched node is output.

As the attribute information calculated by the dividing means 2 and used for grouping, for example, the number of terminals of the circuit element connected to the node, that is, the number of branches coming out of the node and the circuit element. It is possible to use the sum of values preset depending on the type of the terminal (hereinafter referred to as the terminal value). Further, it is possible to give a unique identification value to each correspondence only to the matched nodes and use the information of the sum of the identification values of the adjacent matching nodes (hereinafter referred to as the adjacent value). In addition, for example, the value obtained by adding the terminal value and the adjacent value is used as the attribute value, or the value obtained by adding the identification value and the terminal value of the matching node is added to the adjacent matching node, and that value is used instead of the adjacent value. Various values such as used can be used. These values can be appropriately selected and used in combination.

An identification value may be given to the initial corresponding node of the given netlist in advance. In this case, since it is not necessary to add the identification value to the initial corresponding node first, the information of the netlist is given to the dividing means 2, the dividing means 2, the node matching means 3, and the identification value giving means 1.
You can proceed in the order of.

FIG. 3 is a flow chart for explaining an example of the operation of the first embodiment of the layout verification apparatus of the present invention. In S11, when the netlist of the circuit diagram and the layout is given, the identification value giving means 1 matches the preliminarily given initial corresponding nodes, and the matched circuit diagram netlist node and the layout netlist node are matched. Give the same identification value. In S12, the dividing unit 2 determines whether or not there is an unmatched node. If there is no unmatched node, it means that all the nodes in the circuit diagram netlist and the nodes in the layout netlist are matched, so that a signal indicating that the circuit diagram and the layout are matched is output and the process is ended. If there is an unmatched node, the process proceeds to S13.

In S13, in the dividing means 2, for the unmatched node, the number of branches connected to the node, the terminal value,
Attributes such as adjacent values are calculated, and the nodes of the schematic netlist and the nodes of the layout netlist are divided into groups based on those attributes. It is highly possible that a schematic node and a layout node belonging to the same attribute group correspond to each other. Therefore, in S14, the node matching means 3
At, it is determined whether there is a group in which the nodes of the circuit diagram netlist and the nodes of the layout netlist have a one-to-one correspondence. If there is a one-to-one correspondence group, in S15, it is determined as a matched node. In S16, the identification value giving means 1 gives an identification value to the newly matched node. Then, the process returns to S12 to continue the processing. In S14, when a group corresponding to one-to-one is not found, it is determined that the circuit diagram and the layout do not match, and the mismatch information is output.

FIG. 4 is a block diagram showing a rather concrete example of the first embodiment of the layout verification apparatus of the present invention. In the figure, 21 is a node set storage means, 22 is a matched node storage means, 23 is a non-matched node storage means, 2
4 is the adjacent information extracting means, 25 is the in-set node comparing means,
26 is an unmatched node reorganization means, 27 is an inter-set node comparison means, 28 is a matched node extraction means, 29 is a result notification means, and 30 is an identification value giving means. In this specific example, the identification value given to the initial matching node is given in advance and stored in the matching node storage means 22.

The node set storage means 21 stores at least one initial corresponding node and a node set of a circuit diagram netlist and a layout netlist having the number of elements, the type of elements, and the connection relationship between the nodes. . The coincidence node storage unit 22 stores a coincidence node set of the nodes of the circuit diagram netlist and the layout netlist. In the initial state, the initial matching node of each netlist is stored. The unmatched node storage means 23 stores unmatched node sets. In the initial state, among the node sets of each netlist, the nodes other than the initial corresponding node are stored as the unmatched node set.

The adjacency information extraction means 24 includes the adjacency relation of nodes from the node set storage means 21, the number of nodes and the number of elements adjacent to the unmatched nodes stored in the unmatched node storage means 23, and the matched node storage means. The number of matching nodes stored in No. 22 and the identification value of the matching node are extracted,
Calculate the value of the attribute of each unmatched node. The value of this attribute is stored in the unmatched node storage means 23 in association with each unmatched node. The in-set node comparing means 25 compares the attribute values extracted and calculated by the adjacent information extracting means 24 for each of the circuit diagram netlist and the layout netlist. Unmatched node reorganization means 26
Based on the comparison result by the in-set node comparison unit 25, the unmatched nodes included in the unmatched node storage unit 23 are grouped and reorganized, and the result is stored in the unmatched node storage unit 23.

The inter-set node comparison means 27 includes the attributes calculated by the adjacency information extraction means 24 between the unmatched node sets of the schematic netlist and the layout netlist reorganized by the unmatched node reorganization means 26. Compare the values. The coincident node extraction means 28 detects a coincident node pair based on the comparison result by the inter-set node comparison means 27. Each node pair for which a new match is detected is given a unique identification value, stored in the matched node storage means 22, and deleted from the unmatched node storage means 23.

When these processes are repeated and there are no nodes included in the unmatched node storage means 23, the result notifying means 29 outputs that the circuit diagrams and layouts match. Also, the coincidence node extracting means 28
Therefore, when no new matching node pair is detected and there is a node stored in the unmatched node storage means 23, it is determined that the circuit diagram and the layout do not match, and the result notification means 29 stores the unmatched node storage. The unmatched node stored in the means 23 is output as the unmatched node.

As described above, in the first embodiment, by utilizing the number of branches, the type of circuit element, the text information, and the matched node information, the nodes already connected to the matched node are used. Or, matching will proceed from a unique node in the netlist. However, in the above-described first embodiment, if there is no one-to-one correspondence when divided into groups, it is not identified as a match, so it is considered that there are nodes with similar attributes. There is a problem that the verification ends even if the node remains. In order to avoid this, if there is a non-matching node in the node matching means 3 in FIG. 1 and a group having a one-to-one correspondence cannot be found, another matching means is used to verify the remaining nodes. Good.

FIG. 5 is a block diagram showing a second embodiment of the layout verification apparatus of the present invention. In the figure, the same parts as those in FIG. Reference numeral 4 is a node matching means. The node matching unit 4 detects a matching node in each group divided by the node matching unit 3 and minimizes the number of nodes left as unmatched nodes. A conventionally used method can be used for the detection of the coincident node performed for each group. When the node matching unit 4 is executed, a match has already been detected in most of the nodes, and unmatched nodes are also grouped. The actual matching process performed by the node matching unit 4 is the entire matching. Only a small part of the processing. Therefore, even if a conventional time-consuming matching method is applied to the node matching means 4, it does not affect the overall processing time so much. For example, even if you use a matching method that verifies all combinations,
The verification time is proportional to the square of the number of nodes, but most of the nodes are matched by attribute matching and unmatched nodes are grouped, so the number of combinations is very small and the processing is very short. Ends with.

FIG. 6 is a flow chart for explaining an example of the operation of the second embodiment of the layout verification apparatus of the present invention. In the figure, the operation of S11 to S16 is the same as the operation of the first embodiment. That is, the number of branches, the type of circuit element, the text information, the information node of the matched node, etc. are used as attributes, and the matching is performed by dividing the groups into groups based on the attributes. To do. These operations are realized by the identification value assigning unit 1, the dividing unit 2, and the node matching unit 3.

In S14, if a one-to-one correspondence group is not found even though there are still unmatched nodes, that is, a plurality of nodes have the same attribute and a plurality of corresponding groups belong to the same group. In the second embodiment, if the node candidate is present and further verification cannot be performed, the node verification means 4 performs the verification. In S17, the node matching means 4
Selects a combination of nodes that causes the least contradiction when they are matched in the same group, and performs connection matching so that they match. The result of this collation processing is determined in S18, and if there is no unmatched node, it is determined that the circuit diagram and the layout match, and a matching signal is output and the processing ends. If there are still unmatched nodes, it is determined that the circuit diagram and the layout do not match, a mismatch signal is output, and the process ends. At this time, the number of unmatched nodes is decreased as a result of the matching by the node matching unit 4, and the unmatched portion can be presented to the user more accurately.

Next, specific examples of the layout verifying apparatus of the present invention in the first and second embodiments will be described. FIG. 7 is an explanatory diagram of a circuit example used in a concrete example of the first and second embodiments of the layout verification apparatus of the present invention, and FIG. 8 is a net list of the circuit of FIG. In the figure, 101 to 11
5 is a 2-terminal element, 201 to 206 are 3-terminal elements, 30
1 is a power source, 401 to 420 are wirings, and 501 to 520
Is a node. Consider a circuit in which each element is wired as shown in FIG. The two-terminal elements 101 to 115 have weights of 1 and 2 assigned to their respective terminals. Also,
Weights of 3, 4, and 5 are given to the terminals of the three-terminal elements 201 to 206, respectively. Furthermore, power source 30
A weight of 6 is given to the negative electrode of 1 and a weight of 7 is given to the positive electrode.
The circuit shown in FIG. 7 is converted into the netlist shown in FIG. In FIG. 8, each node 501 to 520
Correspond to the wirings 401 to 420 in FIG. The initial corresponding node designated at this time is the node 501.

First, the case where the circuit diagram netlist and the layout netlist match will be described with reference to the flowchart shown in FIG. 6 and the process diagrams shown in FIGS. 9 to 12. 9 to 12 are process diagrams when the netlists of the specific example match. As the attribute used in the following description, the number of branches emerging from the node, the terminal value, and the adjacent value are used as a set, and the identification value is used in the matching node. Further, it is assumed that both the circuit diagram netlist and the layout netlist are the netlists shown in FIG.

When the netlist and the initial corresponding node shown in FIG. 8 are given, first, in S11, the initial corresponding nodes 501 of the two netlists are made to coincide with each other and an identification value is given. Here, 1 is given as the identification value.
In S12, there are still unmatched nodes.
Proceed to 13. In S13, the attribute of the unmatched node is calculated. The calculated result is shown in FIG. Numerical values in parentheses are attribute values, the first numerical value is the branch number, the second is the terminal value, and the last is the adjacent value. Also, the black circled nodes are coincident nodes, and a single numerical value is an identification value. Once the attributes are calculated,
Grouping is performed based on this attribute. Here, as an example, groups having the same attribute are grouped together. Then, the nodes 503, 505, 50
7 groups and nodes 504, 506, 508, 51
1,514, 516, 518 groups and node 50
Group of 9,515,517,519 and node 51
A group of 2,513 is composed of a plurality of nodes, and each of the nodes 502, 510, 520 is composed of one node. In S14, it is determined whether or not there is a one-to-one correspondence group. Nodes 502, 51
Since 0,520 is a group corresponding to one to one,
In S15, these nodes are matched. Then, in S16, the newly matched nodes 502, 5
An identification value is given to 10,520. For example, the identification value 2 is given to the node 502, the identification value 3 is given to the node 510, and the identification value 4 is given to the node 520. And S
Return to 12.

At S12, since there is an unmatched node, the process proceeds to S13. In S13, the attribute of the unmatched node is calculated. The calculated result is shown in FIG. When the attribute is calculated, grouping is performed based on this attribute. Then, the nodes 504, 506, 508, 51
The group of 1,514, 516, 518 is the node 50
4, 506, 508, a node 511, and nodes 514, 516, 518. In addition, nodes 509, 515, 517, and 519
Group of nodes 509 and node 51
Divided into 5, 517, 519 groups. The other groups are unchanged. Here, the node 511 and the node 509 form a group corresponding to one to one. S1
4, it is determined that there is a one-to-one correspondence group, and in S15, the one-to-one correspondence node 5
09 and 511 are matched. This matching node 509, 5
Reference numeral 11 is a node retrieved from the node 510 other than the initial corresponding node. As described above, according to the method of the present invention, the matching nodes also spread from nodes other than the initial corresponding node. In S16, an identification value is given to the nodes 509 and 511 that have newly become coincident nodes. For example, the identification value 5 is given to the node 509, and the identification value 6 is given to the node 511. Then, the process returns to S12.

At S12, since there is an unmatched node, the process proceeds to S13. In S13, the attribute of the unmatched node is calculated. The calculated result is shown in FIG. When the attribute is calculated, grouping is performed based on this attribute. Then, the nodes 503, 504, 514, 515
Are divided from each group to become independent groups. In S14, it is determined that there is a one-to-one correspondence group, and in S15, the one-to-one correspondence nodes 503, 504, 514, and 515 are matched. In S16, the identification value is given to the nodes 503, 504, 514, 515 that have newly become coincident nodes. Then, the process returns to S12.

Since an unmatched node exists in S12, the attribute of the unmatched node is calculated in S13. This state is shown in FIG. However, since there is no group that is further divided into one-to-one correspondence, the process proceeds from S14 to S17. In S17, the correspondence of the nodes in the group with the least contradiction is checked. The collation at this time is
There are only 10 unmatched nodes. As a result, the remaining unmatched nodes 505 to 508 and 516
Through 519 matches will be matched. In S18, it is confirmed that there is no unmatched node, and a signal indicating that the circuit diagram and the layout match is output.

Next, when the circuit diagram netlist and the layout netlist do not match, based on the flowchart shown in FIG. 6, the circuit example shown in FIGS. 7 and 13, and the process diagrams shown in FIGS. 14 and 15. explain. FIG. 13 is an explanatory diagram of an erroneous circuit example, and FIGS. 14 and 15 are process diagrams when the netlists of the specific examples do not match. In this specific example, as shown in FIG. 13, consider a case where the two-terminal element 107 is connected in reverse. Here, it is assumed that the circuit diagram netlist is based on the circuit shown in FIG. 7 and the layout netlist is based on the layout corresponding to the circuit shown in FIG. The initial corresponding node is node 501.

First, in S11, the initial corresponding nodes are made to match, and 1 is given as an identification value. And S
12, it is determined that there is an unmatched node, and S13
Proceed to. At S13, attributes are calculated for the unmatched nodes. The calculated attributes are as shown in FIG. 9 corresponding to FIG. 7 in the schematic netlist, but in the layout netlist, the attributes of the nodes 502 and 508 are different due to the reverse connection of the two-terminal element 107. The result is as shown in FIG. Here, the node corresponding to one-to-one is only the node 510. Although the node 520 is uniquely determined in the schematic netlist, the node 520 is determined in the layout netlist.
2 and the node 520 have the same attribute, and are not one-to-one correspondence nodes. Also, the node 508 in the layout netlist is uniquely determined as an attribute, but since there is no node in the corresponding circuit netlist, 1
It is not a one-to-one correspondence node. Grouping is performed based on the attributes, it is determined in S14 that there is a one-to-one correspondence node, and in S15, the one-to-one correspondence node 51
Match 0 and give an identification value of 2 in S16. Then, the process returns to S12 and shifts to the second processing.

Similarly, in the second processing, the node 50
Since 9,511 correspond one-to-one, these nodes are matched and the identification values 3 and 4 are given. In the third processing,
Since the nodes 503, 504, 514, and 515 correspond to each other on a one-to-one basis, these nodes are matched and the identification values 5, 6,
Give 7,8. The nodes 520 correspond one-to-one with the fourth processing. This state is shown in FIG. FIG. 15 (A)
Shows the process of the schematic netlist, and FIG. 15B shows the process of the layout netlist. As a result, the attribute of the node 502 in the layout netlist is uniquely determined, but it does not become a one-to-one correspondence node because there is no corresponding node in the schematic netlist. The identification value 9 is given to the node 520.

In the fifth processing, there is no one-to-one corresponding node. Therefore, in S14, it is determined that there is no one-to-one correspondence group, and the process proceeds to S17 to check the correspondence of nodes in the group with the least contradiction. At this time, the nodes to be examined need only be nine unmatched nodes. By this collation, the nodes 505, 506, 507,
It is determined that 512, 513, 516, 517, 518, and 519 correspond, but the nodes 502 and 508 do not match. Therefore, in S18, it is determined that there is an unmatched node, and a signal indicating that the circuit diagram and the layout do not match is output. At this time, the nodes 502 and 508 that have become unmatched nodes are output.
According to this output, for example, a mismatched portion can be displayed on a display or the like on which the circuit diagram or the layout is displayed. As a result, the user can recognize the mismatched portion. At this time, the nodes 502 that do not match
Since the node 508 and the node 508 are connected to the two-terminal element 107, the two-terminal element 107 connected in reverse can be correctly shown to the user. Based on this, the user may inspect the two-terminal element 107.

[0037]

As is apparent from the above description, according to the present invention, in layout verification, when a circuit diagram and a layout do not match, a node causing a connection mismatch can be efficiently detected. There is an effect that it becomes possible. In addition, even if there is an unmatched node left by the method of advancing the matching depending on the attribute, the true unmatched node is selected from among the unmatched nodes by combining the matching methods that match the nodes so that the unmatched nodes are minimized. Is effective.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a layout verification device of the present invention.

FIG. 2 is a block diagram showing an example of a general layout verification apparatus.

FIG. 3 is a flowchart for explaining an example of the operation of the first exemplary embodiment of the layout verification apparatus of the present invention.

FIG. 4 is a block configuration diagram showing a rather specific example of the first embodiment of the layout verification apparatus of the present invention.

FIG. 5 is a block diagram showing a second embodiment of the layout verification device of the present invention.

FIG. 6 is a flowchart for explaining an example of the operation of the second embodiment of the layout verification device of the present invention.

FIG. 7 is an explanatory diagram of a circuit example used in a specific example in the first and second embodiments of the layout verification device of the present invention.

FIG. 8 is a netlist for the circuit of FIG.

FIG. 9 is a part of a process diagram when the netlists of the specific example match.

FIG. 10 is a part of a process diagram when the netlists of the specific example match.

FIG. 11 is a part of a process diagram when the netlists of the specific example match.

FIG. 12 is a part of a process diagram when the netlists of the specific example match.

FIG. 13 is an explanatory diagram of an erroneous circuit example.

FIG. 14 is a part of a process chart when the netlists of the specific example do not match.

FIG. 15 is a part of a process chart when the netlists of the specific example do not match.

[Explanation of symbols]

1 identification value assigning means, 2 dividing means, 3 node matching detecting means, 4 node matching means, 21 node set storing means, 22 matching node storing means, 23 unmatched node storing means, 24 adjacent information extracting means, 25 in-set node Comparison means, 26 unmatched node reorganization means, 27 inter-set node comparison means, 28 matched node extraction means, 29 result notification means, 30 discriminant value giving means.

Claims (2)

[Claims] 1. A layout verification device for verifying a layout by collating a first netlist extracted from a specification such as a circuit diagram with a second netlist extracted from a layout, and a matching node having an attribute of 1 Identification value giving means for giving an identification value as one, and dividing means for calculating a new attribute based on the attribute of the unmatched node adjacent to the unmatched node and the attribute of the matched node and dividing the unmatched node into groups by the attribute And a node matching means for matching a node by detecting a one-to-one correspondence group among the groups divided by the dividing means, wherein the first and second netlists are at least one matching node. Identification value assigning means having initial corresponding nodes until there are no unmatched nodes or no one-to-one correspondence group is detected. A layout verification apparatus, characterized in that the layout verification apparatus executes a dividing unit and a node matching unit. 2. The number of nodes left as unmatched nodes by detecting the matched nodes in each group when the unmatched nodes exist and no one-to-one correspondence group is detected in the node matching means. The layout verification apparatus according to claim 1, further comprising a node verification unit that minimizes the node verification unit.