JP2009020725A - Method for verificating layout data - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for verificating layout data with high precision in LSI design. <P>SOLUTION: At first, MRC processing for verifying final data γ for manufacturing a mask. The MRC processing includes: a step 151 of generating an α formula indicating all layers necessary for forming a device and a β formula indicating any layer which should not exist in order to form the device; a step 152 of automatically generating a rule file 3 for recognizing a correct layer-constructed device; a step 153 of specifying each device, and specifying the physical position; and a step of determining the layout data on the basis of the α and β formulas about each specified device. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for automatically verifying whether layout data of a large-scale semiconductor integrated circuit (hereinafter referred to as LSI) is properly designed.

  FIG. 6 shows a conventional LSI manufacturing flow. First, layout data (also referred to as design data or layout pattern data) is created based on an LSI circuit diagram. The layout data is subjected to merge / resize processing, and mask production data is created. The mask production data is data corresponding to a plurality of layers.

  Using the mask manufacturing data, the number of semiconductor manufacturing masks corresponding to a plurality of layers is manufactured. A semiconductor wafer trial manufacture is performed using the mask for semiconductor manufacture. For example, the resist applied on the semiconductor wafer is first exposed and developed using a P-well mask to form a resist opening in the P-well formation region. Then, ion implantation is performed on the resist opening. Subsequently, LOCOS, gates, and the like are formed using the respective masks.

  Thus, a large number of LSIs are formed on the surface of the semiconductor wafer. Then, the LSI is tested and evaluated, and if the result is defective, the cause is analyzed. If a defect in the layout data is found as the cause, the layout data is corrected, and the semiconductor is again processed according to the above flow. Wafer re-production and re-evaluation.

However, if a layout data defect is discovered after the trial production of a semiconductor wafer, the above flow must be repeated, leading to a problem that the delivery date of the LSI is delayed. Therefore, it is important to verify in advance whether the designed layout data is correct. Conventionally, DRC (design rule check) or LVS for verifying whether the layout data is designed according to the circuit diagram. (Logic Vs Schematic) Verification was performed. A method for verifying layout data is described in Patent Document 1.
JP 2005-265497 A

  However, the conventional layout data verification method only determines whether or not all layers for forming a certain device (for example, a transistor) constituting an LSI exist, so that device is formed. If there was a layer that should not be present, it could not be detected. Therefore, when a semiconductor wafer is prototyped with a mask having such a defect, there has been a problem that the LSI becomes defective.

  The present invention has been made in view of the above-described problems, and in the layout data verification method composed of a plurality of layers, the first expression representing all the layers necessary to form a device and Generate a second expression representing all layers that should not be present to form the device, identify the device from the layout data, and for the identified device, It is characterized in that it is determined whether or not all the layers included are present, and whether or not there is a layer included in the second equation.

  According to the present invention, since it is also determined whether or not there is a layer that should not exist in order to form a device, layout data can be verified more reliably. Therefore, LSI defects caused by layout data defects can be reduced, contributing to a reduction in trial production costs and a shortened delivery time.

  Embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows an LSI manufacturing flow. A feature of the present invention is that a program process called MRC process for verifying layout data is added. Hereinafter, description will be given with reference to the flowcharts of FIGS.

  In general, an LSI has various devices (N-channel MOS transistor, P-channel MOS transistor, etc.), and a plurality of devices selected from the various devices are connected to each other to form an LSI circuit. .

  In designing an LSI layout pattern, first, minimum graphic data (in the case of a transistor, a well, a diffusion layer, a gate, etc.) constituting each device is drawn and stored in a computer memory. (Step 10) The graphic data is composed of a plurality of layers to form the device.

  Next, LVS verification is performed based on the rule file 1 stored in the memory of the computer. (Step 11)

  As a result of the LVS verification, if it is determined that there is an error in the graphic data of the device, the subsequent processing is stopped. (Step 12) As a result of the LVS verification, if it is determined that the graphic data of the device is correct, the process proceeds to the next Step 13.

  The shortage of all graphic data constituting the device is generated based on the rule file 2 stored in the memory of the computer. (Step 13) The deficient graphic data is, for example, data of a layer corresponding to the ion implantation mask and can be generated by a logical operation by a computer using the above-mentioned minimum graphic data.

  The rule file 2 stores, as data, rules regarding what kind of logical operation to generate insufficient graphic data for forming a device. Here, the logical operation is a logical operation on the graphic data, and includes addition, multiplication, subtraction, and the like, and new graphic data is generated by the logical operation. For example, if figure A and figure B are added (A + B), a figure simply obtained by adding figure A and figure B is generated. If the figure A and the figure B are multiplied (A × B), the calculation result is a figure in a common area of the figures.

  Then, the deficient graphic data is added to the above-mentioned minimum graphic data, and the mask production final data γ is produced and stored in the memory of the computer. (Step 14)

  Next, an MRC process for verifying the final mask production data γ is performed. (Step 15) This MRC process is a feature of the present invention. FIG. 3 is a flowchart of the MRC process. First, referring to the device-specific layer configuration table, an α formula (an example of the first formula of the present invention) representing all layers necessary for forming a device and a device for forming the device exist. A β expression (an example of the second expression of the present invention) representing all layers that should not be generated is generated. (Step 151)

  An example of the layer configuration table for each device is shown in FIG. This figure shows the layer structure of four types of devices in the triple well process, which are 3.3V N-channel MOS transistors (Nch) and 3.3V P-channel MOS transistors. (Pch) 5V type N-channel MOS transistor (Nch) and 5V type P-channel MOS transistor (Pch).

  4A shows the layer structure of the transistor portion, and B shows the layer structure of the substrate potential fixing region arranged adjacent to the transistor. In this example, there are 16 types of layers, “SW” is a second P well, “F” is an activation region where a device is formed, and a field region around which a thick field oxide film is formed. Yes. “NCA” is a capacitor region, “PE” and “SPE” are channel doped regions, “W” is a first P well, “NW” is an N well, and “FP” is on the first and second P wells. “FN” is an ion implantation region of the field region on the N well, “SLN” is an ion implantation region for forming a low concentration source / drain region of the N-channel high breakdown voltage transistor, and “SLP” is P An ion implantation region for forming a low concentration source / drain region of a channel type high breakdown voltage transistor, “GS” is an etching region of a gate oxide film, “GC” is a gate contact region, “GP” is a gate region, and “LN” is an N channel An ion implantation region for forming a low concentration source / drain region of a MOS transistor, “LP” is a low concentration source / drain region of a P channel MOS transistor. An ion implantation region for forming.

“◯” in FIG. 4 indicates that the layer is necessary, and “X” indicates that the layer should not exist. For example, for a 3.3V N-channel MOS transistor (Nch), all the layers where “F”, “W”, “GS”, “GP”, “LN” are necessary and other layers Layers where “SW”, “NCA”, “PE”, “SPE”, “NW”, “FP”, “FN”, “SLN”, “SLP”, “GC”, “LP” must not exist It is. Accordingly, for the 3.3V N-channel MOS transistor (Nch), the α and β equations are as follows.
α formula = F + W + GS + GP + LN
β = SW + NCA + PE + SPE + NW + FP + FN + SLN + SLP + GC + LP
For the other transistors, α and β equations are similarly created with reference to the device layer configuration table of FIG.

  Next, a rule file 3 for recognizing a device having a correct layer configuration is automatically created by the computer from the device-specific layer configuration table of FIG. (Step 152) The rule file 3 is referred to in the following step 154.

Next, each device is recognized and its physical location is identified. (Step 153)
The physical position of the device is a coordinate position on the LSI. That is, as shown in FIG. 5, the N-channel MOS transistor and the P-channel MOS transistor are identified and their physical position is specified from the LSI layout data (mask production final data γ).

In the next step 154, for each device at the identified physical location,
(1) It is automatically determined whether or not all layers included in the α formula exist.
(2) It is automatically determined whether or not a layer included in the β expression exists.

  The recognition of each device, the identification of its physical position, and the automatic determination in step 154 are executed for all devices existing in the mask production final data γ.

  When it is determined that all the layers included in the α expression exist and no layer included in the β expression exists, it is determined that the layout data of the device is correct. When it is determined that the layout data of all devices is correct, it is verified that the final mask manufacturing data γ is correct, and the process proceeds to the mask manufacturing in the next process (step 16).

  On the other hand, if it is determined that there is a layer that does not exist among the layers included in the α expression, or one or more layers included in the β expression exist, it is determined that the layout data of the device is not correct. In this case, it is determined that there is an error in the rule file 2, and a logical operation expression for generating insufficient graphic data is verified.

  In particular, if it is determined that there is one or more layers included in the β expression, there is a high possibility that the logical operation expression of the rule file 2 has an error. When an error is found in the logical operation expression, the rule file 2 is corrected to recreate the mask production final data γ. Then, the MRC process of step 15 is executed again.

  As described above, according to the present invention, since it is also determined whether or not there is a layer that should not be present in order to form a device, layout data can be verified more reliably. Therefore, LSI defects caused by layout data defects can be reduced, contributing to a reduction in trial production costs and a shortened delivery time.

  Needless to say, the present invention is not limited to the above-described embodiment and can be changed without departing from the scope of the invention. For example, the device-specific layer configuration table in FIG. 4 of the embodiment is an example, and the present invention is a verification of layout data of other devices, for example, all devices such as bipolar transistors and diodes, and LSIs including such devices. Can be applied to.

5 is a flowchart showing a manufacturing flow of an LSI according to an embodiment of the present invention. 5 is a flowchart illustrating verification of layout data according to an embodiment of the present invention. 5 is a flowchart illustrating verification of layout data according to an embodiment of the present invention. It is a layer structure table according to device by embodiment of this invention. It is a figure explaining recognition of each device by the embodiment of the present invention, and specification of its physical position. It is a flowchart which shows the manufacture flow of the conventional LSI.

Claims (4)

In the verification method of layout data composed of multiple layers,
Generate a first expression representing all the layers necessary to form a device and a second expression representing all the layers that should not be present to form the device;
Identify the device from the layout data,
It is determined whether or not all the layers included in the first equation exist for the specified device, and determine whether or not the layer included in the second equation exists. Layout data verification method. When it is determined that all the layers included in the first expression exist and the layer included in the second expression does not exist for the specified device, the layout data of the specified device is determined to be correct. The layout data verification method according to claim 1, wherein: The layout data of the specified device is incorrect when it is determined that the layer included in the first formula is insufficient for the specified device or that one or more layers are included in the second formula The layout data verification method according to claim 1, wherein the layout data is corrected. 4. The layout data verification method according to claim 1, further comprising a step of automatically creating a rule file for recognizing a device having a correct layer configuration based on a device layer configuration table.

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