JPH05151708A - Synchronization protection device - Google Patents

Abstract

PURPOSE:To compensate for synchronization discontinuities caused by random coding errors and burst errors, to prevent pseudo synchronization due to pseudo synchronization patterns and to perform a rapid synchronization restore right after a head switching. CONSTITUTION:A synchronization pattern detecting circuit 12 outputs synchronization pattern detection signals A13 and B14 when signal train, whose all bits match with a true synchronization signal pattern and one bit does not match, are detected in digital input signals 11. Synchronization protecting circuits A15 and B17 decide whether the synchronization pattern detection signals A13 and B14 are outputted at a period in which synchronization to be detected or not and output synchronization signal 18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization protection device applied to a reproducing system of a digital signal recording / reproducing device such as a digital VTR.

[0002]

2. Description of the Related Art In a reproducing system of various digital signal recording / reproducing devices, in order to separate a time-division multiplexed digital signal, synchronization is lost due to a random code error or burst error, or a random data portion other than a synchronization pattern is used. , It is necessary to prevent loss of synchronization due to the occurrence of a pseudo synchronization pattern that is the same pattern as the synchronization pattern, and to restore synchronization immediately if loss of synchronization occurs due to switching of the rotary head. is there.

An example of a synchronization protection device in a reproducing system of a conventional digital signal recording / reproducing device will be described below with reference to the drawings. FIG. 6 is a block diagram of a synchronization protection device that has been adopted in the past. In FIG. 6, reference numeral 61 is an input signal reproduced from a digitally recorded signal, and the normally reproduced input signal has a sync signal pattern N at n-bit intervals as shown in FIG. 62,
Reference numeral 63 is an n-bit delay circuit, which outputs data after n-bit delay and data after 2n-bit delay, respectively. 6
Reference numerals 4, 65 and 66 denote sync pattern detection circuits, and the sync protection circuit 67 determines whether or not the sync pattern is a true sync pattern based on the detection results of these sync pattern detection circuits 64, 65 and 66. Be seen. 68 is an output synchronizing signal as a synchronizing signal.

The operation of the synchronization protection device configured as described above will be described below. First, the sync pattern detection circuit 64 constantly monitors the sync pattern of the input signal 61, and outputs a signal if a pattern in which all bits match the sync pattern is found. n-bit delay circuit 6
Similarly, the data passed through 2 and the data passed through the 2n-bit delay circuit 63 are constantly monitored by the sync pattern detection circuits 65 and 66, and a signal is output if a pattern in which all bits match the sync pattern are found. I do.
In the synchronization protection circuit 67, the synchronization pattern detection circuits 64, 6
Only when signals 5 and 66 are output simultaneously, all the detected synchronization signals are output as true synchronization signals.

Although it depends on the characteristics of the code to be recorded / reproduced, the occurrence of the pseudo sync pattern three consecutive times in the sync pattern period is stochastically equal to 0. Synchronization will be almost solved. Also, the effect of head switching is almost zero.

[0006]

However, in the above configuration, when the true sync pattern signal fails due to a random code error or burst error and the sync pattern cannot be detected, the true sync signal should be obtained. The synchronization signal cannot be obtained, and the continuity of the synchronization signal is impaired, which hinders subsequent signal processing. In order to compensate for the discontinuity of synchronization due to these random code errors and burst errors, if the detection signal of the synchronization detection circuit is output up to 1 bit mismatch or 2 bit mismatch, the continuity is improved. However, the possibility of pseudo synchronization increases.

The present invention solves the above-mentioned problems, and makes it possible to compensate for the discontinuity of the sync signal due to random code errors or burst errors, to prevent the pseudo sync due to the pseudo sync pattern, and to promptly perform even after head switching. It is an object of the present invention to provide a synchronization protection device capable of returning to synchronization with.

[0008]

In order to solve the above-mentioned problems, a synchronization protection device of the present invention is characterized by comparing an input digital signal with a pattern of a predetermined signal sequence indicating a synchronization signal,
A synchronization that detects a signal sequence that is presumed to be a synchronization signal and outputs first and second detection signals with two detection accuracies that differ in the degree of including a signal that matches the signal sequence of the synchronization signal in the signal sequence. A pattern detection circuit and the first detection signal as an input,
Whether or not the first detection signal is output at the interval at which the synchronization signal should be obtained is determined by comparing it with an internal pulse generated at the interval at which the synchronization signal should be obtained, and the loss of synchronization is determined. A first synchronization protection circuit that outputs a pulse when new synchronization is obtained after the first synchronization signal and the first synchronization protection circuit that detects and outputs the synchronization signal with a detection accuracy lower than that of the first detection signal. By inputting two detection signals and comparing whether or not the second detection signal is output at the interval at which the synchronization signal should be obtained, by comparing with the internal pulse generated inside at the interval at which the synchronization signal should be obtained. If it is determined that the synchronization is obtained, the internal pulse is output as a synchronization signal, and the pulse output of the first synchronization protection circuit is input, and the pulse output is input. And a second synchronization protection circuit for outputting in synchronization with the synchronization signal to the pulse output to come.

[0009]

According to the above construction, the first synchronization protection circuit can exclude the pseudo synchronization pattern, and the synchronization can be quickly restored even after the head switching, so that the true synchronization can be quickly obtained. It is possible. In the second synchronization protection circuit, once the synchronization is restored, it is difficult to release the synchronization, and the discontinuity of the synchronization signal due to the random code error or the burst error is always compensated. Even when the next head switching is performed, the second synchronization protection circuit tries to keep the current synchronization, but the first synchronization protection circuit transmits the next true synchronization to the second synchronization protection circuit. In addition, the second sync protection circuit will perform a new true sync.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of a synchronization protection device according to a first embodiment of the present invention. In FIG. 1, 11 is a reproduced digital input signal, 12 is a sync pattern detection circuit, 13 is a detected sync pattern detection signal A, 14 is a detected sync pattern detection signal B,
Reference numeral 15 is a sync protection circuit A, 16 is a sync pulse A of its output, 17 is a sync protection circuit B, and 18 is a final output sync signal.

FIG. 2 is an example of a detailed block diagram of the synchronization protection circuit A15. In FIG. 2, 21 is a synchronization pattern detection signal A, 22 is an internal synchronization pulse generation circuit A, 23 is a synchronization determination circuit A, and 24 is a logic. 25 is the reset signal A of the internal sync pulse generator A22, 26 is the internal sync pulse A, 27 is the out-of-sync signal A, and 28 is the true sync pulse A determined by the sync protection circuit A.

FIG. 3 is an example of a detailed block diagram of the synchronization protection circuit B. 31 is a synchronization pattern detection signal B, 32 is an internal synchronization pulse generation circuit B, 33 is a synchronization determination circuit B, 3
4 is the input of the synchronizing pulse A, 35 is the logical product, 36 is the logical sum, 37 is the reset signal B for generating the internal synchronizing pulse, 38
Is an out-of-sync signal B, 39 is an internal sync pulse B, which is the finally protected output sync signal.

The operation of the synchronization protection device configured as described above will be described below with reference to FIGS. 1, 2 and 3. First, the sync pattern detection circuit 12 of FIG. 1 detects the sync pattern by constantly comparing and collating the input digital reproduction signal with a specific sync pattern determined in advance in a format. A13 and a synchronization pattern detection signal B14 are output as a pulse. The maximum number of bits of the two sync pattern detection signals A13 and B14 that each of the sync patterns is allowed to be inconsistent depends on the respective sync protection circuits A15 and B15.
It matches the characteristics of B16. Here, the synchronization pattern detection signal A13 is output only when all bits match, and the synchronization pattern detection signal B14 is output when up to 1 bit mismatch. Therefore, the synchronization pattern detection signal B14 includes the synchronization pattern detection signal B14. Although it includes more pseudo sync signals than A13, even if the true sync pattern has a 1-bit error, it is output as a sync signal without being ignored.

The sync protection circuit A15 constantly determines whether the input sync pattern detection signal A13 is output at n-bit intervals. The synchronization protection circuit A15 has a characteristic of being easily judged to be out of synchronization and tries to perform new synchronization frequently, and if new synchronization is found as a result, it is output to the synchronization protection circuit B17 as a synchronization pulse A16. That is, the synchronization protection circuit A15 is very effective when prompt new synchronization is required due to head switching or the like.

In the synchronization protection circuit B17, the synchronization protection circuit A1
As in the case of 5, it is constantly determined whether the input synchronization pattern detection signal B14 is output at n-bit intervals. The synchronization protection circuit B17 has a characteristic that it is difficult to determine that the synchronization is lost, and tries to maintain the synchronization state as much as possible once synchronization is achieved. Then, the output synchronizing signal 18 synchronized with the synchronizing pulse A16 is output. That is, the synchronization protection circuit B17 is effective for interpolating the synchronization signal from the characteristic of maintaining the synchronization when the true synchronization pattern cannot be detected due to the random code error or the burst error.

Here, the synchronization protection circuit A15 will be specifically described with reference to FIG. The input sync pattern detection signal A21 is compared in the sync determination circuit A23 with the internal sync pulse A26 output at an n-bit interval at which the sync pattern signal is to be detected, and a sync determination is made.
The synchronization determination circuit A23 has a characteristic that it is easy to determine that it is out of synchronization.

When the result of the synchronization determination by the synchronization determination circuit A23 is regarded as synchronization, the synchronization determination circuit A23 does not output any data. When the result of the synchronization determination is regarded as out-of-synchronization, the out-of-synchronization signal A27 is output and the mask by the logical product 24 is released to input the synchronization pattern detection signal A21 to the internal synchronization pulse generating circuit A22 as the reset signal A25. ,Reset. Then, the synchronization determination is performed again with the new internal synchronization pulse A26 and the synchronization pattern detection signal A21, and if it is determined that new synchronization is obtained, the synchronization pulse A28 is immediately output.

Next, the synchronization protection circuit B will be specifically described with reference to FIG. Input sync pattern detection signal B
In the synchronization determination circuit B33, the synchronization determination 31 is performed by comparison with the output synchronization signal 39 which is an internal synchronization pulse output at n-bit intervals. The synchronization determination circuit A23 has a characteristic that it is difficult to determine that it is out of synchronization.

When the result of the synchronization determination by the synchronization determination circuit B33 is regarded as synchronization, the synchronization determination circuit B33 does not output. If the result of the synchronization determination is regarded as out-of-synchronization, the out-of-synchronization signal B38 is output and the mask by the logical product 35 is released, whereby the synchronization pattern detection signal B
31 to the internal synchronizing pulse generation circuit B32
Enter as 37 and reset. After that, the synchronization determination is continued by the output synchronization signal 39 and the synchronization pattern detection signal B31 which are new internal synchronization pulses. Even if the out-of-sync determination is not made, when the synchronization protection circuit A15 inputs a new synchronization pulse A34, the internal synchronization pulse generation circuit B32 is immediately reset and the synchronization determination is continued by the new synchronization.

As described above, in this embodiment, the sync pattern detection circuit 12 for outputting the specific sync pattern detection signals A13 and B14 detected in accordance with a certain rule from the inputted digital signal sequence, A sync protection circuit A which receives the sync pattern detection signal A13 and has good sync recovery characteristics
15, sync pattern detection signal B14, and sync protection circuit A
A protection circuit B17 having a good sync holding characteristic and having the protection result 16 of 15 as an input is provided. Therefore, in the reproduction system of various digital signal recording / reproducing devices, when separating time-division-multiplexed digital signals, out-of-sync due to random code error or burst error does not easily occur, and due to switching of the rotary head, etc. When the synchronization is lost, the synchronization can be promptly restored.

A second embodiment of the present invention will be described below with reference to the drawings. FIG. 4 is a block diagram of a synchronization protection device according to the second embodiment of the present invention. In FIG. 4, 41
Is the reproduced digital input signal. 42,43
Is an n-bit delay circuit, which outputs n-bit and 2n-bit delay signals 4a and 4b, respectively. 44, 45, 46
Are sync pattern detection circuits, 4c, 4d,
Reference numeral 4e is a detected sync pattern detection signal A, and reference numeral 4f is a sync pattern detection signal B detected by the sync pattern detection circuit 46. 47 is a synchronization protection circuit A
Therefore, the synchronization pattern detection signals A4c, 4d, 4e are input. A sync protection circuit B 48 receives the sync pattern detection signal B. 4g is a sync pulse A output from the sync protection circuit A47 to the sync protection circuit B48, and 49 is a final output sync signal. The synchronization pattern detection circuit 46 and the synchronization protection circuit B48 are the same as those in FIG. The difference from the configuration of FIG. 1 is that extra synchronization pattern detection circuits 44 and 45 are provided.
Addition of n-bit delay circuits 42 and 43, and synchronization protection circuit A
The content of 47 is different.

The operation of the synchronization protection device configured as described above will be described below. First, the n-bit delay circuits 42 and 43 shown in FIG. 4 enable the synchronization pattern to be detected at several locations at the same time when the original synchronization pattern signal is input at n-bit intervals. In this embodiment, 3
Two n-bit delay circuits are provided so that simultaneous detection can be performed at one place. Sync pattern detection circuits 44, 45, 46
Is for constantly comparing and collating the input signal 41, which is a digital reproduction signal, with a specific synchronization pattern determined in advance by a format, and detecting the synchronization pattern. The detection result is the synchronization pattern detection signals A4c, 4d, 4e. , And outputs a pulse as the synchronization pattern detection signal B4f.

The sync pattern detection circuits 44 and 45 do not output the sync pattern detection signal B. The number of bits of the two types of sync pattern detection signals A and B that are allowed to be inconsistent among the total number of bits of the sync pattern depends on the characteristics of the respective sync protection circuits. Here, it is assumed that the synchronization pattern detection signal A is output only when all bits match, and the synchronization pattern detection signal B is output when there is a 1-bit mismatch. Although many pseudo sync signals are included, even if the true sync pattern has one bit error, it is not ignored and is output as a sync signal.

In the sync protection circuit A47, the input sync pattern detection signals A4c, 4d, 4e simultaneously notify the detection to find the position of the true sync pattern, and the sync pulse A4g is output to the sync protection circuit B48. .. In other words, the synchronization protection circuit A47 is very effective when combined with a plurality of synchronization pattern detection circuits, when rapid new synchronization is required due to head switching or the like. Also, depending on the characteristics of the code to be recorded and reproduced,
The probability that the pseudo sync pattern occurs three times consecutively in the sync pattern period is stochastically equal to 0, and this sync protection almost eliminates the pseudo sync due to the pseudo sync pattern. The synchronization protection circuit B48 is the same circuit as that of the first embodiment, and is effective for interpolating the synchronization signal from the characteristic of maintaining the synchronization when the true synchronization pattern cannot be detected due to the random code error or the burst error. Become.

As described above, the conventional sync protection circuit 67 shown in FIG. 6 can be used as the sync protection circuit A47, and digital signals time-division multiplexed in the reproduction system of various digital signal recording / reproducing devices can be used. When separating,
Loss of synchronization due to random code error or burst error is unlikely to occur, and if loss of synchronization occurs due to switching of the rotary head, etc., it is possible to quickly recover synchronization and also due to generation of a pseudo synchronization pattern. Pseudo synchronization can be largely prevented.

Although the sync pattern detection signal A is output only for all bit pattern matches in both embodiments, it may be output for 1 bit mismatch, 2 bit mismatch, etc. depending on the characteristics of the input signal. Sync pattern B
Is also the same. Further, in the second embodiment, two n-bit delay circuits and three synchronization pattern detection circuits are provided, but the number of circuits may be increased or decreased depending on the characteristics of the input signal.

[0027]

As described above, according to the present invention, by providing the sync protection circuit A having a good sync recovery characteristic and the sync protection circuit B having a good sync holding characteristic using the sync signal obtained therefrom, various digital signal recordings can be performed. When separating time-division-multiplexed digital signals in the playback system of the playback device, it is unlikely that out-of-sync or pseudo-sync will occur due to the occurrence of random code errors, burst errors or pseudo sync patterns, and switching of the rotary head. If synchronization is lost due to such reasons, synchronization can be quickly restored.

In the above description, various digital signal recording / reproducing devices have been taken as examples, but the present synchronization protection device can also be applied to digital signal transmitting devices and the like.

[Brief description of drawings]

FIG. 1 is a block diagram of a synchronization protection device according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a synchronization protection circuit A of the device.

FIG. 3 is a block diagram of a synchronization protection circuit B of the device.

FIG. 4 is a block diagram of a synchronization protection device according to a second embodiment of the present invention.

FIG. 5 shows an example of input data reproduced normally in digital signal recording / reproduction.

FIG. 6 is a block diagram of a synchronization protection device in a conventional embodiment.

[Explanation of symbols]

 11 input signal 12 sync pattern detection circuit 15 sync protection circuit A 17 sync protection circuit B 18 output sync signal 21 sync pattern detection signal A 22 internal sync pulse generation circuit A 23 sync determination circuit A 28 sync pulse A output 31 sync pattern detection signal B 32 Internal sync pulse generation circuit B 33 Sync determination circuit B 39 Output sync signal 41 Input signal 44, 45, 46 Sync pattern detection circuit 47 Sync protection circuit A 48 Sync protection circuit B 49 Output sync signal

Claims (2)

[Claims] 1. Comparing an input digital signal with a pattern of a predetermined signal sequence indicating a synchronization signal, synchronization is performed with two detection accuracies having different degrees of including a signal that coincides with the signal sequence of the synchronization signal in the signal sequence. A synchronization pattern detection circuit that detects a signal sequence that is presumed to be a signal and outputs first and second detection signals; and the first detection signal that is input to the first synchronization pattern detection circuit at an interval at which a synchronization signal should be obtained. When a new synchronization is obtained after the loss of synchronization is determined by determining whether the detection signal of is output by comparing it with an internal pulse generated at an interval in which the synchronization signal should be obtained. A first synchronization protection circuit that outputs a pulse to the first detection signal; and a second detection signal that is output when the synchronization signal is detected with a lower detection accuracy than the first detection signal, can get It is determined whether the second detection signal is output at a predetermined interval by comparing it with an internal pulse generated at an interval at which a synchronization signal should be obtained. If synchronization is obtained, The internal pulse is output as a synchronization signal, and the first pulse
Of the synchronization protection circuit as an input, and a second synchronization protection circuit that outputs the synchronization signal in synchronization with the pulse output when the pulse output is input. 2. A means for delaying an input digital signal including a synchronization signal of a predetermined interval by an integer multiple of the interval to create a plurality of input digital signal sequences delayed by an integer multiple of the interval. A plurality of first synchronization signals that compare the plurality of input digital signal sequences with a pattern of a predetermined signal sequence of the synchronization signal, detect a signal sequence estimated to be the synchronization signal, and output first detection signals, respectively. In the comparison between the pattern detection circuit, one of the plurality of input digital signal sequences, and the pattern of the predetermined signal sequence of the synchronization signal, the degree to which the signal sequence includes a signal that matches the signal sequence of the synchronization signal is the first. A second synchronization pattern detection circuit that detects a signal sequence presumed to be a synchronization signal and outputs a second detection signal with a detection accuracy different from that of the first synchronization pattern detection circuit; A plurality of first detection signals output from the first synchronization pattern detection circuit are input, and since they are input simultaneously, synchronization is detected and pulse output is performed.
Of the protection circuit and the second detection signal that is output by detecting the synchronization signal with lower detection accuracy than the first detection signal, and inputs the second detection signal at an interval at which the synchronization signal should be obtained. It is determined by comparing with the internal pulse generated at the interval that the synchronization signal should be obtained inside, and if the synchronization is obtained, the internal pulse is used as the synchronization signal. Output and the first
Of the synchronization protection circuit as an input, and a second synchronization protection circuit that outputs the synchronization signal in synchronization with the pulse output when the pulse output is input.