JPH0313024A - Frame synchronizer for pcm broadcast receiver - Google Patents

Abstract

PURPOSE:To demodulate a voice data normally quickly by providing a mis- synchronization detection circuit using a full coincidence signal to a conventional frame synchronizer, and detecting mis-synchronization to be often caused at the time of changing over between broadcast stations while keeping a synchronization protection characteristic. CONSTITUTION:A pattern detection means 1 switches a threshold level of a coincident bit number with a switching signal, and outputs a full coincidence signal. A malfunction detection means 10 counts an inputted digital signal data by frame synchronization, the count is reset by a full coincidence signal of a pattern detection signal 1' and the means 10 outputs a mis-synchronizing signal when the count reaches N. When the count means 3 counts a dissidence signal and detects the signal by M-times consecutively, an asynchronizing signal is outputted. The mis-synchronizing signal and the asynchronizing signal reset a flip-flop 5 via an OR circuit 11 to cause the asynchronization state, and reset the count means 2, 3 via an OR circuit 4. Thus, synchronization pull-in is attained and normal sound is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a frame synchronization device for preventing erroneous synchronization during frame synchronization in demodulating PCM broadcast signals, and is used for demodulating PCM audio signals of direct satellite broadcasting. can.

Conventional technology low and near There is a movement in many countries around the world to convert audio signals to PCM with the aim of achieving high quality audio broadcasting. Even if the use of the PCM method for audio in audio-only broadcasts is being considered and planned, what about the transmission of such PCM signals? 1. A frame structure consisting of a fixed number of bits is used, and even if a frame synchronization pattern is installed in this frame to determine frame synchronization on the receiver side, the position of this frame synchronization pattern is detected on the receiver side. To do this, pattern matching is performed with the true frame synchronization pattern, and a pattern matching signal is output when all bits match or even some bit errors are tolerated.

If this frame synchronization is not accurate and stable, demodulation of the PCM signal will be completely impossible. Therefore, it is important for a frame synchronizer to (a) prevent erroneous synchronization from occurring at locations other than the synchronization pattern, and (b) maintain synchronization even if there are slight bit errors after synchronization has been achieved. An example of a conventional frame synchronization device will be described below without reference to the drawings. FIG. 3 shows a conventional frame synchronization device (Japanese Patent Application No. 58-200328). In FIG. 3, 1 is a pattern detection means capable of switching the threshold value of the number of matching bits by a switching signal, and outputs a matching signal and a mismatching signal. 2.
3 is a counting means, which measures the coincidence signal of consecutive times or consecutive M
In response to the mismatch signal, output signals are output, respectively, to set and reset the flip-flop 5, and to reset both counting means 2.3 via the FOR circuit 4. When the synchronous state output of the flip-flop 5 is at a low level, that is, when it is in an asynchronous state, the threshold value of the pattern detection means 1 is set to A1.
, when the output of the flip-flop 5 is at a high level, that is, in a synchronous state, the threshold value of the pattern detection means 1 is set to A.
This is a switching signal for switching to 2. Usually it is set to A+≧A2. FIG. 4 Table c is a block diagram showing an example of the internal configuration of the pattern detection means 1. The frame synchronization pattern of the input digital signal is read into a shift register 6 having the same number of stages as the code length of the synchronization pattern. shift register 6
The outputs of are taken out in parallel and input to the pattern matching circuit 7. The pattern matching circuit 7 detects the number of matching bits with the true frame synchronization pattern and has two outputs indicating whether the value is greater than or equal to A1 or the resultant value and whether it is greater than or equal to A2. Next, in the selection circuit 8, when the switching signal is at a low level, a signal indicating whether the resultant force is greater than or equal to A1 is selected, and when the switching signal is at a high level, a signal indicating whether or not the resultant force is greater than or equal to A2 is selected and outputted as a match signal. The mismatch signal can be obtained by inverting the match signal using the inversion circuit 9. However, by being able to set the threshold for the number of match bits independently depending on the synchronous state and the asynchronous state, it is extremely resistant to bit errors. It realizes a frame synchronization device.

Problems to be Solved by the Invention In such a conventional example, when the frame synchronization pattern synchronizer is in a synchronized state, the threshold value for detecting the number of matching bits is A2. If X, then even if the frame synchronization pattern contains an error of (X-A2) bits or less, the synchronization will not be lost. Therefore, when switching between broadcast stations, the frame synchronization pattern (X
-A2) If digital signal data having a difference of less than a bit exists periodically at frame intervals, a state in which normal audio data is not demodulated continues. In view of the above problems, it is an object of the present invention to provide a frame synchronization device that prevents false synchronization while maintaining strong frame synchronization protection.

Means for Solving the Problems In order to solve the above problems, the frame synchronization device of the present invention (1)
This device has a configuration that outputs an erroneous synchronization signal when the synchronization signal is not input twice.

If the complete coincidence signal from the action pattern detection means is not manually input N times in succession, the synchronization state is canceled. Therefore, when switching between broadcast stations, digital signal data with a frame synchronization pattern and a small Hamming distance may periodically exist at the current synchronization timing position of the broadcast station after switching between broadcast stations.
Since no all-match signal is input, cancel the synchronization state and search for a frame synchronization pattern again in the asynchronous state.Return to a state where audio data can be demodulated normally.

EXAMPLE An example of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, and 1' in the figure is a pattern detection method 10 in which the threshold value of the number of matching bits can be switched by a switching signal and a total matching signal is output. The erroneous synchronization detection circuit 3 resets the counting by the frame synchronization of the input digital signal data and resets the counting by the all match signal of the pattern detection signal 1' and outputs an erroneous synchronization signal when the counted value reaches N. It is a counting means that outputs an asynchronous signal when detected M times in a row, and the erroneous synchronization signal and the asynchronous signal pass through an OR circuit 11, reset the flip-flop 5 to an asynchronous state, and pass through an OR circuit 4 to the counting means 2.3. Reset.

FIG. 2 is a block diagram showing an example of the internal configuration of the erroneous synchronization detection circuit 10, in which 12 is a counter that counts up to a count value N, and the count value is reset each time a complete match signal is input. On the other hand, 13 is a frame cycle generation circuit that generates a clock synchronized with the frame cycle of the input digital signal.
The generated clock becomes the clock input of the counter. Therefore, if the complete coincidence signal is not manually input, the counter performs a counting operation at the frame period, and when the count value reaches N, outputs an erroneous synchronization signal. Blocks with the same number and name in Fig. 1@ Fig. 3 indicate the same parts. The operation and characteristics of the frame synchronizer configured as described above will be explained using current satellite broadcasting as an example. The number of bits given as the frame synchronization pattern for the PCM audio of the above broadcast is 16 bits. In the case of Figure 3, 1, A+ = 16. L
-3, A2-12. By setting it to M-5, it is possible to obtain synchronization protection characteristics that pose no practical problems. Therefore, in order not to damage the original synchronization protection characteristics, ζ is set to the service limit (
The probability that synchronization will be canceled by countermeasures against false synchronization up to input error rate P = 10-2) needs to be sufficiently smaller than the probability of cancellation due to synchronization protection. Therefore, the strength of synchronization protection is A = (+aC4)・P'(1-P)'2]'Saki1.05x
10-*a In other words, when P=10-2 and the Hamming distance with the frame synchronization pattern is 4 or more five times in a row, the probability of erroneously outputting an asynchronous detection signal is A. - Thick The strength of false synchronization detection is B = (1-(1-P) + s l'→0.1485"P-10"), and if there are no complete matches N times in a row, the false synchronization detection signal is erroneously detected. The probability of output is B. Therefore, in order to maintain the strength of synchronization protection and prevent false synchronization, BA is required.
Must be A. Temporary c:=P-10-'', N≧29, and considering the simplicity of the circuit, it would be good to set it to N-32~ In this case, after switching between broadcast stations, the false synchronization detection circuit moves one time and the synchronization is released. The synchronization pull-in operation is performed again and normal sound is output.As in the case above, iQ
When A + -16, a signal of ≧A1 can also be used as the all-match signal.

Effects of the Invention As described above, the present invention provides a false synchronization detection circuit that uses an all-coincidence signal in a conventional frame synchronizer, thereby preventing false synchronization that tends to occur when switching between broadcasting stations while maintaining synchronization protection characteristics. It can be detected and quickly restored to normal demodulation.However, it can be realized with a very simple circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a frame synchronizer according to an embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of the pattern detection means of FIG. 1. FIG. 3 is a block diagram of a conventional frame synchronizer. FIG. 4 is a block diagram showing the configuration of the pattern detection means shown in FIG. 3; 1.1'... Pattern detection method 2.3... Counting method 5... Flip-flop, 6... Shift register 9... False synchronization detection circuit 12... Hisashi Karan 13...Frame cycle generation circuit

Claims (1)

[Claims] A frame synchronization device for a PCM broadcast receiver that receives a digital signal transmitted having a frame structure including a frame synchronization pattern consisting of a plurality of bits, which detects the frame synchronization pattern by comparing it with a true frame synchronization pattern. pattern detection means that outputs a mismatch signal when the number of matching bits is less than a threshold value and outputs a full match signal when a complete match is made; and a pattern detection means that outputs a first asynchronous signal when the mismatch signal is detected M times in a row. 1 asynchronous detection circuit;
If the above all-match signal is not input N times consecutively, the second
a second asynchronous detection circuit that outputs an asynchronous signal;
A frame synchronization device for a PCM broadcast receiver, characterized in that a synchronization state is canceled by the first asynchronous signal and the second asynchronous signal.