JPH04309030A - Frame synchronizing equipment - Google Patents

Abstract

PURPOSE:To realize the frame synchronizing equipment having a strong synchronization protection characteristic and eliminating mis-synchronization quickly with high reliability. CONSTITUTION:Since the equipment is provided with a pattern detection means 10 collating a pattern of a reception signal and a specific frame synchronization pattern whose dissidence discrimination threshold level is varied, and a control code detection means 11 detecting a voice suppression bit included in the reception signal and outputting a signal to select the dissidence discrimination threshold level for the pattern detection means 10 depending on the content of the bit, the frame synchronization equipment having strong synchronization protection characteristic and releasing quickly mis-synchronization is realized.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization device for improving the reliability of synchronization in a PCM broadcast receiver, and can be used for demodulating PCM audio signals of direct satellite broadcasting.

0002

2. Description of the Related Art In recent years, there has been a movement in various countries around the world to convert audio signals to PCM with the aim of achieving high quality audio. In Japan, PCM conversion of audio signals for television broadcasts using broadcasting satellites or communication satellites has already been implemented. By the way, in the transmission of such a PCM signal,
A frame structure in which a fixed number of bits is used as a unit is used, and a frame synchronization signal indicating a frame synchronization position is provided. On the receiver side, in order to detect the frame synchronization bit position and correctly achieve frame synchronization, the receiver side performs pattern matching between the unique frame synchronization pattern and the received signal, and pulls in and releases synchronization. Control. Pattern matching is judged based on whether the number of matching bits is less than a threshold value. If the number of matching bits is more than the threshold value, it is determined that there is a match and the synchronization pull-in process begins. If it is less than the threshold value, it is determined that there is no match. It is determined that the synchronization is canceled. Demodulation of the PCM signal is impossible unless frame synchronization is accurate and stable. Therefore, the following points are important in a frame synchronizer. Normal synchronization pattern
Synchronization is established only at the input position, and synchronization does not occur at other locations (high reliability). Furthermore, once synchronization is achieved, synchronization will not be canceled even if there is a slight bit error due to disturbance, etc.
strong synchronization protection).

An example of a conventional frame synchronization device will be described below with reference to the drawings. Figure 3 shows the conventional framework.
This figure shows a system synchronizer (Japanese Patent Application No. 1-147862). 20 is a pattern that outputs a match signal when all bits of the unique frame synchronization pattern and the frame synchronization signal of the received signal match, and outputs a mismatch signal when they do not match.
This is a means for detecting 21 counts the number of frames of the received signal, and outputs an erroneous synchronization detection signal when the counted value exceeds N;
This is an erroneous synchronization detecting means that resets the count value by a coincidence signal from the pattern detecting means 20. 22 counts coincidence signals and outputs a synchronization signal when detected L times in succession. 23 is a counting means that counts the mismatched signals and outputs an asynchronous signal when detected M times consecutively. The above-mentioned false synchronization detection signal and synchronization release signal reset the flip-flop 24 to an asynchronous state via the OR circuit 26 and reset the counting means 22 and 23 via the OR circuit 25.

FIG. 4 shows an example of the internal configuration of the erroneous synchronization detection means 21. A counter 27 counts up to a count value N, and resets the count value when the pattern detection means 20 outputs a matching signal. On the other hand, reference numeral 28 denotes a clock generating means for generating a frame clock which is synchronized with the frame of the received signal and has the same period, and this frame clock becomes the clock input of the counter. Therefore, if there is no matching signal,
The counter performs counting operation in frame period and the count value is N.
When this occurs, a false synchronization detection signal is output.

The operation and characteristics of the conventional frame synchronization device configured as described above will be explained using current satellite broadcasting as an example. The number of bits of the frame synchronization signal of PCM audio of satellite broadcasting is 16 bits. In the conventional example, the match judgment threshold is {16/16}, and the mismatch judgment threshold is {
12 or less/16}, L=3, and M=5.

Here, it is assumed that the frame synchronizer is out of synchronization. When the unique frame synchronization pattern and the frame synchronization signal of the received signal match in all bits, the pattern detection means 20 outputs a match signal. When the coincidence signal is inputted L (=3) times in succession, the counting means 22 outputs a synchronizing signal and sets the flip-flop circuit 24. At this time, the flip-flop circuit 24 outputs a synchronization detection signal, indicating that the frame synchronizer has established synchronization. Further, the synchronization signal which is the output of the counting means 22 is output from the OR circuit 2.
5, the counting means 23 (22) is reset and the generation state of the mismatch signal is monitored (this state is called a synchronization protection state). In this synchronization protection state, the mismatch judgment threshold is set to {
12 or less/16}, and the number of mismatch bits between the unique frame synchronization pattern and the frame synchronization signal of the received signal is 4 or more (threshold value {12 or less/16}). After K (=5) times, the counting means 23 outputs an asynchronous signal to reset the flip-flop circuit 24 and release the synchronization. This asynchronous signal resets the counting means 22 (23) via the OR circuit 25 and monitors the coincidence signal (this state is called a synchronization pull-in state).

In the erroneous synchronization state, the erroneous synchronization detection means 21
The probability that the counter 27 counts the clock of the clock generating means 28 and exceeds N and outputs an erroneous synchronization detection signal is:
The pattern detection means 20 outputs a complete match signal and the counter 2
This is considered to be much higher than the probability of resetting 7. (Inherent frame synchronization pattern and received signal frame
The pattern detection means 2 does not match all bits with the system synchronization signal.
0 does not output an all match signal. The counter 27 performs a counting operation using the clock of the clock generating means 28, and when the count value reaches N, it outputs an erroneous synchronization detection signal, resets the counting means 22 (23) via the OR circuits 26 and 25, releases the synchronization, and pulls in the synchronization. state.

In a normal synchronization state, the pattern detection means 2
0 outputs an all-match signal and resets the counter, and the counter 27 in the erroneous synchronization detection means 21 counts the clocks of the clock generation means 28 and exceeds N and outputs an erroneous synchronization detection signal. N is set so that the probability that the synchronization will be canceled due to the synchronization is negligible.

Therefore, in order to add a function to prevent false synchronization without impairing the original synchronization protection characteristics, the probability that synchronization will be canceled due to the operation of synchronization protection is P1, and the probability that synchronization will be canceled due to the operation of the false synchronization detection means is set as P1. If the probability is P2,

0
010]

[Math 1]

It must be [0011]. Here, if the bit error rate at the limit of broadcasting service is r=10-2, the following equation holds true.

0012

[Math 2]

[0013] However, the synchronization can be canceled using the above-mentioned {12 or less/1
6} is assumed to be dominant.

On the other hand, the probability of false synchronization detection is expressed by the following equation.

[0015]

[Math 3]

Therefore, the count value N of the counter for canceling erroneous synchronization is

[0017]

[Math 4]

In consideration of the simplicity of circuit implementation, N=32 is set in the conventional frame synchronizer.

As described above, the conventional configuration achieves strong synchronization protection characteristics by reducing the mismatch judgment threshold for synchronization patterns (ignoring mismatch bits of 3 or less); This was an attempt to eliminate false synchronization, which is a problem caused by making the size smaller, by using false synchronization detection means.

[0020]

[Problem to be Solved by the Invention] However, in the above-mentioned conventional configuration, once the erroneous synchronization condition occurs, the N frame
If the error synchronization continues, the error synchronization state will be detected and the error synchronization will be canceled. The shortest period to resynchronize is N+M
(=37) frames are required. If N is made small in an attempt to speed up the cancellation of the erroneous synchronization state, the probability that normal synchronization will be canceled due to malfunction of the erroneous synchronization detection means increases, and the originally strong synchronization protection characteristics will be impaired.

[0021] In order to maintain strong synchronization protection characteristics, N=32
It is not possible to shorten the time required to release the erroneous synchronization.

Therefore, the problem remains how to maintain strong synchronization protection characteristics and shorten the period of erroneous synchronization release.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a frame synchronization device that maintains strong synchronization protection characteristics and quickly releases erroneous synchronization.

[0024]

[Means for Solving the Problems] In order to achieve this object, the frame synchronization device of the present invention has a frame synchronization device that detects when all bits of a unique frame synchronization pattern and a frame synchronization signal of a received signal match. A pattern detection means that outputs a coincidence signal, outputs a mismatch signal in case of mismatch, and can switch the threshold for determining mismatch, and outputs a synchronization signal when a coincidence signal is input L times in a row. a counting means, a counting means that outputs a synchronization release signal when a mismatch signal is inputted M times in succession, a synchronization signal is connected to a set input, a synchronization release signal is connected to a reset input, and a synchronization detection signal is output by inputting the synchronization signal. The control code detecting means detects specific information contained in the received signal and outputs a signal for switching the mismatch determination threshold of the pattern detecting means depending on the content of the specific information.

[0025]

[Operation] The operation of the structure of the present invention will be explained below. When erroneous synchronization occurs, it occurs when the source station is switched, and when the source station is switched, information for suppressing the voice (this is called the voice suppression bit, and determines whether to suppress or not suppress the voice) is always sent. Although strong synchronization protection characteristics are normally required, they are not required when switching stations.

Here, it is assumed that the synchronization device of the present invention is in a synchronization protection state, and that a source station switching has occurred. At this time, the audio suppression signal is detected, and the mismatch determination threshold of the pattern detection means is switched to a state where synchronization is likely to be lost, thereby weakening the synchronization protection. Erroneous synchronization can be canceled by weakening the synchronization protection, and its duration becomes M (=5) frames. Compared to N+M (=37) in the conventional example, the time can be reduced to about 1/7. Furthermore, when the voice suppression signal is not received, the mismatch determination threshold is set to a normal value and synchronization protection is strengthened. This makes it possible to quickly release erroneous synchronization while maintaining strong synchronization protection characteristics.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a detailed block diagram of the pattern detection means 10. 10 is a pattern detection means that outputs a coincidence signal when all bits of the frame synchronization pattern and the received signal match, outputs a mismatch signal when they do not match, and can switch the threshold value for determining mismatch. It is. Reference numeral 12 denotes a counting means for counting coincidence signals and outputting a synchronizing signal when detected L times consecutively. 13 is a counting means that outputs an asynchronous signal if the mismatch signal is counted M times in succession. The synchronous signal and the asynchronous signal are passed through an OR circuit 15 to the counting means 12 and 1.
Reset 3. 14 is a set/reset type flip-flop circuit which is set by a synchronization signal, reset by a synchronization release signal, and outputs a synchronization detection signal. Reference numeral 11 denotes a control code detection means that detects the voice suppression bit of the control code included in the received signal and uses the detection result to output a signal for switching the mismatch determination threshold of the pattern detection means 10.

FIG. 2 is a detailed block diagram of the pattern detection means 10. 16 is a shift register that converts a serial input signal into a parallel signal. 17 is a unique frame
This is a pattern matching means that performs bit matching between the system synchronization pattern and the received synchronization signal. 18 is a mismatch signal {12
Select either the mismatch signal 2 of {15 or less/16} or the mismatch signal 1 of {15 or less/16}. Selection of this mismatch signal is performed using a threshold switching signal which is an output of the control code detection means 11.

The operation and characteristics of the frame synchronization apparatus constructed as described above will be explained by taking as an example the satellite broadcasting currently being carried out.

Matching judgment threshold: {16/16
}Disagreement judgment threshold: {12 or less/16}
Audio suppression bit = 0 or {15 or less/16} Audio suppression bit = 1 {
n/m}: The threshold condition is the case where n bits out of m bits match.

m: Number of bits of frame synchronization pattern n:
Number of matching bits If L = 3 and M = 5, synchronization pull-in: {16/16} is 3 or more times in a row Synchronization protection: When audio suppression bit = 0, {12 or less/
16} occurs five or more times in a row.When the audio suppression bit=1, {15 or less/16} occurs five times or more in a row.

At this point, the frame synchronizer loses synchronization and enters a synchronization pull-in state. The received signal is transferred to the shift register 16
input signal, which is converted to a parallel signal. This parallel signal is input to the pattern matching means 17, which compares the bits of the input signal and the unique frame synchronization pattern, and outputs three types of signals depending on the number of matching bits. do. If all bits match, {16/
16} match signal, if the number of matching bits is 15 or less, {
15 or less/16} mismatch signal 1, number of matching bits is 12
If it is less than or equal to {12 or less/16}, a mismatch signal 2 is output. Assuming that the unique frame synchronization pattern and the frame synchronization signal of the received signal match in all bits, the match signal is input to the counting means 12 at the next stage. When the coincidence signal is continuously input to the counting means 12 L (=3) times, a synchronizing signal is output, and 14 flip-flops are set. At this time, the frame synchronizer establishes synchronization and enters the synchronization protection state.

In the synchronization protection state, when the control code detection means 11 detects the voice suppression bit = 0 without switching the originating station, the switching circuit 18 selects {12 or less/16} as the mismatch judgment threshold and makes it strong. This provides proper synchronization protection to prevent accidental release of synchronization due to noise, etc. In this synchronization protection state, if a signal satisfying {12 or less/16} is received K (=5) times in a row, an asynchronous signal is output from the counting means 13 to reset the flip-flop circuit 14 and release the synchronization.

In the synchronization protection state, when the control code detection means 11 detects the voice suppression bit=1, the mismatch determination threshold is selected as {15 or less/16}, and the synchronization pattern
The number of matching bits between the received signal and the frame synchronization signal is 1.
If a signal satisfying 5 bits or less is received K (=5) times in succession, the synchronization is canceled. Therefore, even if erroneous synchronization occurs, it can be released, and the period required for release is K (=5) frames.

As described above, the pattern detecting means 10 performs pattern matching between the unique frame synchronization pattern and the received signal, and switches the match/mismatch judgment threshold, and the By providing a control code detection means 11 that detects the suppression bit and outputs a signal for switching the mismatch determination threshold of the pattern detection means depending on the content of the suppression bit,
It is possible to realize a frame synchronization device that maintains strong synchronization protection characteristics and quickly releases erroneous synchronization.

[0036]

As described above, the present invention provides a pattern detection means for switching the match/mismatch determination threshold, and a control code detection means for outputting a switching signal for the mismatch determination threshold of the pattern detection means. By providing this, when the control code detection means detects the voice suppression bit = 1 (voice suppression bit = 1 if false synchronization occurs), the mismatch judgment threshold is switched to weaken the synchronization protection to prevent false synchronization. When the voice suppression bit = 0, the mismatch determination threshold is switched to maintain strong synchronization protection. This makes it possible to realize an excellent frame synchronization device having strong synchronization protection characteristics and a function for quickly canceling erroneous synchronization.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a frame synchronizer according to an embodiment of the present invention.

FIG. 2 is a detailed diagram of a pattern detection means according to an embodiment of the present invention.

FIG. 3 is a block diagram of a conventional erroneous synchronization detection means.

FIG. 4 is a detailed diagram of a conventional synchronization pattern detection means.

[Explanation of symbols]

10 Pattern detection means 11 Control code detection means 12 Counting means 13 Counting means 14 Flip-flop circuit 15 OR circuit 16 Shift register 17 Pattern matching means 18 Switching circuit 20 Pattern detection means 21 Erroneous synchronization detection means 22 Counting means 23 Counting means 24 Flip-flop circuit 25 OR circuit 26 OR circuit 27 Counter circuit 28 Clock generation means

Claims (1)

[Claims] Claim 1: When all bits of the unique frame synchronization pattern and the frame synchronization signal of the received signal match, a match signal is output, and when they do not match, a mismatch signal is output and a mismatch is determined. a pattern detection means that can switch the threshold;
A counting means that outputs a synchronization signal when a coincidence signal is inputted L times in a row, a counting means that outputs a synchronization release signal when a mismatch signal is inputted M times in a row, and a synchronization signal is set and synchronized. A flip-flop circuit that connects a release signal to a reset input and outputs a synchronization detection signal when a synchronization signal is input, and a flip-flop circuit that detects specific information (control code) included in the received signal and detects the above pattern based on its contents. control code detection means for outputting a signal for switching the mismatch determination threshold of the means, and when the frame synchronization device detects specific information included in the received signal in a synchronization protection state, the pattern detection means 1. A frame synchronization device characterized by switching a non-coincidence determination threshold of a means.