JPH06119722A - Device and method for pcm signal reproduction - Google Patents

Abstract

PURPOSE:To prevent the generation of erroneous correction by providing a prohibition circuit for forcibly rewriting the decoded result of detected code to an erroneous state when the detecting condition of a block address does not hold. CONSTITUTION:Data written in a memory 9 and the result of a CRC check are sent to an error correction circuit 10, the error is detected and corrected and these are again written in the memory 9. The error correction is executed by means of a P parity in which the checked result of the CRC check is used as a flag and then executed by means of a Q parity check as a flag whether the correction by the P parity is performed. In this case, when the signal of a 8mm VTR-PCM is reproduced, a detection/protection circuit 6 for block address executes the interpolation because of the failure of detection, the erroneous correction does not occur since the result of the CRC check is forced to be an erroneous state even when an n-th block signal is inadvertently treated as an m-th signal and an abnormal sound does not occurs in the reproduced sound.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PCM signal reproducing device and a PCM signal reproducing method.

[0002]

2. Description of the Related Art In the prior art, when an address signal is detected from a reproduction signal as described in Japanese Patent Laid-Open No. 183059, a continuous number is added to the allocated block address signal and ID signal during recording. The detection protection is performed by checking the generated parity code and checking whether two block addresses reproduced from the following two blocks are continuous. Further, as in the 8 mm VTR-PCM format, the block address detection condition is set for the block address signal to which the above-mentioned parity code is absent and a continuous number is allocated and the signal having the error detection code for the signal of one block as a whole. 3 consecutive block addresses reproduced from the following 3 blocks, or 2 consecutive block addresses reproduced from the following 2 blocks, and the previous block address of the consecutive block addresses Is determined to be error-free by the error detection code of the detected block. For example, the protection is performed by a combination of the continuous condition of the detected block address and the decoding result of the error detection code for the signal of the entire block. It was

[0003]

In the above conventional technique, there is a case where the correct block address is not detected even if the error detection code of a certain n-th block has no error. That is, although the data of the nth block is erroneously processed as the data of the mth block, that is, the data of the nth block is erroneous, the error detection code is decoded. The result is no error. Therefore, even if error correction is performed based on the decoding result of the error detection code, erroneous correction will occur.

An object of the present invention is to prevent erroneous correction even if the data of the nth block is erroneously processed as the data of the mth block.

[0005]

In order to achieve the above object, it is achieved by providing a decoding result prohibition circuit for forcibly rewriting the error detection code decoding result to the error state when the block address detection condition is not satisfied. To be done.

[0006]

According to the present invention, when the block address is detected from the data of the nth block, the detection condition is not satisfied, and the block address detection protection circuit detects the error even if the block address is m. The code decoding result mask flag is set when the block address detection condition is not satisfied, and the decoding result gate circuit rewrites the decoding result of the nth block into an error state according to the error detection code decoding result mask flag. Therefore, the erroneous data processed as the m-th signal is added with the decoding result of the error state (actually, the data of the n-th block), and erroneous correction does not occur.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram of a PCM reproducing apparatus according to the present invention, and FIG. 2 is an 8 mm VTR (NT) generated at the time of recording.
FIG. 3 is a flow chart showing the operation of the present invention. FIG. 3 is a recording signal format showing the configuration of the data signal of (SC). In the following, the embodiments are intended for signals according to the format of FIG. In FIG. 2, reference numeral 201 is a recording tape, and 202 is a rotary head contacting the tape 22.
This is a signal of one track recorded for 1 °. Only the PCM area of the signal of one track is shown in detail in FIG. 2b. The PCM area includes a margin area of 5 ° including a clock area in which a shortest wavelength signal of 2.06 ° is recorded, a data area of 26.32 ° in which data is recorded, a clock area of 2.06 °, It consists of a total of 36 ° of 2.62 ° guard bands for separation from the video signal. The data area consists of 132 blocks.
The structure of one block is shown in FIG. 2c. One block is a SYNC-CODE indicating the beginning of the block, a block address which is a continuous number given to each block and gives an independent address (the numbers 0 to 131 are assigned), W0 to W7. 8 word (8 bit = 1 word) PCM data, P and Q 2 word error correction code added to the PCM code, and error detection code (CRC) added to all data of one block except SYNC. Code). Next, an example of reproducing the recorded signal according to this configuration will be described. In FIG. 1, 1 is a rotary cylinder to which a magnetic head is attached, 2 is a magnetic tape, 3 is a reproducing amplifier, and 16 is a servo circuit for controlling a rotating system, a tape running system and the like. The reproduction signal read from the magnetic tape is detected by the synchronization circuit 5 and protected when the synchronization signal is lost, and the reproduction signal is synchronized with the PCM signal reproducing device at the determined synchronization timing and demodulated by the demodulation circuit 4. It The synchronizing circuit 5 simultaneously generates a timing signal having a cycle equal to the time when one block of data is reproduced from the magnetic tape. The demodulated data is sent to the CRC decoding circuit 7 and the block address detection protection circuit 6. CRC decoding circuit 7
Then, the availability of data is checked from the CRC code added at the time of recording, and the result is sent to the CRC gate circuit 8 and the block address detection protection circuit 6. In the block address detection protection circuit 6, the reproduced block addresses sent from the demodulation circuit 4 are n, n + 1 and 2 consecutive, and
If the CRC check result of the nth block among the CRC check results sent from the CRC decoding circuit 7 is not in the error state, the block address is detected (FIG. 3-3).
02) If it cannot be detected, one block address is added in synchronization with the block cycle timing signal from the synchronizing circuit 5 to generate an interpolated protected block address (hereinafter referred to as a protected address). The protected address is sent to the address control circuit 14. Further, the block address detection protection circuit 6 sends to the CRC gate circuit 8 a flag signal which becomes 0 (FIG. 3-303) if it can detect the block address at the same time, and 1 (FIG. 3-304) if it cannot detect the block address. In the CRC gate circuit 8, the CRC mask flag is 1
If it is, the CRC check result is forcibly rewritten to the error state (FIG. 3-306). The operation of forced rewriting by the CRC gate circuit 8 can be stopped by the system controller 15. That is, the operation of the CRC gate circuit 8 can be limited only when the reproduction state is bad, such as during special reproduction. The protected address is sent to the address control circuit 14. An address to be written in the memory is generated here, and the data from the demodulation circuit 4 and the CRC are generated.
The CRC check result from the gate circuit 8 is written in the memory 9. The data written in the memory 9 and the CRC check result are sent to the error correction circuit 10 to detect and correct the error, and then written in the memory 9 again. In this error correction, the CRC check result is used as a flag to perform correction with P parity, and then the Q parity is used as a flag indicating whether correction with P parity has been performed. The flag used in the description of this error correction indicates which data is erroneous when the correction is performed, and corrects the indicated data by parity. The data written in the memory 9 again is sent to the interpolation circuit 11 and interpolated, and then converted into an analog signal by the D / A converter 12 and output.

As described above, according to this embodiment, the 8 mm VTR-P is used.
When the CM signal is reproduced, the block address detection protection circuit 6 does not detect it and performs interpolation, and even if the signal of the nth block is mistakenly treated as the mth signal, the CRC check result is forced to be in an error state. Therefore, no erroneous correction occurs and no abnormal noise occurs in the reproduced sound. That is, it is possible to prevent the occurrence of abnormal noise even in the special reproduction, in which the error is likely to occur continuously in the signal at the beginning of one track.

The above embodiment will be described in more detail with reference to FIG. FIG. 4 is a timing chart showing the concept of the operation of the present invention. Reference numeral 401 is a timing at which the reproduced data is input to the demodulation circuit 4, and 402 is a timing at which the protection block address changes. 403 is a change timing of the CRC mask flag. Reference numeral 404 indicates a CRC check result output from the CRC gate circuit 8 to the memory 9. Here, the conditions for block address detection are the same as those in the above-described embodiment, that is, the block addresses sent from the demodulation circuit 4 are two consecutive,
The result of the CRC check of the preceding block is O
If K, it is assumed that the block address is the protected address. First, at the protection address change timing B point, the CRC check result of the (n-1) th block is impossible, so the block address is incremented to m. At this time, the CRC mask flag is set at the same time. (403) As a result, the CR of the nth block
The output of the C gate circuit 8 can be rewritten to be impossible. This n
Data from the second block and CR from the CRC gate circuit
The C check result is subsequently processed as the data of the mth block. At the next protection address change timing C point, the block addresses are continuous with n and n + 1, and the CRC check result of the nth block is OK.
The block address detection condition is satisfied, the protection block address is set to n, and the CRC mask flag is reset. CRC mask flag has been reset n +
The CRC check result for the first block is OK
Is output from the CRC gate circuit 8. Thus
When the block address is interpolated, the CRC check result is forcibly rewritten to the error state.

[0010]

Even if the block address is erroneously processed by the block address internal processing, the error detection result of the corresponding block is forcibly rewritten to the error state, thereby preventing erroneous correction, and thus the PCM having high data reliability. A signal reproducing device can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram of a PCM playback device according to the present invention.

FIG. 2 is a diagram showing a recording signal format showing a configuration of an 8 mm VTR data signal.

FIG. 3 is a flowchart showing the operation of the present invention.

FIG. 4 is a timing chart showing the operation timing of the present invention.

[Explanation of symbols]

4 ... Demodulation circuit, 5 ... Synchronization circuit, 6 ... Block address detection protection circuit, 7 ... CRC decoding circuit, 8 ... CRC gate circuit, 14 ... Address control circuit, 201 ... Recording tape, 2
02 ... 1 track signal to be recorded.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuhiro Togaku 1410 Inada, Katsuta City, Ibaraki Prefecture Hitachi Ltd. AV Equipment Division

Claims (6)

[Claims] 1. Data is divided into blocks, and
For each block, a block synchronization signal added to the beginning of the block, a block address code added as a continuous number, and an error detection code added to the data of the block excluding the block synchronization signal, or
In a PCM signal reproducing apparatus for reproducing a recording medium having an error correction code and recorded in a unit of a plurality of blocks, a block synchronizing circuit for detecting the block synchronizing signal, and reproduced data is stored based on a detection output of the block synchronizing circuit. Temporary storage means, error detection means for judging an error by the error detection code or error correction code, block for judging that n block addresses have been continuously detected from n consecutive (n: integer) blocks of a reproduced signal. The address continuity determination means, the block address detection protection means for determining the address value of the temporary storage means by the detected block address based on the results of the error detection means and the block address continuity determination means, and the block address detection protection means block If the address is not detected, the error detection PCM characterized by comprising gate means for forcibly bringing the detection result of the stage into an error state.
Signal reproduction device. 2. The data is divided into blocks and
For each block, a block synchronization signal added to the beginning of the block, a block address code added as a continuous number, and an error detection code added to the data of the block excluding the block synchronization signal, or
In a PCM signal reproducing device for reproducing a recording medium having an error correction code and recorded in a unit of a plurality of blocks, the block synchronization signal is detected, and reproduction data is stored in a temporary storage means on the basis of the detected block synchronization signal. An error is determined by the error detection code or the error correction code, and it is determined that n consecutive block addresses have been detected from n consecutive (n: integer) blocks of the reproduction signal and the error detection result. According to the result, the address value of the temporary storage means is determined as the detection block address, and when the block address detection protection means does not detect the block address, the detection result of the error detection means is forcibly set to the error state. PC characterized by
M signal reproduction method. 3. The PCM signal reproducing apparatus according to claim 1, further comprising system control means for stopping the operation of the gate means. 4. The PCM signal reproducing apparatus according to claim 3, wherein the condition for operating the gate means is special reproduction including cue, review, and search. 5. The PCM signal reproducing apparatus according to claim 1, wherein the error detecting code is a CRC code. 6. The PCM signal reproducing method according to claim 2, wherein the process of rewriting the detection result of the error detecting means to include an error is limited to a special reproduction including a queue, a review, and a search. PCM signal reproduction method.