JPH05150018A - Logic circuit test mode setting method and circuit - Google Patents

Abstract

PURPOSE:To dispense with an increase in the number of input terminals for the setting of a test mode. CONSTITUTION:When a test mode setting data latch signal is inputted from an input terminal 3, a latch circuit 5 holds the assigned test mode setting data inputted from an input terminal 1 by a latch authorization signal prepared by a latch authorization signal preparing circuit 4 only when a test mode setting authorization signal inputted from an input terminal 2 instructs the preparation of the latch authorization signal, and a decoder circuit 6 decodes setting data and sets an assigned test mode to a logic circuit 7. In the case of the test mode setting authorization signal instructing the preparation of a normal action mode signal, the latch circuit 5 ignores the data from the input terminal 1 by a normal action mode signal prepared by the latch authorization signal preparing circuit 4, and the input terminal 1 inputs normal action data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to creating a test mode for testing a logic circuit.

[0002]

2. Description of the Related Art A conventional method of setting a test mode for a logic circuit requires a dedicated input terminal for each test mode,
As the number of test modes increased, many input terminals were needed.

[0003]

The above-mentioned conventional method has a drawback in that when many test modes are desired to be set, a large number of test mode setting dedicated input terminals are required, which leads to an increase in the number of terminals.

An object of the present invention is to provide a test mode setting method and a circuit for a logic circuit which can set a large number of test modes with a small number of test mode setting dedicated input terminals.

[0005]

According to a method of setting a test mode of a logic circuit of the present invention, a test mode setting data designated by the logic circuit is input to a first terminal to which normal operation data is input during normal operation of the logic circuit. , A test mode setting enable signal to the second terminal, a test mode setting data latch signal to the third terminal, and a test mode setting data latch signal from the third terminal. Is input and a test mode setting enable signal for instructing the creation of the latch enable signal is input from the second terminal,
Let the latch enable signal creation circuit create the latch enable signal,
When the test mode setting data latch signal is input from the third terminal and the test mode setting permission signal for instructing the generation of the normal operation mode signal is input from the second terminal, the normal operation mode signal is input to the latch permission signal generation circuit. And a latch enable signal creating circuit creates a latch enable signal, the test mode setting data latch circuit holds the test mode setting data input from the first terminal, and the latch enable signal creating circuit Generate a normal operation mode signal, the test mode setting data latch circuit is made to ignore the data inputted from the first terminal, and the test mode setting data held in the test mode setting data latch circuit is tested. Mode setting Decode circuit decodes and sets test mode specified in the logic circuit. And a step of.

The test mode setting circuit of the logic circuit of the present invention receives the normal operation data when the logic circuit operates normally, and when the test mode is set to the logic circuit, the designated test mode setting data is input. A first terminal to which the test mode setting permission signal is input, a third terminal to which the test mode setting data latch signal is input, and a test mode setting data latch signal from the third terminal Is input and the test mode setting enable signal input from the second terminal instructs the creation of the latch enable signal, the latch enable signal is created and the test mode setting data latch signal is input from the third terminal. Was
A latch enable signal creating circuit for creating a normal operation mode signal when the test mode setting enable signal input from the second terminal instructs the creation of the normal operation mode signal, and a latch enable signal from the latch enable signal creating circuit. When the signal is received, the test mode setting data input from the first terminal is held, and when the normal operation mode signal is received from the latch enable signal creating circuit, the data input from the first terminal is ignored. A test mode setting data latch circuit,
The test mode setting data latch circuit includes a test mode setting decoding circuit for decoding the test mode setting data held in the test mode setting data latch circuit and setting the test mode specified in the logic circuit.

[0007]

The specified test mode setting data input from the first terminal is set to the test mode setting data only when the test mode setting enabling signal input from the second terminal instructs the creation of the latch enable signal. The number of test modes to be set is large because it is held in the data latch circuit, the first terminal can be used to input a plurality of test mode setting data, and can be used to input normal operation data in the normal operation mode. However, only two input terminals are required for setting the test mode.

[0008]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a test mode setting circuit for a logic circuit according to the present invention.

The test mode setting circuit of this logic circuit is composed of an input terminal 1, an input terminal 2, an input terminal 3, a latch enable signal generating circuit 4, a latch circuit 5 and a decoder circuit 6. It is connected to the logic circuit 7.

Normal operation data is input from the input terminal 1 during normal operation of the logic circuit 7, and designated test mode setting data is input when the test mode of the logic circuit 7 is to be set. A test mode setting permission signal is input from the input terminal 2. A test mode setting data latch signal is input from the input terminal 3. When the test mode setting enable signal is input from the input terminal 2 and the test mode setting data latch signal is input from the input terminal 3, the latch enable signal generating circuit 4 latches the test mode setting enable signal input from the input terminal 2. If the generation of the permission signal is instructed, the latch permission signal is generated, and if the test mode setting permission signal input from the input terminal 2 specifies the normal operation mode signal generation, the normal operation mode signal is generated. The latch circuit 5 holds the test mode setting data input from the input terminal 1 when receiving the latch enable signal from the latch enable signal creating circuit 4, and receives the normal operation mode signal from the latch enable signal creating circuit 4 The data input from 1 is ignored. Decoder circuit 6 decodes the test mode setting data received from latch circuit 5 to set the designated test mode in logic circuit 7.

In the test mode setting circuit of this logic circuit, when the latch circuit 5 receives the normal operation mode signal, the data inputted from the input terminal 1 is ignored, so that the input terminal 1
The normal operation data can be input to the logic circuit 7 for normal operation.

In the test mode setting circuit of the logic circuit of the present embodiment, the input terminal 1 is also used for inputting the normal operation data and the test mode setting data, and a plurality of test modes can be set by simply providing the input terminals 2 and 3. Since it can be set, the dedicated input terminal is the input terminal 2 even if the number of test modes increases.
The required test mode can be set with only two of 3 and 3.

[0014]

As described above, according to the present invention, the test mode setting enable signal input from the second terminal is input from the first terminal only when the instruction to create the latch enable signal is instructed. When setting the test mode in the logic circuit by holding the instructed test mode setting data in the test mode setting data latch circuit, the test mode setting data input terminal is the data input terminal during normal operation of the logic circuit. Since it can also be used as the test mode, even if the number of test modes increases, it is possible to use only the second and third dedicated input terminals, which does not lead to an increase in the number of terminals.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a test mode setting circuit for a logic circuit according to the present invention.

[Explanation of symbols]

 1, 2, 3 Input terminals 4 Latch enable signal creation circuit 5 Latch circuit 6 Decode circuit 7 Logic circuit

Claims (2)

[Claims] 1. A test mode setting method for setting a test mode of a logic circuit, comprising: a specified test mode of the logic circuit at a first terminal to which normal operation data is input during normal operation of the logic circuit. Inputting the setting data, inputting the test mode setting enable signal to the second terminal, inputting the test mode setting data latch signal to the third terminal, and inputting the test mode setting data from the third terminal. When a latch signal is input and a test mode setting enable signal is input from the second terminal to instruct creation of the latch enable signal, the latch enable signal creating circuit is made to create the latch enable signal, and the test mode is set from the third terminal. Data latch signal is input and second
When a test mode setting enable signal for instructing the creation of the normal operation mode signal is input from the terminal of, the step of causing the latch enable signal creating circuit to create the normal operation mode signal, and the latch enable signal creating circuit When created, make the test mode setting data latch circuit hold the test mode setting data input from the first terminal,
A step of causing the test mode setting data latch circuit to ignore the data input from the first terminal when the latch enable signal generating circuit generates the normal operation mode signal; and a step of holding the test mode setting data latch circuit in the test mode setting data latch circuit. And a step of causing the test mode setting decoding circuit to decode the test mode setting data to set the specified test mode in the logic circuit. 2. A test mode setting circuit for setting a test mode of a logic circuit, wherein normal operation data is input during a normal operation of the logic circuit, and when the test mode is set to the logic circuit, a designation is made. The first terminal to which the input test mode setting data is input, the second terminal to which the test mode setting permission signal is input, the third terminal to which the test mode setting data latch signal is input, and the third terminal When the test mode setting data latch signal is input from the terminal and the test mode setting enable signal input from the second terminal is instructing to create the latch enable signal, the latch enable signal is created and the third terminal is used. The test mode setting data latch signal is input, and the test mode setting enable signal input from the second terminal instructs the creation of the normal operation mode signal. When a latch enable signal creating circuit for creating a normal operation mode signal and a latch enable signal from the latch enable signal creating circuit is received, the test mode setting data input from the first terminal is held and the latch enable signal is created. A test mode setting data latch circuit that ignores the data input from the first terminal when receiving the normal operation mode signal from the signal generating circuit, and decodes the test mode setting data held in the test mode setting data latch circuit. And a test mode setting decoding circuit for setting a designated test mode in the logic circuit.