JPS62177635A - Logic circuit - Google Patents

Abstract

PURPOSE:To simply and automatically produce the test pattern of a high detection factor by providing an additional circuit whose output value is always fixed by the information on the input group of a logic circuit and a circuit which selects either of the output of the logic circuit or the additional circuit. CONSTITUTION:A driver control signal 22 is set at 0 when a driver control input 20 is set at 1. Thus a driver 5 and a test signal group 14 are set under a high impedance state. At the same time, a driver control signal 21 is also equal to 1 and therefore a driver 4 outputs the output signal group 11 of an original function as it is to a supply signal group 15 to be applied to other circuits. Then the signal 21 is set at 0 when the input 20 is set at 0 and the driver 4 and a driver output signal group 13 are set under a high impedance state respectively. While the driver 5 outputs the output signal group 12 of a circuit 3 whose value is always fixed with the use of an input signal group 10 of the circuit realizing an original function as an input to said group 15 since the signal 22 is equal to 1. Thus it is possible to produce simply and automatically the test pattern of a high detection factor.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a logic circuit used in a data processing device, and particularly relates to a circuit configuration method for configuring a logic circuit to facilitate testing. .

[Conventional technology]

Conventionally, some logic circuits of this type have a circuit configuration in which an undefined state is output depending on the combination of inputs.

[Problem that the invention seeks to solve]

The above-described conventional logic circuit that outputs an undefined state has a drawback in that when manually creating a test A turn, the combination of inputs must be considered so that an undefined state is not output. Also, when automatically generating the test A data, fix the values of the input terminals, etc. so that an undefined state does not occur.

The drawback is that it is difficult to obtain test results with a high detection rate.

The object of the invention is to provide a logic circuit which eliminates the above-mentioned drawbacks.

[Failure to solve the problem]

According to the present invention, in a logic circuit whose output is in an undefined state in the case of a specific input combination, an additional circuit whose output value is always determined using information of an input group of the logic circuit, and two selection signals, A logic circuit characterized in that it includes a selection circuit that selects and outputs either the output of the logic circuit or the output of the additional circuit.

〔Example〕

Next, two aspects of the present invention will be explained with reference to the drawings.

In FIG. 1 showing a logic circuit according to an embodiment of the present invention, reference numeral 1 denotes a logic circuit that realizes the original function of outputting an undefined state depending on the combination of inputs.

10 is a group of input signals of the logic circuit 1 which realizes the original function, and 11 is a group of output signals of the logic circuit 1 which realizes the original function. The following are the configurations added to carry out the present invention, 3 is an additional circuit whose output value is always determined by inputting the input signal group 10 of the circuit realizing the original function, and 12 is an additional circuit where the output value is always determined. 2 is an AN gate, an ND gate, 4 and 5 are drivers with tri-state outputs, and 20 is a driver control input (
(i.e. selection signal), 21.22 is a driver control signal, 13
14 is a driver output signal group, and 14 is a test signal group.

15 is a group of signals to be supplied to other circuits. A group of output signals 11 with original functions, a group of output signals 12 whose values are always determined,
The number of signal lines of the driver output signal group 13, the test signal group 14, and the supply signal group 15 to other circuits is the same.

Further, the number of drivers 4 and 5 having tri-state outputs is also the same, and these are also equal to the number of signal lines of the output signal group 11 of the original function.

The circuit operation of this embodiment is as follows.

By setting the driver control signal 20 to 1, the driver control signal 22 becomes O, and the driver 5 and test signal group 14 enter a high impedance state. On the other hand, since the dry control signal 21 becomes 1, the driver 4
The output signal group 11 of the two original functions is output as is to the signal group 15 to be supplied to other circuits.

By setting the driver control input 20 to O, the driver control signal 21 becomes O, and the driver 4 and driver output signal group 13 are placed in a high impedance state. Conversely, since the driver control signal 22 becomes 1, the value of the driver 5 is always determined by inputting the input signal group 10 of the circuit that realizes the original function as the input signal group 15 of the supply signal group 15 to other circuits. The output signal group 12 of the circuit 3 is output.

In this way, the AND/HA) gate 2 and the drivers 4 and 5 operate a selection circuit that selects and outputs either the output of the logic circuit 1 or the output of the additional circuit 3 according to the 2 selection signal 20. It consists of

FIG. 2 shows a specific example of FIG. 1.

The table below shows the combinations of input signals of the logic circuit 1 that realizes the original function and the output state at that time.

The additional circuit 3 whose output value is always determined is an EXOR gate.

If 0, 0 or 1°1 is given to the input signal 10a*10b in the conventional circuit, the output will be in an undefined state, but 2
According to this specific example, by setting the dry/4 control input 20 to O, EXO is used as a supply signal to other circuits.
An output value O of Rr -1' 3 is output. Finally, the following output states are given to the signal group 15 to be supplied to other circuits.

〔Effect of the invention〕

As explained above, the present invention relates to a logic circuit whose output is in an undefined state depending on the combination of inputs.

An additional circuit whose output value is always determined using information on an input group of the logic circuit, and a selection circuit which selects either the output of the logic circuit or the output of the additional circuit in response to a 2-selection signal are added. By the way.

By preventing undefined states from becoming input to other logic circuits, there is no need to fix the values of input terminals or manually create patterns when a test or turn occurs, resulting in high detection. This has the effect of easily automatically generating rate test patterns.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a logic circuit according to an embodiment of the present invention, and FIG. 2 is a diagram showing a specific example of the logic circuit of FIG. 1... Logic circuit that realizes the original function, 2...
AND/NΔD gate, 3...Additional circuit whose value is always determined, 4, 5...Driver with tri-state output, 10...Input signal group, 11...Output of circuit 1 Signal group, 12... Output signal group of circuit 3, 13...
Driver output signal group, 14... test signal group, 15
... Supply signal group to other circuits, 2'0... Driver control input (selection signal), 2.1, 22... Driver control signal. Figure 1 Figure 2

Claims (1)

[Claims] 1. In a logic circuit whose output is in an undefined state in the case of a specific input combination, an additional circuit whose output value is always determined using information of the input group of the logic circuit, and according to a selection signal,
A logic circuit comprising: a selection circuit that selects and outputs either the output of the logic circuit or the output of the additional circuit.