JPH0514949B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a microcomputer that includes a built-in tone generator that can output buzzer sounds and melodies.

(b) Prior art Generally, general-purpose microcomputers do not have built-in tone generators, but when using this general-purpose microcomputer to generate melodies, etc., the frequency of the tone to be generated is The output signal of the output terminal was manipulated by an output command so that the tone output time was also created by a program. Therefore, a program that generates a melody or the like has an increased number of steps, and the number of steps of other programs is inconveniently limited.

Therefore, a microcomputer with a built-in tone generator was developed, as described in "NEC Electronic Device New Product Bulletin μPD6651P" published on September 21, 1981. The tone generator divides the fundamental frequency to a specific value to create a tone signal of a predetermined pitch, and also uses a counter to create a time for outputting the created tone signal. Further, the frequency division ratio that determines the pitch of the tone signal and the time for outputting the tone signal are set by the operand data of the command.

(c) Problems to be solved by the invention However, in the conventional microcomputer with a built-in tone generator, it is necessary to process the order, pitch, and occurrence time of each note of a melody using a normal program. Since tone data is sent to the tone generator with a command to generate a tone generator, the tone data written to each operand of the command is different, making programming complicated. Another drawback was that the longer the melody, the longer the number of program steps.

(d) Means for Solving the Problems The present invention has been made in view of the above points, and includes frequency designation data that designates the frequency of a tone signal, and time designation data that designates the generation time of the tone signal. A tone data register that holds tone data consisting of data, a program memory that has a table area that stores a series of tone data such as a melody, and a program area that stores a program, and address data that specifies the table area of the program memory. It includes a register for storing data, and an instruction for switching and applying the address data stored in the register to the program memory, and when the instruction is executed, the tone data read by the address data in the register is transmitted via the data bus. This is set in the tone data register.

(E) Effect According to the above-mentioned means, a predetermined instruction (table reference instruction) stored in the program area is specified by the program counter, and when this instruction is executed, the instruction is stored in the register instead of the program counter. address data is applied to the program memory, and tone data in a table area specified by the address data is preset in the tone data register via the data bus. The frequency division ratio of the reference frequency is set by the frequency designation data set in the tone data register, and a tone signal of a predetermined frequency is created. on the other hand,
The time specified by the timer counter is set by the time designation data set in the tone data register, and the tone signal is output to the outside for that time. Therefore, the same command can be used to output each sound of the melody.

(F) Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention. 1 and 2 are counters, 3 and 4 are ROMs, 5 is a pulse generation circuit, and 6 is a tone data register, which constitute a tone generator. The tone data register 6 is composed of 8 bits, the lower 4 bits store frequency designation data that designates the frequency of the tone signal, and the higher 4 bits store time designation data that designates the time to output the tone signal. The ROM 3 receives the output of the lower 4 bits of the tone data register 6, that is, the frequency designation data, and creates a numerical value counted by the counter 1 in order to create the frequency designated by the data. Counter 1 consists of a down counter, which counts the numerical value applied from ROM3 based on the reference frequency CL1, and when the counting is completed, it is set to "0" by the built-in T-FF (flip-flop).
and “1” output alternately. The pulse generating circuit 5 generates a pulse based on the signal outputted when the counter 1 finishes counting, and applies it to the counter 1 via the OR gate 7, causing the counter 1 to set the value from the ROM 3 again and restart counting. Therefore, by repeatedly counting the numerical value created by the ROM 3 by the counter 1 based on the reference frequency CL1, a tone signal of the frequency designated by the frequency designation data is created. That is, ROM3,
Counter 1, pulse generation circuit 5 and OR gate 7
forms a tone signal generation circuit.

On the other hand, the counter 2 and the ROM 4 form a tone time generation circuit, and the ROM 4 inputs the upper 4 bits output of the tone data register 6, that is, time designation data, and creates a numerical value counted by the counter 2. Counter 2 is formed by a down counter, and uses the value applied from ROM 4 as a reference frequency.
By counting based on CL2, AND is performed by the output during the time from the start of counting to the end of counting.
It controls the gate 8 and outputs the tone signal output from the counter 1 to the outside. That is, it determines the generation time of the tone signal.

The control circuit 9 controls the internal operation of the microcomputer based on the output from the instruction decoder 10 and the timing signal from the timing generator 11, and performs interrupt control to which the output from the counter 2 is applied. It has a built-in circuit 12. The timing generator 11 generates timing signals necessary for the operation of the microcomputer based on the reference clock pulse CP, and one machine cycle consists of T ₁ , T ₂ ,
It consists of four basic timings: T ₃ and T ₄ . The instruction decoder 10 is
The output of the instruction register 14 which stores the instruction code to be executed read from the ROM 13, that is, the instruction code is input and the control circuit 9 decodes the instruction. Instructs the control signal to

The ROM 13 is a program area 15 in which a program consisting of a set of instruction codes is permanently stored.
and a table area 16 in which tone data indicating the pitch and length of each note constituting a melody is stored, and the output of a multiplexer 17 is connected to the address input of the ROM 15.
The output of the program counter 18 is applied to the input of the multiplexer 17, and the address is specified by the output of the accumulator 19, which temporarily holds data, and the data pointer 20.
The output of RAM21 is applied. The multiplexer 17 normally outputs the output of the program counter 18.
The instruction code is applied to the ROM 13 to enable the program counter 18 to specify the address of the program area 15, and at this time, the read instruction code is sent to the instruction register 14 and stored therein. Further, the multiplexer 17 is controlled by a control signal TABLE output from the control circuit 9 when a table reference instruction (TML instruction) is executed, and the multiplexer 17 is controlled by the control signal TABLE outputted from the control circuit 9.
The output of the table area 1 is applied to the ROM 13, and the table area 1 is
6 addresses can be specified. At this time, the read tone data is sent to the data bus 22 and applied to the tone data register 6. In addition, the data bus 22 includes a ROM 13, an accumulator 19, a RAM 21, and a data pointer 2.
0 input/output is connected.

A table reference instruction (TML instruction) is an instruction that takes two machine cycles to execute, and the operation when the TML instruction is executed will be explained with reference to FIG. The TML instruction is provided in a program stored in the program area 15 of the ROM 13, and is executed when it is necessary to generate a melody. First, before executing the TML instruction, ROM1
In order to specify the address of the tone data constituting the melody stored in the table area 16 of 3, the lower 4 bits of the tone data address are set in the accumulator 19, and the upper 4 bits of the tone data address are stored. RAM21
The address of is set in the data pointer 20.
Next, when the TML instruction is executed, the control signal TABLE becomes "1" during timings T ₃ and T ₄ of the first machine cycle, and the data of the accumulator 19 is used instead of the output of the program counter 18. specified by data pointer 20
Data read from the RAM 21 is applied to the ROM 13 via the multiplexer 17, and the table area 16 specified by these data is
The tone data stored at the address is sent to the data bus 22. In addition, the control circuit 9
From then on, a control signal STB1 is output to the tone data register 6 at the first half of timing _T4 , that is, at timing _T3 , and the tone data sent to the data bus 22 by this control signal STB1 is stored in the tone data register 6. Ru. The upper 4 bits of the tone data stored in the tone data register 6 are applied to the ROM 4, and the ROM 4 outputs a numerical value for creating the time specified by the data of the upper bits. Furthermore, the lower 4 bits of the tone data are applied to the ROM 3, and the ROM 3 outputs a numerical value for creating the frequency of the tone signal. At this time, a control signal is sent from the control circuit 9 at the latter half of the timing _T4 , that is, at the timing _T4・CP.
STB2 is applied to counter 2 and also applied to counter 1 via OR gate 7. This control signal STB2 sets the output of the ROM 4 in the counter 2, and the counter 2 starts counting the reference frequency CL2 and sets the output to "1".
Further, the output of the ROM 3 is set in the counter 1, and the counter 1 starts counting the reference frequency CL1. Therefore, by generating the control signal STB2, generation of a tone having the pitch and length specified by the tone data is started. In the second machine cycle, the control signal TABLE becomes "0" and the output of the address counter 18 is applied to the ROM 13 via the multiplexer 17 again. and,
At timing T ₄ of the second machine cycle,
The instruction in the program area 15 specified by the program counter 18 is read out and set in the instruction register 14. Therefore, the normal program is executed even while the tone signal is being generated.

When the predetermined tone signal is output by the above operation, when the count of the counter 2 is completed, the output of the counter 2 becomes "0", and the AND gate 5
At this point, the output from counter 1 is cut off, and the tone signal up to that point is stopped. Further, since the signal in which the output of the counter 2 becomes "0" is applied as the end signal FIN of the tone signal to the interrupt control circuit 12 of the control circuit 9, the control circuit 9 controls the interrupt processing program. FIG. 3 shows the timing of interrupts. end signal
When the interrupt by FIN is accepted, the start address of the interrupt program is set in the program counter 18, and execution of the interrupt program is started. In this interrupt processing, after data is set to the accumulator 19 and data pointer 20 in the same way as described above,
TML instructions are executed. As a result, tone data indicating the pitch and length of the next tone is read from the ROM 13 and set in the tone data register 6. Therefore, the next tone signal is sent out from the melody output following the previous tone signal.

In this way, by storing tone data indicating the pitch and length of each note making up a melody in the table area 16 of the ROM 13, tone signals making up the melody can be created just by executing TML instructions. Furthermore, when changing the melody, it is sufficient to simply change the tone data stored in the table area 16. Furthermore, if the tone data of several melodies is stored in the table area 16, the accumulator 19 can be changed. It is also possible to generate a plurality of melodies simply by changing the address data stored in the RAM 21 to specify the start address of each melody.

(G) Effects of the Invention As described above, according to the present invention, the command for generating a tone signal such as a melody or a buzzer requires only a table reference command, making it easy to create a program for creating a melody. Furthermore, the number of program steps is reduced, which has the advantage of increasing other program capacities.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are timing diagrams showing the operation of the embodiment shown in FIG. 1, 2...Counter, 3, 4...ROM, 5...
... Pulse generation circuit, 6 ... Tone data register, 9 ... Control circuit, 10 ... Instruction decoder, 11 ... Timing generator, 12 ... Interrupt control circuit, 13 ...
ROM, 14...instruction register,
15...Program area, 16...Table area, 17...Multiplexer, 18...Program counter, 19...Accumulator, 20...
...Data pointer, 21...RAM, 22...Data bus.

Claims (1)

[Scope of Claims] 1. A tone generation circuit that creates a tone signal with a frequency based on frequency designation data, a tone time creation circuit that creates a time to generate the tone signal based on time designation data, and the tone signal. a tone data register that holds tone data consisting of the frequency designation data and time data in order to generate the tone data for a predetermined period of time; a program memory having a table area that stores the tone data; and a program area that stores a program; and the table area. and an instruction for switching and applying the address data held in the register to the program memory, and when the instruction is executed, the address data of the register is read out. A microcomputer with a built-in tone generator, characterized in that tone data generated by a tone generator is set in a tone data register via a data bus. 2 In claim 1, the register specifying the address of the table area is a RAM.
A microcomputer having a built-in area and a tone generator characterized by being an accumulator.