JPH0514770A - Digital filter for video band waveform equalizer - Google Patents

Abstract

PURPOSE:To attain the high speed of multification, to enable a time dividing processing, and to simplify a circuit constitution by separately calculating a carry to which a partial product is added, and a SUM, without allowing a multifier to have a carry look ahead adding circuit CLA. CONSTITUTION:Coefficient registers 41-4N, and data registors 21-2N, and 22N+1-23N are enabled by the rise of the clock of a two phase clock generating circuit 7, and 1 Nth order sum of product arithmetic circuits are turned active. Then, at the time of the completion of the arithmetic operation, the residual coefficient and data registers are enabled by the rise of an other clock of the circuit 7, N+1-2Nth order sum of product arithmetic circuits are turned active, and the Nth order arithmetic operation is operated. Thus, a 2Nth order filter can be prepared by the N pieces of sum of product conversion circuits, the carry to which the partial product is added, and the SUM are transmitted by different systems, and they are added by a CLA 6 at a final stage. Thus, the high speed of the multification can be attained, and the circuit constitution can be simplified.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated waveform equalizing digital filter used for TV, VTR, communication and the like.

[0002]

2. Description of the Related Art FIG. 2 shows a configuration example of a conventional video band waveform equalizing filter. Reference numerals 1, 2, 3 and 4 in the figure respectively denote a multiplier, a delay device (data register), an adder and a coefficient register.

Next, the operation will be described. An analog signal in the video band to be waveform equalized is converted into an n-bit digital signal by an A / D converter (not shown) and then input to the waveform equalization filter. This digital input signal x
, After being delayer (data register) 2 ₀ at a predetermined time delay, is input to the multiplier 1 ₁ to 1 _2N. The multiplier 1 ₁ multiplies the input signal x by the n-bit coefficient data a _2N stored in the coefficient register 4 ₁ , and the product a _2N x
(z) (where x (z) represents the z-transform of x) is delayed by the delay unit 2 _{1 for a} predetermined time and input to the adder 3 ₁ .
The result of multiplication by the multiplier 4 ₂ is added to a _2N-1 x (z).
Therefore, from the adder 3 ₁ , a _2N x (z) z ^-1 + a _2N-1 x
(z) is output. Similarly, the adder 3 _{2 outputs} a _2N
x (z) z ^-2 + a _2N-1 x (z) z ^-1 + a _2N-2 is output, and finally a _2N x (z) z ^{-2N + 1} + a is output from the adder 3 _2N-1.
2N-1 x (z) z ^{-2N + 2} + a _2N-2 x (z) z ^{-2N + 3} + ... + a ₂
x (z) z ⁻¹ + a ₁ x (z) is output, delayed by a delay device 2 _{2N for a} predetermined time, and output to the outside.

[0004]

The conventional video band waveform equalizing filter is constructed as described above, and the product-sum operation circuit is required for the order of the filter. Therefore, there has been a problem that an attempt to realize a high-order video band digital filter requires a considerably large circuit scale and is expensive because a process needs to be devised.

The present invention has been made in order to solve the above-mentioned problems of the conventional one, and obtains a digital filter for equalizing a video band waveform capable of realizing a high-order filter with a smaller circuit scale. The purpose is that.

[0006]

A digital filter for video band waveform equalization according to the present invention has a carry look-ahead adder circuit (Carry Look Ahead; Called CLA),
Carry and SUM in which each partial product is added instead of the multiplication result
It is configured so as to speed up the multiplication and to execute the Nth-order multiply-add operation a plurality of times by using the separately calculated values as the output results.

[0007]

According to the present invention, with the above-described structure, the structure of the digital filter for video band waveform equalization can be simplified, and the circuit scale and cost can be reduced.

That is, since the operation time of the multiplier of the digital filter is slow, the element constituting the filter that determines the upper limit of the operation time is:
Usually, it is a multiplier, and the CLA calculation time is a major factor that determines the calculation time in the multiplier. However, in the digital filter, only the final output is necessary, and the result of each multiplier is not necessary. , CLA is removed from the multiplier, carry and SUM are separately added to the next stage, CLA is provided at the final stage of the filter, and the result is output. Is what you get. That is, by eliminating the CLA of each multiplier, it is possible to shorten the operation time of each product-sum operation part, and it is possible to configure a time-division processing in which the output is fed back to the input and the product-sum operation is repeated a plurality of times. Become. This is due to the use of the feedback configuration above.
High-order filters can be realized with a small circuit scale.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a digital filter for equalizing a video band waveform according to an embodiment of the present invention.

In the figure, 10 is a multiplier without CLA, 2 is a delay device (data register), 3 is an adder, 4 is a coefficient register, 5 is a multiplexer, 6 is a CLA, and 7 is a two-phase clock generation circuit. is there.

Next, the operation will be described. In this embodiment, each of the multipliers 10 ₁ to 10 _N does not have a CLA in its circuit, and the adders 3 _{1 to} 3 _N , 3 are included.
_{N + 1 to} 3 _2N , multiplexers 5 _{0 to} 5 ₂ ... _, 5 _{N to} 5
_{The N + 2} and the data registers 2 ₁ to 2 _{2N and} 2 _{2N + 1} to 2 _4N are provided as separate systems for the carry and the SUM, so that the carry and the SUM in which the partial products are added are separately propagated. As a result, it is possible to perform the multiplication that governs the filter calculation speed at high speed. Therefore, in the present embodiment, it is possible to perform the filter operation by time division, that is, using the same operation circuit a plurality of times.

The time division processing will be described below.
The two-phase clock generation circuit 7 generates a one-phase clock at the beginning of the operation cycle, and at the rise of this one-phase clock, the lower side 4 ₁ to 4 _N of each coefficient register and the lower side 2 ₁ to 2 _{N of the} data register. , 2 _{2N + 1 to} 2 _3N are enabled,
The 1st to Nth order multiply-accumulate operation circuits become active. Since the product-sum calculation operation of this N-th order product-sum calculation circuit is the same as that of the conventional one, its explanation is omitted. When the Nth-order multiply-add operation is completed, the two-phase clock generation circuit 7 generates another phase clock, and at the rising edge of this clock, the upper side 4 _{N + 1} to 4 _{2 N} of each coefficient register and the upper side ₂ of the data register. _{N + 1 to} 2 _2N ,
2 _{3N + 1 to} 2 _4N are enabled, the _{N + 1} to 2Nth-order product-sum operation circuits are activated, and the remaining N-th order product-sum operation is performed. That is, it is possible to construct a 2Nth-order filter with N product-sum operation circuits using a two-phase clock. The multiplexer added to the output of each register switches the output of the register motivated by the clock. In addition, carry and SU with each partial product added
M is propagated through different systems, and is added by CLA6 at the final stage.

As described above, according to the above-described embodiment, the carry and the SUM are propagated in different systems, respectively, and CL is transmitted at the final stage.
Taking advantage of the fact that the addition by A removes CLA from each of the multipliers forming the product-sum operation circuit to speed up the operation, and that the multiplication speed that governs the operation speed of the filter operation is increased. Since the Nth-order filter circuit is made to operate as a 2Nth-order filter circuit by returning the output of the Nth-order filter circuit to the input again, there is an effect that a high-order filter can be realized at a small circuit scale and at a low cost.

In the above embodiment, the case where the Nth-order filter is used as a 2Nth-order filter has been described as an example. However, the present invention is not limited to this, and it is naturally applicable to an N-th order integer multiple. Needless to say.

Further, although the transposition type digital filter has been described as an example in the above embodiment, it is needless to say that the present invention is not limited to this and can be applied to other types of digital filters.

Further, in the above-mentioned embodiment, the case where the waveform equalization of the video band signal is performed has been described as an example, but it goes without saying that a digital filter in a frequency domain other than this can also be applied.

[0017]

As described above, according to the video band waveform equalization filter of the present invention, the carry and the SUM are propagated separately without providing each multiplier with a CLA circuit, thereby increasing the speed of multiplication. Since it is possible to perform the time-division processing a plurality of times by this, the order of the filter can be equivalently multiplied by an integer. Therefore, a high-order filter can be realized with a small circuit scale, and a digital filter in the video band, which has been very expensive until now, can be realized at low cost.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a video band waveform equalizing filter according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional video band waveform equalization filter.

[Explanation of symbols]

 1 Multiplier 10 Multiplier without CLA 2 Register (delayer) 3 Adder 4 Coefficient register 5 Multiplexer 6 CLA 7 Two-phase clock generation circuit

Claims (1)

Claim: What is claimed is: 1. A digital filter used for waveform equalization of a video band signal, wherein each multiplier constituting the product-sum operation circuit does not have a carry look-ahead addition circuit. A video band waveform characterized in that it has a path for separately propagating carry and sum (SUM) output from the multiplier, and is capable of executing N-th (N is a positive integer) multiply-accumulate operation multiple times. Digital filter for equalization.