JPH05144969A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05144969A JPH05144969A JP30144391A JP30144391A JPH05144969A JP H05144969 A JPH05144969 A JP H05144969A JP 30144391 A JP30144391 A JP 30144391A JP 30144391 A JP30144391 A JP 30144391A JP H05144969 A JPH05144969 A JP H05144969A
- Authority
- JP
- Japan
- Prior art keywords
- insulating substrate
- semiconductor device
- circuit pattern
- board
- heat sink
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
Landscapes
- Structure Of Printed Boards (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、絶縁基板を有する半導
体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an insulating substrate.
【０００２】[0002]
【従来の技術】図３（ａ）は従来の半導体装置の平面図
であり、図３（ｂ）はその断面図である。図３におい
て、１は放熱板、２は絶縁基板、３，４はこの絶縁基板
２の回路パターン部、５は前記放熱板１と絶縁基板２の
固着に用いる半田、６は半導体素子、７はこの半導体素
子６と絶縁基板２の固着に用いる半田である。また、図
４（ａ）〜（ｄ）に従来の絶縁基板の表，裏面のパター
ンおよびその縦断部分拡大断面図および横断面図を示
す。2. Description of the Related Art FIG. 3A is a plan view of a conventional semiconductor device, and FIG. 3B is a sectional view thereof. In FIG. 3, 1 is a heat sink, 2 is an insulating substrate, 3 and 4 are circuit pattern portions of this insulating substrate 2, 5 is solder used for fixing the heat sink 1 and the insulating substrate 2, 6 is a semiconductor element, and 7 is This is a solder used for fixing the semiconductor element 6 and the insulating substrate 2. Further, FIGS. 4A to 4D show front and back patterns of a conventional insulating substrate, and an enlarged sectional view and a lateral sectional view of a longitudinal section thereof.
【０００３】この半導体装置は以下のように組み立てら
れる。まず、放熱板１上に半田５を介し、絶縁基板２を
配置する。さらに、半田７を介し、半導体素子６を配置
する。そして、これらをあらかじめ熱した放熱板１の上
に載せるか、リフロー炉を通すことにより各部品を融着
する。This semiconductor device is assembled as follows. First, the insulating substrate 2 is arranged on the heat sink 1 with the solder 5 interposed therebetween. Further, the semiconductor element 6 is arranged via the solder 7. Then, these parts are placed on the heat radiating plate 1 which is heated in advance, or are passed through a reflow furnace to fuse the respective parts.
【０００４】[0004]
【発明が解決しようとする課題】従来の半導体装置は以
上のように構成され組み立てられるので、絶縁基板２と
放熱板１の間の半田５の縮小により放熱板１にそりが発
生することがあり、この放熱板１に発生するそりにより
絶縁基板２に割れを生じさせようとする応力がかかると
いう問題があった。また、割れが生じた場合には絶縁基
板２の絶縁不良を起こすという問題点があった。Since the conventional semiconductor device is constructed and assembled as described above, the heat sink 1 may be warped due to the reduction of the solder 5 between the insulating substrate 2 and the heat sink 1. However, there is a problem in that the warp generated in the heat dissipation plate 1 exerts a stress that causes the insulating substrate 2 to crack. Further, there is a problem that when the cracks occur, the insulation failure of the insulating substrate 2 occurs.
【０００５】本発明は、上記のような問題点を解消する
ためになされたもので、従来とおりの構成，製造方法で
も絶縁不良を防止できる半導体装置を得ることを目的と
する。The present invention has been made to solve the above problems, and an object of the present invention is to obtain a semiconductor device capable of preventing insulation failure even with the conventional structure and manufacturing method.
【０００６】[0006]
【課題を解決するための手段】本発明に係る半導体装置
は、絶縁基板の表面と裏面で同一形状とした回路パター
ン部間にスリット部を形成したものである。A semiconductor device according to the present invention has a slit portion formed between circuit pattern portions having the same shape on the front surface and the back surface of an insulating substrate.
【０００７】[0007]
【作用】本発明においては、絶縁基板に加わる応力がス
リット部に加わるようになる。しかも、裏面の回路パタ
ーン部が同一形状であるので、スリット部に割れが生じ
る場合でも、その位置が回路パターン部間に確実に制限
される。In the present invention, the stress applied to the insulating substrate is applied to the slit portion. Moreover, since the circuit pattern portions on the back surface have the same shape, even if cracks occur in the slit portions, their positions are reliably limited between the circuit pattern portions.
【０００８】[0008]
【実施例】以下、本発明の一実施例を図について説明す
る。図１（ａ），（ｂ）は本発明の半導体装置の平面図
および断面図である。図において、１は放熱板、２は絶
縁基板、３，４はこの絶縁基板２の回路パターン部、５
は前記放熱板１と絶縁基板２の固着に用いる半田、６は
半導体素子、７はこの半導体素子６と絶縁基板２の固着
に用いる半田、８は前記絶縁基板２の回路パターン３，
４間にそれぞれ設けたスリット部である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1A and 1B are a plan view and a sectional view of a semiconductor device of the present invention. In the figure, 1 is a heat sink, 2 is an insulating substrate, 3 and 4 are circuit pattern portions of this insulating substrate 2, and 5
Is a solder used for fixing the heat sink 1 to the insulating substrate 2, 6 is a semiconductor element, 7 is solder used for fixing the semiconductor element 6 and the insulating substrate 2, and 8 is a circuit pattern 3 of the insulating substrate 2.
It is a slit portion provided between each of the four.
【０００９】次に、作用について図１〜図２を用いて説
明する。図３，図４に示したような従来の半導体装置で
は、絶縁基板２の表，裏面の回路パターン部３，４が別
々であり、裏面（放熱板１と固着する面）の半田固着面
積が広かったたため、放熱板１が大きくなって絶縁基板
２にクラックが発生することがあったが、本発明では回
路パターン部３，４間にそれぞれスリット部８を設けて
いるため、加熱時に絶縁基板２の回路部に加わる応力を
緩和でき、発生するクラックをスリット部８に集めるこ
とができる。また、特に図１，図２に示したように、絶
縁基板２の表面と裏面の回路パターン部３，４を同一と
することにより、応力をさらに緩和できるほか、クラッ
クが生じても絶縁不良を生じないように構成することが
できる。Next, the operation will be described with reference to FIGS. In the conventional semiconductor device as shown in FIGS. 3 and 4, the circuit pattern portions 3 and 4 on the front and back surfaces of the insulating substrate 2 are separate, and the solder fixing area on the back surface (the surface fixed to the heat sink 1) is small. Since it is wide, the heat sink 1 may become large and cracks may occur in the insulating substrate 2. However, in the present invention, since the slit portions 8 are provided between the circuit pattern portions 3 and 4, respectively, the insulating substrate is heated during heating. The stress applied to the second circuit portion can be relaxed, and the generated cracks can be collected in the slit portion 8. Further, as shown in FIGS. 1 and 2, in particular, by making the circuit pattern portions 3 and 4 on the front surface and the back surface of the insulating substrate 2 the same, the stress can be further relieved, and even if cracks occur, insulation failure can be prevented. It can be configured so that it does not occur.
【００１０】なお、上記実施例ではスリット部８を連続
した溝で設けたが、図２に示すように、ミシン目のよう
な不連続な穴によってスリット部８を形成してもよい。Although the slit portion 8 is provided as a continuous groove in the above embodiment, the slit portion 8 may be formed by a discontinuous hole such as a perforation as shown in FIG.
【００１１】[0011]
【発明の効果】以上説明したように、本発明は、回路パ
ターン部間にスリット部を形成したので、例えば加熱時
等の応力が回路部以外のスリット部に加わるようにで
き、放熱板のそりや、その他の応力により絶縁基板が割
れるような場合でも任意の場所で割れるようなことがな
くなるため、半導体装置が絶縁不良になることがなくな
り、歩留りを向上できる。しかも、回路パターン部を絶
縁基板の表面および裏面で同一形状としたことにより、
表，裏のスリット部の位置が一致し、絶縁基板が万一割
れるときでも、必ずスリット部から割れるので、一層信
頼度を向上できるという効果がある。As described above, according to the present invention, since the slit portions are formed between the circuit pattern portions, for example, stress at the time of heating can be applied to the slit portions other than the circuit portion, and the heat dissipation plate can be bent. Also, even if the insulating substrate is cracked due to other stress, it will not be cracked at any place, so that the semiconductor device will not be defective in insulation and the yield can be improved. Moreover, since the circuit pattern portion has the same shape on the front surface and the back surface of the insulating substrate,
Even if the positions of the slits on the front and back sides coincide with each other and the insulating substrate should be cracked, the slits are always cracked, so that the reliability can be further improved.
【図１】本発明の半導体装置の一実施例における平面図
および断面側面図である。FIG. 1 is a plan view and a cross-sectional side view in an embodiment of a semiconductor device of the present invention.
【図２】本発明の他の実施例における絶縁基板を示す図
である。FIG. 2 is a diagram showing an insulating substrate according to another embodiment of the present invention.
【図３】従来の半導体装置の平面図および断面側面図で
ある。FIG. 3 is a plan view and a sectional side view of a conventional semiconductor device.
【図４】従来の半導体装置における絶縁基板を示す図で
ある。FIG. 4 is a diagram showing an insulating substrate in a conventional semiconductor device.
１ 放熱板 ２ 絶縁基板 ３ 回路パターン部 ４ 回路パターン部 ５ 半田 ６ 半導体素子 ７ 半田 ８ スリット部 1 Heat sink 2 Insulating substrate 3 Circuit pattern part 4 Circuit pattern part 5 Solder 6 Semiconductor element 7 Solder 8 Slit part
Claims (1)
回路パターン部が形成された絶縁基板が載置され、さら
にこの絶縁基板上にロー材を介して半導体素子が載置さ
れ、加熱されることにより前記放熱板，絶縁基板および
半導体素子が融着される半導体装置において、回路パタ
ーン部を絶縁基板の表面および裏面で同一形状とすると
ともに、前記回路パターン部間にスリット部を形成した
ことを特徴とする半導体装置。1. An insulating substrate having a plurality of circuit pattern portions formed on both surfaces thereof is mounted on a heat dissipation plate via a brazing material, and a semiconductor element is mounted on the insulating substrate via the brazing material. In a semiconductor device in which the heat sink, the insulating substrate, and the semiconductor element are fused by being heated, the circuit pattern portion has the same shape on the front surface and the back surface of the insulating substrate, and a slit portion is formed between the circuit pattern portions. A semiconductor device characterized by the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30144391A JPH05144969A (en) | 1991-11-18 | 1991-11-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30144391A JPH05144969A (en) | 1991-11-18 | 1991-11-18 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05144969A true JPH05144969A (en) | 1993-06-11 |
Family
ID=17896957
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30144391A Pending JPH05144969A (en) | 1991-11-18 | 1991-11-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05144969A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012085045A (en) * | 2010-10-08 | 2012-04-26 | Nippon Dempa Kogyo Co Ltd | Oven-controlled crystal oscillator |
| JP2012085046A (en) * | 2010-10-08 | 2012-04-26 | Nippon Dempa Kogyo Co Ltd | Oven-controlled crystal oscillator |
-
1991
- 1991-11-18 JP JP30144391A patent/JPH05144969A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012085045A (en) * | 2010-10-08 | 2012-04-26 | Nippon Dempa Kogyo Co Ltd | Oven-controlled crystal oscillator |
| JP2012085046A (en) * | 2010-10-08 | 2012-04-26 | Nippon Dempa Kogyo Co Ltd | Oven-controlled crystal oscillator |
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