JPH0514429B2 - - Google Patents
Info
- Publication number
- JPH0514429B2 JPH0514429B2 JP60288328A JP28832885A JPH0514429B2 JP H0514429 B2 JPH0514429 B2 JP H0514429B2 JP 60288328 A JP60288328 A JP 60288328A JP 28832885 A JP28832885 A JP 28832885A JP H0514429 B2 JPH0514429 B2 JP H0514429B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- conductive path
- resistance region
- semiconductor substrate
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
(イ) 産業上の利用分野
本発明はイオン注入法により形成した抵抗領域
上に多層配線を行つた半導体集積回路装置に関す
る。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a semiconductor integrated circuit device in which multilayer wiring is formed on a resistance region formed by ion implantation.
(ロ) 従来の技術
例えば実公昭53−52393号公報に記載されてい
る如く、IC上に組み込む抵抗素子としてインプ
ラ抵抗を用いれば、拡散抵抗では困難であつた数
＋ＫΩ〜数ＭΩの高抵抗を構成することが可能で
ある。(b) Conventional technology For example, as described in Japanese Utility Model Publication No. 53-52393, if an implant resistor is used as a resistive element to be incorporated into an IC, it is possible to achieve a high resistance of several KΩ to several MΩ, which is difficult to achieve with a diffused resistor. It is possible to configure
第４図及び第５図はこのようなインプラ抵抗の
上に多層配線を行つた装置を示し、１は半導体基
体、２はイオン注入により形成した抵抗領域、３
はあらかじめ抵抗領域２の両端に設けたコンタク
ト領域、４は抵抗領域２上の他より薄い第１の絶
縁膜、５，６は電極、７は第２の絶縁膜、８は抵
抗領域２上の第２の絶縁膜７の上に配設した第２
の導電路である。第１の絶縁膜４は最終工程で形
成するため厚さが800〜3000Å程度の非常に薄い
絶縁膜となつており、そこに急峻な段差を有する
溝を形成してしまう。 4 and 5 show a device in which multilayer wiring is formed on such an implant resistor, in which 1 is a semiconductor substrate, 2 is a resistance region formed by ion implantation, and 3 is a resistor region formed by ion implantation.
are contact regions provided in advance at both ends of the resistance region 2, 4 is a first insulating film thinner than the others on the resistance region 2, 5 and 6 are electrodes, 7 is a second insulating film, and 8 is a contact region on the resistance region 2. A second insulating film 7 disposed on the second insulating film 7
It is a conductive path. Since the first insulating film 4 is formed in the final step, it is a very thin insulating film with a thickness of about 800 to 3000 Å, and a trench with a steep step is formed there.
(ハ) 発明が解決しようとする問題点
しかしながら、前記溝内は狭く急峻であるので
第２の絶縁膜７にクラツクや他より特に薄い部分
が生じやすく、そのため特に抵抗領域２との電位
差が大になるような第２の導電路８、例えば電源
電位の配線等を抵抗領域２の上に配設すると、第
１の絶縁膜４が非常に薄いことと相まつて短絡事
故が発生しやすいという欠点があつた。(C) Problems to be Solved by the Invention However, since the inside of the groove is narrow and steep, cracks and parts that are particularly thinner than others are likely to occur in the second insulating film 7, and therefore the potential difference between the second insulating film 7 and the resistance region 2 is particularly large. If the second conductive path 8, such as power supply potential wiring, is disposed on the resistive region 2, the disadvantage is that the first insulating film 4 is very thin and short circuits are likely to occur. It was hot.
(ニ) 問題点を解決するための手段
本発明は斯上した欠点に鑑みてなされ、前記溝
内の第１の絶縁膜１４を第１の導電路１５で保護
し、それから第２の絶縁膜１８をはさんで第２の
導電路１９を配設したことを特徴とする。(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned drawbacks, and includes protecting the first insulating film 14 in the groove with a first conductive path 15, and then protecting the first insulating film 14 in the groove with a first conductive path 15. It is characterized in that a second conductive path 19 is provided across the conductive path 18.
(ホ) 作用
本発明によれば、あらかじめ前記溝を第１の導
電路１５で埋没してから第２の絶縁膜１８を形成
するので、抵抗領域１２と第２の導電路１９との
短絡事故を防止することができる。(e) Effect According to the present invention, since the trench is buried with the first conductive path 15 before the second insulating film 18 is formed, short-circuit accidents between the resistance region 12 and the second conductive path 19 are avoided. can be prevented.
(ヘ) 実施例
以下、本発明を図面を参照しながら詳細に説明
する。(f) Examples Hereinafter, the present invention will be explained in detail with reference to the drawings.
第１乃至第３図は本発明による装置を示し、１
１は半導体基板、１２はイオン注入により形成し
た抵抗領域、１３はあらかじめ抵抗領域１２の両
端に設けたコンタクト領域、１４は抵抗領域１２
上の他より薄いシリコン酸化膜より成る第１の絶
縁膜、１５はアルミニウムより成る第１の導電
路、１６，１７は第１、第２の電極、１８はポリ
イミド系樹脂より成る第２の絶縁膜、１９は第１
の導電路１５の上に第２の絶縁膜１８をはさんで
配設した第２の導電路である。 1 to 3 show an apparatus according to the invention, 1
1 is a semiconductor substrate, 12 is a resistance region formed by ion implantation, 13 is a contact region provided in advance at both ends of the resistance region 12, and 14 is a resistance region 12.
A first insulating film made of a silicon oxide film thinner than the others above; 15 a first conductive path made of aluminum; 16 and 17 first and second electrodes; 18 a second insulating film made of polyimide resin. membrane, 19 is the first
This is a second conductive path disposed on the conductive path 15 of , with a second insulating film 18 interposed therebetween.
目的の抵抗値を達成するために、できる限り熱
処理工程が加わらないIC製造の最終工程でイオ
ン注入工程を取り入れるため、第１の絶縁膜１４
は、厚さが800〜3000Å程度のシリコン酸化膜と
なつており、抵抗領域１２以外の半導体基板１１
表面のシリコン酸化膜より非常に薄くなつてい
る。この薄い絶縁膜１４の形成される理由は、半
導体基板を露出して直接イオン注入し、その後薄
い絶縁膜をキヤツプしアウトデイフユージヨン等
の防止をしながらアニールするため、またはイオ
ンを注入する前に薄い絶縁膜を形成し、この絶縁
膜により不純物の濃度分布を均一にしたり、欠陥
やアウトデイフユージヨンの防止をするためであ
る。抵抗領域１２はコンタクト領域１３を介して
第１、第２の電極１６，１７により導出される。
第１、第２の電極１６，１７及び第１の導電路１
５は共に１層目の配線工程で形成されており、第
１の導電路１５は第１の電極１６から延在するよ
うに形成して抵抗領域１２の一端の電位を印加し
ている。その後第２の絶縁膜１８を形成し、第１
の導電路１５の上に第２の絶縁膜１８をはさんで
第２の導電路１９を形成している。 In order to incorporate an ion implantation process in the final process of IC manufacturing with as little heat treatment as possible in order to achieve the desired resistance value, the first insulating film 14 is
is a silicon oxide film with a thickness of about 800 to 3000 Å, and covers the semiconductor substrate 11 other than the resistance region 12.
It is much thinner than the silicon oxide film on the surface. The reason why this thin insulating film 14 is formed is that the semiconductor substrate is exposed and ions are directly implanted, and then the thin insulating film is capped and annealed while preventing out-diffusion, etc., or ions are implanted. This is because a thin insulating film is formed beforehand, and this insulating film makes the concentration distribution of impurities uniform and prevents defects and out-diffusion. The resistance region 12 is led out by first and second electrodes 16 and 17 via a contact region 13 .
First and second electrodes 16, 17 and first conductive path 1
5 are both formed in the first layer wiring process, and the first conductive path 15 is formed to extend from the first electrode 16 to apply the potential of one end of the resistance region 12. After that, a second insulating film 18 is formed, and the first insulating film 18 is formed.
A second conductive path 19 is formed on the conductive path 15 with a second insulating film 18 interposed therebetween.
本発明の最も特徴とする点は、第１の絶縁膜１
４上に第１の導電路１５を配設し、この第１の導
電路１５の上に第２の絶縁膜１８をはさんで第２
の導電路１９を配設した点にある。そして第１の
導電路１５には抵抗領域１２のどちらか一端の電
位を印加して薄い第１の絶縁膜１４でも絶縁破壊
が生じないようにしてある。 The most characteristic feature of the present invention is that the first insulating film 1
A first conductive path 15 is provided on the first conductive path 15, and a second insulating film 18 is sandwiched between the first conductive path 15 and the second conductive path 15.
The point is that a conductive path 19 is provided. The potential of either end of the resistance region 12 is applied to the first conductive path 15 so that dielectric breakdown does not occur even in the thin first insulating film 14.
この構造によれば、抵抗領域１２は第１の導電
路１５により保護されるので第２の導電路１９と
抵抗領域１２との短絡事故を未然に防ぐことがで
きる。また薄い第１の絶縁膜１４によつて形成さ
れる溝は第１の導電路で埋没させられるので、こ
の上に形成した第２の絶縁膜１８は前記溝内を直
接被覆したものより良好な絶縁性を有し、第１の
導電路１５と第２の導電路１９とが短絡すること
もない。従つて本発明によれば、抵抗領域１２と
の電位差が大になるような第２の導電路１９、例
えば電源電圧用の配線等であつても短絡すること
のない装置が実現できる。 According to this structure, since the resistance region 12 is protected by the first conductive path 15, a short circuit accident between the second conductive path 19 and the resistance region 12 can be prevented. Furthermore, since the trench formed by the thin first insulating film 14 is buried with the first conductive path, the second insulating film 18 formed thereon is better than one that directly covers the inside of the trench. It has an insulating property, and the first conductive path 15 and the second conductive path 19 will not be short-circuited. Therefore, according to the present invention, it is possible to realize a device that will not be short-circuited even if the second conductive path 19 has a large potential difference with the resistance region 12, such as a wiring for a power supply voltage.
(ト) 発明の効果
以上説明した如く、本発明によれば抵抗領域１
２と第２の導電路１９との短絡事故を未然に防げ
るという利点を有する。また電源電位等の配線で
も抵抗領域１２上に配設することが可能になるの
で、配線設計が非常に容易になり、且つ余分な配
線に要する面積が必要なくなるので、チツプ面積
を縮小できるという利点をも有する。そして本発
明は何ら付加的工程を要せず即実施可であるとい
う利点をも有する。(g) Effects of the invention As explained above, according to the present invention, the resistance region 1
This has the advantage that a short circuit accident between the conductive path 2 and the second conductive path 19 can be prevented. In addition, since wiring for power supply potential etc. can be arranged on the resistance region 12, wiring design becomes extremely easy, and additional area required for extra wiring is not required, so the chip area can be reduced. It also has The present invention also has the advantage that it can be implemented immediately without requiring any additional steps.
第１乃至第３図は各々本発明を説明するための
断面図、断面図、平面図、第４図及び第５図は従
来例を説明するための断面図である。
１１はＰ型半導体基体、１２は抵抗領域、１４
は第１の絶縁膜、１５は第１の導電路、１６，１
７は第１、第２の電極、１８は層間絶縁膜、１９
は第２の導電路である。
1 to 3 are a sectional view, a sectional view, and a plan view for explaining the present invention, and FIGS. 4 and 5 are sectional views for explaining a conventional example. 11 is a P-type semiconductor substrate, 12 is a resistance region, 14
is the first insulating film, 15 is the first conductive path, 16,1
7 is the first and second electrodes, 18 is an interlayer insulating film, 19
is the second conductive path.
Claims (1)
を有した半導体集積回路装置であつて、 半導体基板と、 この半導体基板上に形成された厚い絶縁膜と、 前記イオン注入法により、前記厚い絶縁膜に囲
まれ且つこの厚い絶縁膜よりも薄く形成されるこ
とで溝を成す第１の絶縁膜と、 この第１の絶縁膜下の半導体基板内にイオン注
入法で形成された抵抗領域と、 この抵抗領域の両端に形成されたコンタクト領
域から前記厚い絶縁膜に延在された第１の電極お
よび第２の電極と、 前記溝を埋めるため、前記第１の電極から一体
で延在された第１の導電路と、 少なくともこの第１の導電路上に形成された第
２の絶縁膜と、 前記抵抗領域上の前記第２の絶縁膜上に設けた
第２の導電路とを具備することを特徴とした半導
体集積回路装置。[Scope of Claims] 1. A semiconductor integrated circuit device having a resistance region formed by ion implantation in a semiconductor substrate, comprising: a semiconductor substrate; a thick insulating film formed on the semiconductor substrate; , a first insulating film surrounded by the thick insulating film and formed thinner than the thick insulating film to form a groove, and a first insulating film formed by ion implantation in the semiconductor substrate under the first insulating film a resistive region; a first electrode and a second electrode extending from contact regions formed at both ends of the resistive region to the thick insulating film; and integrally extending from the first electrode to fill the groove. an extended first conductive path; a second insulating film formed at least on the first conductive path; and a second conductive path provided on the second insulating film on the resistance region. A semiconductor integrated circuit device comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28832885A JPS62295445A (en) | 1985-12-20 | 1985-12-20 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28832885A JPS62295445A (en) | 1985-12-20 | 1985-12-20 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62295445A JPS62295445A (en) | 1987-12-22 |
| JPH0514429B2 true JPH0514429B2 (en) | 1993-02-25 |
Family
ID=17728758
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28832885A Granted JPS62295445A (en) | 1985-12-20 | 1985-12-20 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62295445A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7439146B1 (en) * | 2000-08-30 | 2008-10-21 | Agere Systems Inc. | Field plated resistor with enhanced routing area thereover |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55162255A (en) * | 1979-06-04 | 1980-12-17 | Hitachi Ltd | High voltage resistance resistor element |
| JPS56133863A (en) * | 1980-03-22 | 1981-10-20 | Citizen Watch Co Ltd | Semiconductor device |
-
1985
- 1985-12-20 JP JP28832885A patent/JPS62295445A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55162255A (en) * | 1979-06-04 | 1980-12-17 | Hitachi Ltd | High voltage resistance resistor element |
| JPS56133863A (en) * | 1980-03-22 | 1981-10-20 | Citizen Watch Co Ltd | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62295445A (en) | 1987-12-22 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |