JPH0344063A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0344063A JPH0344063A JP17950089A JP17950089A JPH0344063A JP H0344063 A JPH0344063 A JP H0344063A JP 17950089 A JP17950089 A JP 17950089A JP 17950089 A JP17950089 A JP 17950089A JP H0344063 A JPH0344063 A JP H0344063A
- Authority
- JP
- Japan
- Prior art keywords
- metal film
- layer metal
- trimming resistor
- fusing
- active element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims abstract description 99
- 239000002184 metal Substances 0.000 claims abstract description 99
- 238000009966 trimming Methods 0.000 claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 230000002411 adverse Effects 0.000 abstract description 9
- 238000011109 contamination Methods 0.000 abstract 2
- 239000010408 film Substances 0.000 description 100
- 239000010410 layer Substances 0.000 description 44
- 150000002500 ions Chemical class 0.000 description 13
- 230000000694 effects Effects 0.000 description 10
- 239000000356 contaminant Substances 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 7
- 230000010354 integration Effects 0.000 description 5
- 239000006185 dispersion Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910001431 copper ion Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910001414 potassium ion Inorganic materials 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910001415 sodium ion Inorganic materials 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は、半導体装置に関し、特にトリミング抵抗内蔵
′１′導体装置に係る。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a semiconductor device, and more particularly to a '1' conductor device with a built-in trimming resistor.
〈従来技術〉
第５図は従来のトリミング抵抗を有する半導体装置の要
部概略平面図である。<Prior Art> FIG. 5 is a schematic plan view of a main part of a semiconductor device having a conventional trimming resistor.
従来の電流溶断法によるトリミングの一例を第５図に基
づいて説明すると、電流溶断部ｌは、層目金属膜または
二層目金属膜によって形成されており、トリミング抵抗
４と並列に配置されている。そして、トリミング抵抗４
が適当な抵抗値となるよう、例えばＡ−Ｂ間に過大な電
流を流して溶断部１を溶断することによって、抵抗４ａ
、パッド３ ａ、 ３ ｂ、 ３ ｃを通る回路を構威
し、抵抗値の修正を行なっていた。An example of trimming by the conventional current fusing method will be explained based on FIG. There is. And trimming resistor 4
For example, by flowing an excessive current between A and B to blow out the fusing part 1, the resistance 4a is set to have an appropriate resistance value.
, a circuit passing through pads 3a, 3b, and 3c was used to correct the resistance value.
なお、第５図中、５はコンタクト窓、６はパッド窓であ
る。In addition, in FIG. 5, 5 is a contact window, and 6 is a pad window.
〈 発明が解決しようとする課題 〉
しかし、上記の方法によると、溶断部１を電流によって
溶断する際、高温の熱が発生し、溶断部ｌの近傍の絶縁
膜中、または絶縁膜上に多量の汚染イオンが発生してし
まう。この汚染イオンとしては、例えばナトリウムイオ
ンやカリウムイオン等のアルカリイオン、または銅イオ
ン等の金属イオンが知られている。こうした汚染イオン
が絶縁膜中また（Ｊ絶縁膜上を移動すること、および溶
断部Ｉの金属膜の発散が近傍の素子へ悪影響を与え、素
子の電気特性、信頼性を著しく低下させ−ていた。<Problems to be Solved by the Invention> However, according to the above method, when the fusing part 1 is fused with an electric current, high-temperature heat is generated, and a large amount of heat is generated in or on the insulating film near the fusing part l. of contaminating ions are generated. Known examples of these contaminating ions include alkali ions such as sodium ions and potassium ions, and metal ions such as copper ions. The movement of these contaminant ions into the insulating film (J) and the dispersion of the metal film at the fused portion I had an adverse effect on nearby devices, significantly reducing the electrical characteristics and reliability of the device. .
このノコめ、溶断部Ｉから素子を十分に遠ざけて設（Ｊ
ろ必要があり、高集積化の障書どなっていた。This saw is installed with the element sufficiently far away from the fusing part I (J
This was an obstacle to higher integration.
そこで、本発明は、−」二足課題に鑑み、多層金属膜配
線の溶断時に発生する電荷や汚染イオンによる溶断部近
傍の素子への悪影響を防止することができ、素子の信頼
性の向上、素子の高集積化に貢献する半導体装置の提供
を目的とする。SUMMARY OF THE INVENTION In view of the two problems, the present invention is capable of preventing the adverse effects of electric charges and contaminant ions generated when a multilayer metal film wiring is fused on the elements near the fused part, improving the reliability of the element; The aim is to provide semiconductor devices that contribute to higher integration of elements.
く 課題を解決するための手段 〉
本発明による課題解決手段は、第１図ないし第４図の如
く、半導体基板１０中に能動素子１１とトリミンク抵抗
１２とが組み込まれ、該能動素子＋１とトリミング抵抗
１２とが二層目金属膜Ｉ３と二層目金属膜Ｉ４とで結線
された半導体装置において、前記能動素子１１と二層目
金属膜上４の溶断部Ｉ６との間およびトリミング抵抗１
２と二層１」金ｆｉｌ膜１４の溶断部１６との間に、−
層ｌ」金属膜１３と二層目金属膜１７Ｉとを導通させる
ための導通窓１７ａ、１７ｂが夫々形成され、前記二層
目金属膜１４で溶断部１６また（よその近傍の能動素子
１１およびトリミング抵抗１２が被覆され、該二層目金
属膜Ｉ４の電位がグランド電位または定電位に設定され
たしのである。Means for Solving the Problems> As shown in FIGS. 1 to 4, the means for solving the problems according to the present invention includes an active element 11 and a trimming resistor 12 incorporated in a semiconductor substrate 10, and a trimming resistor 12 and an active element +1. In a semiconductor device in which a resistor 12 is connected by a second metal film I3 and a second metal film I4, the trimming resistor 1
2 and the fusing part 16 of the two-layer 1'' gold film 14, -
Conductive windows 17a and 17b are respectively formed to conduct the layer 1'' metal film 13 and the second layer metal film 17I. The trimming resistor 12 is coated, and the potential of the second metal film I4 is set to the ground potential or constant potential.
〈作用〉
」二足課題解決手段において、半導体基板１０中に組み
込まれた能動素子１１やトリミング抵抗Ｉ２を配線する
よう二層目金属膜１３を形成し、層目金属膜１３の形成
後、一層目金属膜１３と二層目金属膜１４とを導通させ
たい部分、ずなわち能動素子１１と二層目金属膜１４の
溶断部１６となる部分との間およびｌ・リミング抵抗１
２と溶断部１６となる部分との間に窓開（づを施して導
通窓１７ａ、Ｉ７ｂを形成し、溶断部１６の近傍の能動
素子１１およびトリミング抵抗１２」二に二層目金属膜
１４を形成する。これにより、一層目金属膜１３と二層
目金属膜１４と（ま導通窓１７ａ、＋７ｂて導通されろ
。このとき、二層目金属膜１４の屯位は、クランド電位
または定電位に設定される。<Function> In the two-pronged problem solving means, the second layer metal film 13 is formed to wire the active element 11 and the trimming resistor I2 incorporated in the semiconductor substrate 10, and after the formation of the second layer metal film 13, the first layer metal film 13 is formed. The part where the metal film 13 and the second metal film 14 are to be electrically connected, that is, the part between the active element 11 and the part of the second metal film 14 that will become the fusing part 16, and the rimming resistor 1.
2 and the part that will become the fusing part 16 to form conduction windows 17a and I7b, and the active element 11 and trimming resistor 12 in the vicinity of the fusing part 16 and the second layer metal film 14. As a result, conduction is established between the first metal film 13 and the second metal film 14 (through the conduction windows 17a and +7b. At this time, the level of the second metal film 14 is at the ground potential or constant set to potential.
そして、ｌ・リミング時に二層目金属膜１４の溶断部１
６に過大な電流を流す、あるいはレーザー光を照射して
溶断部１６を溶断してトリミング抵抗Ｉ２の抵抗値が調
整される。この溶断の際、高温の熱が発生し、溶断部１
６の近傍の絶縁膜中、または絶縁膜上に多量のイオンが
発生ずる。この汚染イオンは絶縁膜中または絶縁膜上を
移動し、また溶断部１６の金属膜の発散が近傍の能動素
子１１およびトリミング抵抗１２へ悪影響を与え、能動
素子１１および）・リミング抵抗１２の電気特性、信頼
性を著しく低下させる場合がある。Then, during rimming, the fusing portion 1 of the second layer metal film 14 is
The resistance value of the trimming resistor I2 is adjusted by passing an excessive current through the trimming resistor I2 or by irradiating the cutout portion 16 with a laser beam. During this fusing, high-temperature heat is generated, and the fusing part 1
A large amount of ions are generated in or on the insulating film near 6. These contaminant ions move in or on the insulating film, and the dispersion of the metal film in the fusing part 16 has an adverse effect on the nearby active element 11 and trimming resistor 12. Characteristics and reliability may be significantly deteriorated.
しかし、一層目金属膜１３と二層目金属膜１４との導通
を図るための導通窓１７ａ、１７ｂを能動素子１１と二
層目金属膜Ｉ４の溶断部Ｉ６との間お上びｌ・リミング
抵抗１１と二層目金属膜１４の溶断部１６との間に設け
、二層目金属膜１４で溶断部１６の近傍の能動素子１．
１およびトリミング抵抗１２を被覆しているので、溶断
部１６とその近傍の能動素子１１およびトリミング抵抗
１２の素子を遮蔽することかできる。However, the conduction windows 17a and 17b for establishing electrical conduction between the first metal film 13 and the second metal film 14 are placed between the active element 11 and the fusing portion I6 of the second metal film I4. The active element 1. is provided between the resistor 11 and the fusing part 16 of the second metal film 14, and the active element 1.
1 and the trimming resistor 12, the fusing portion 16 and the active element 11 and trimming resistor 12 in the vicinity thereof can be shielded.
また、二層目金属膜Ｉ４の電位をグランド電位または定
電位に設定しているので、電荷が外部に流出される。Furthermore, since the potential of the second layer metal film I4 is set to a ground potential or a constant potential, charges are leaked to the outside.
したがって、金属膜配線の溶断時に発生ずる電荷や汚染
イオンによる溶断部近傍の素子への悪影響を防止するこ
とができ、素子の信頼性の向」二、素子の高集積化に貢
献することができる。Therefore, it is possible to prevent the charge and contaminant ions generated when the metal film wiring is fused from having an adverse effect on the elements near the fused part, which contributes to improving the reliability of the elements and increasing the integration of the elements. .
〈実施例〉
以下、本発明の一実施例を第１図ないし第３図に基づい
て説明する。<Example> Hereinafter, an example of the present invention will be described based on FIGS. 1 to 3.
第１図は本発明の一実施例を示す半導体装置の要部概略
平面図、第２図は第１図のＣ−Ｃ部分の断面図、第３図
は同じくその製造Ｉ：程を示す図である。FIG. 1 is a schematic plan view of the main parts of a semiconductor device showing an embodiment of the present invention, FIG. 2 is a sectional view taken along the line C-C in FIG. 1, and FIG. 3 is a diagram showing the manufacturing process thereof. It is.
図示の如く、本実施例のトリミング抵抗内蔵半導体装置
は、半導体基板１０中に能動素子（トランジスタ）１１
とトリミング抵抗１２とが組み込まれ、該能動素子ＩＩ
とトリミング抵抗１２とがトリミング時に二層目金属膜
１３と二層目金属膜１４とて結線されている。As shown in the figure, the semiconductor device with a built-in trimming resistor of this embodiment has an active element (transistor) 11 in a semiconductor substrate 10.
and a trimming resistor 12 are incorporated, and the active element II
and the trimming resistor 12 are connected through the second metal film 13 and the second metal film 14 during trimming.
そして、前記能動素子１１と二層目金属膜１４の溶断部
１６との間、およびトリミング抵抗１２と二層目金属膜
１４の溶断部１６との間に、後述の眉間絶縁膜２１で絶
縁された二層目金属膜１３と二層目金属膜１４とを導通
させるための導通窓１７ａ、１７ｂが形成され、前記二
層目金属膜１４で溶断部１６の近傍の能動素子１１およ
びトリミング抵抗Ｉ２が被覆され、該二層目金属膜１４
の電（ｈ−がグランド電位または定電位となるよう設定
されている。Insulation is provided between the active element 11 and the fusing part 16 of the second metal film 14, and between the trimming resistor 12 and the fusing part 16 of the second metal film 14, by an insulating film 21 between the eyebrows, which will be described later. Conductive windows 17a and 17b are formed for electrically connecting the second layer metal film 13 and the second layer metal film 14, and the active element 11 and trimming resistor I2 near the fusing part 16 are formed in the second layer metal film 14. is coated, and the second layer metal film 14
The voltage (h-) is set to be the ground potential or constant potential.
前記半導体基板ＩＯは、第２図の如く、Ｐ形の基板上に
エピタキシャルＮ形層を成長させておき、これに表面か
ら必要に応じてＰ、Ｎ層を拡散させてトランジスタ１１
、トリミング抵抗１２等の回路素子が組み込まれている
。該トランジスタ１１およびトリミング抵抗１２等の回
路素子を分離絶縁するために、Ｐ＋層を表面から基板の
Ｐ層に届くまで拡散させているので、トランジスタ１１
およびトリミング抵抗Ｉ２の周囲はｐ４層の壁で囲まれ
ている。As shown in FIG. 2, the semiconductor substrate IO is made by growing an epitaxial N-type layer on a P-type substrate, and diffusing the P and N layers from the surface as necessary to form the transistor 11.
, a trimming resistor 12, and other circuit elements are incorporated therein. In order to isolate and insulate circuit elements such as the transistor 11 and the trimming resistor 12, the P+ layer is diffused from the surface to the P layer of the substrate.
The trimming resistor I2 is surrounded by a p4 layer wall.
前記トランジスタＩＩは、第１図の如く、二層目金属膜
１４の溶断部１６を挾んてトリミング抵抗１２と平行に
配置されており、複数の抵抗素子を有している。As shown in FIG. 1, the transistor II is arranged parallel to the trimming resistor 12 across the fusing portion 16 of the second metal film 14, and has a plurality of resistor elements.
そして、トランジスタ＋１よびトリミング抵抗１２の表
面には、第２図の如く、５ｉＯｐ等に上りフィールド絶
縁膜１８が被覆形成されており、これによりトランジス
タ１１およびトリミング抵抗１２の表面状態の変化によ
る特性の変化を制御し、表面に発生ずる雑音簀を小さく
している。なお、トランジスタ１１およびトリミング抵
抗Ｉ２には、コンタクト窓１９が設けられている。As shown in FIG. 2, the surfaces of the transistor +1 and the trimming resistor 12 are coated with an upward field insulating film 18 such as 5iOp, which allows the characteristics of the transistor 11 and the trimming resistor 12 to change due to changes in their surface conditions. It controls the changes and reduces the amount of noise generated on the surface. Note that a contact window 19 is provided in the transistor 11 and the trimming resistor I2.
前記一層目金属膜１３は、第１．２図の如く、）・ラン
ジスタ１１およびトリミング抵抗１２等の回路素子を結
線するようフィールド絶縁膜１８」二にＡＱ蒸着等によ
り薄膜形成されており、また、一層目金属膜■３は導通
窓１７ａ、＋７ｂの下側にも形成されている。そして、
該一層目金属膜１３の表面には、二層目金属膜Ｉ４との
層間絶縁を図るために８１０２等により層間絶縁膜２１
が被覆形成されている。The first layer metal film 13 is formed as a thin film by AQ evaporation or the like on the field insulating film 18 to connect circuit elements such as the transistor 11 and the trimming resistor 12, as shown in FIG. , the first layer metal film 3 is also formed on the lower side of the conduction windows 17a and +7b. and,
An interlayer insulating film 21 is formed on the surface of the first metal film 13 using 8102 or the like in order to achieve interlayer insulation with the second metal film I4.
is coated.
前記二層目金属膜１４は、第２図の如く、層間絶縁膜２
１上にＡＣ蒸着等により薄膜形成されて１ｊす、該二層
目金属膜Ｉ４の表面は、保護樹脂により表面保護膜２２
が被覆形成されている。The second layer metal film 14 is, as shown in FIG.
A thin film 1j is formed on the second layer metal film 1j by AC vapor deposition or the like, and the surface of the second metal film 14 is covered with a surface protective film 22 made of a protective resin.
is coated.
前記溶断部１６は、第１．２図の如く、二層目金属膜１
４で形成されており、トリミング抵抗１２と並列に配置
されている。なお、溶断部Ｉ６には、パッド窓２０が接
続されている。As shown in FIG. 1.2, the fusing portion 16
4, and is arranged in parallel with the trimming resistor 12. Note that a pad window 20 is connected to the fusing portion I6.
前記導通窓１７ａ、＋７ｂは、第３図の如く、層目金属
膜１３」二に層間絶縁膜２Ｉを形成した後、一層目金属
膜Ｉ３と二層目金属膜１４とを導通させたい部分、すな
わちトランジスタ１１と溶断部１６との間およびトリミ
ンク抵抗１２と溶断部１６との間に窓開（′Ｊして形成
されており、該導通窓１７ａ、１７ｂで二層目金属膜１
３二層目金属膜１４とを導通させている。As shown in FIG. 3, the conduction windows 17a and +7b are the portions where the first metal film I3 and the second metal film 14 are to be electrically connected after the interlayer insulating film 2I is formed on the second metal film 13. That is, windows are formed between the transistor 11 and the fusing part 16 and between the trimming resistor 12 and the fusing part 16, and the second layer metal film 1 is formed in the conduction windows 17a and 17b.
It is electrically connected to the third second layer metal film 14.
そして、トランジスタ１１例の導通窓１７ａは、第１図
の如く、トランジスタ１１と平行に溶断部１６の並列方
向を長手方向とずろ長寸法の短冊形孔とされている。一
方、トリミング抵抗１２側の導通窓１７ｂは、短寸法の
短冊形孔としてトリミング抵抗１２ど平行に複数個（二
個）配されている。As shown in FIG. 1, the conduction window 17a of the transistor 11 is formed into a rectangular hole parallel to the transistor 11 with the parallel direction of the fusing portion 16 offset from the longitudinal direction. On the other hand, a plurality (two) of conductive windows 17b on the side of the trimming resistor 12 are arranged as short rectangular holes parallel to the trimming resistor 12.
上記半導体装置の製造方法を第３図に基づいて説明する
。A method for manufacturing the above semiconductor device will be explained based on FIG. 3.
まず、半導体基板１０中に組み込まれたトランジスタ１
１やトリミング抵抗１２等の回路素子の表面に５ｉＯｚ
等によりフィールド絶縁膜１８を形成し、フィールド絶
縁膜１８」二にＡＱ蒸着等に上り）・ランノスタ１１お
よびトリミング抵抗１２等の回路素子を結線するよう二
層目金属膜１３を形成する。First, a transistor 1 incorporated in a semiconductor substrate 10
5iOz on the surface of circuit elements such as 1 and trimming resistor 12.
The field insulating film 18 is then formed by AQ evaporation, etc.) and the second metal film 13 is formed to connect the circuit elements such as the lannostar 11 and the trimming resistor 12.
そして、一層目金属膜１３の形成後、一層目金属膜１３
と二層目金属膜１４との層間絶縁をするために５ｉＯｐ
等により層間絶縁膜２１を形成する。After forming the first metal film 13, the first metal film 13 is
5iOp to provide interlayer insulation between the metal film 14 and the second metal film 14.
The interlayer insulating film 21 is formed by et al.
つづいて、層間絶縁膜２１−Ｌにおいて、一層目金属膜
１３と二層目金属膜Ｉ４とを導通させたい部分、すなわ
ちトランジスタ１１と二層目金属膜１４の溶断部１６と
なる部分との間、およびトリミング抵抗１２と溶断部Ｉ
６となる部分との間に、窓開けを施して導通窓１７ａ、
Ｉ７ｂを形成する。Next, in the interlayer insulating film 21-L, a portion where the first layer metal film 13 and the second layer metal film I4 are desired to be electrically connected, that is, a portion between the transistor 11 and the portion of the second layer metal film 14 that will become the fused portion 16. , and the trimming resistor 12 and the fusing part I
A conductive window 17a is made by opening a window between the part 6 and the part 6.
Form I7b.
次に、二層目金属膜１４の溶断部１６とその近傍のトラ
ンジスタ１１およびトリミング抵抗１２の層間絶縁膜２
１」二にＡＣ蒸着等により二層目金属膜１４を形成する
。Next, the interlayer insulating film 2 of the fused portion 16 of the second layer metal film 14 and the transistor 11 and trimming resistor 12 in the vicinity thereof is
1) Second, a second layer metal film 14 is formed by AC vapor deposition or the like.
しかる後、二層目金属膜１４上に表面保護膜２２が形成
される。Thereafter, a surface protection film 22 is formed on the second layer metal film 14.
このように製造された半導体装置は、そのトリミング時
に二層目金属膜Ｉ４の溶断部１６に過大な電流を流す、
あるいはレーザー光を照射して溶断部１６を溶断してト
リミング抵抗Ｉ２の抵抗値が調整される。In the semiconductor device manufactured in this way, an excessive current is passed through the fusing portion 16 of the second layer metal film I4 during trimming.
Alternatively, the resistance value of the trimming resistor I2 is adjusted by irradiating laser light to fuse the fusing portion 16.
この溶断の際、高温の熱が発生し、溶断部１６の近傍の
絶縁膜中、または絶縁膜上に多量のイオンが発生ずる。At the time of this fusing, high temperature heat is generated and a large amount of ions are generated in or on the insulating film near the fusing part 16.
この汚染イオンは絶縁膜中または絶縁膜上を移動し、ま
た溶断部１６の金属膜の発散が近傍のトランジスタ１１
およびトリミング抵抗Ｉ２へ悪影響を与え、トランジス
タ１１およびトリミング抵抗１２の電気特性、信頼性を
著しく低下させる場合がある。These contaminant ions move in or on the insulating film, and the dispersion of the metal film at the fused portion 16 causes the nearby transistor 11
This may have an adverse effect on the trimming resistor I2, and may significantly deteriorate the electrical characteristics and reliability of the transistor 11 and the trimming resistor 12.
しかし、本実施例では、一層目金属膜１３と二層目金属
膜１４との導通を図るための導通窓１７ａ、１７ｂをト
ランジスタ１１と二層目金属膜１４の溶断部１６との間
、およびトリミング抵抗１１と二層目金属膜１４の溶断
部１６との間に設け、二層目金属膜１４で二層目金属膜
１４の溶断部１６の近傍のトランジスタ１１お上びトリ
ミング抵抗１２とを被覆しているのて、溶断部１６に対
してその近傍のトランジスタ１１およびトリミング抵抗
１２の素子を遮蔽することができる。However, in this embodiment, the conduction windows 17a and 17b for establishing electrical conduction between the first metal film 13 and the second metal film 14 are provided between the transistor 11 and the fusing portion 16 of the second metal film 14, and It is provided between the trimming resistor 11 and the fusing part 16 of the second metal film 14, and the second metal film 14 connects the transistor 11 and the trimming resistor 12 near the fusing part 16 of the second metal film 14. Because of the covering, the elements of the transistor 11 and trimming resistor 12 in the vicinity of the fusing portion 16 can be shielded.
また、二層目金属膜１４の電位をグランド電位または定
電位に設定しているので、電荷が外部に流出される。Furthermore, since the potential of the second layer metal film 14 is set to a ground potential or a constant potential, charges are leaked to the outside.
したがって、金属膜配線の溶断時に発生ずる重荷や汚染
イオンによる溶断部近傍の素子への悪影響を防止するこ
とができ、素子の信頼性の向上、素子の高集積化に貢献
することができる。Therefore, it is possible to prevent the adverse effects of the heavy load and contaminant ions generated when the metal film wiring is fused on the elements near the fused part, contributing to improved reliability of the element and higher integration of the element.
なお、本発明は、上記実施例に限定されるものではなく
、本発明の範囲内で上記実施例に多くの１−
修正および変更を加え得ることは勿論である。It should be noted that the present invention is not limited to the above embodiments, and it goes without saying that many modifications and changes can be made to the above embodiments within the scope of the present invention.
例えば、」二足実施例では、素子部を二層目金属膜で被
覆しているが、溶断部のみを多層金属膜で被覆する構成
としても良い。For example, in the two-legged embodiment, the element portion is covered with a second layer metal film, but a structure may be adopted in which only the fusing portion is covered with a multilayer metal film.
また、第４図の如く、溶断部を二層目金属膜で形成して
も良く、この場合、二層目金属膜は溶断部を被覆してい
るが、近傍の素子側を被覆してもよい。また、溶断時に
フィールド絶縁膜中に発生する汚染イオンや電荷を遮断
するには、一層目金属膜とコンタクトを取るコンタクト
窓を設けておくとその効果は大きくなる。Further, as shown in FIG. 4, the fusing part may be formed by a second layer metal film. In this case, the second layer metal film covers the fusing part, but it may also cover the nearby element side. good. Furthermore, in order to block contaminant ions and charges generated in the field insulating film during blowout, the effect will be greater if a contact window is provided to make contact with the first layer metal film.
〈発明の効果〉
以上の説明から明らかな通り、本発明によると、一層目
金属膜と二層目金属膜との導通を図るための導通窓を能
動素子と二層目金属膜の溶断部との間およびトリミング
抵抗と二層目金属膜の溶断部との間に設け、二層目金属
膜で溶断部の近傍の能動素子およびトリミング抵抗を被
覆しているので、溶断部に対してその近傍の能動素子お
よびトリミング抵抗の素子を遮蔽することができる。<Effects of the Invention> As is clear from the above description, according to the present invention, the conduction window for establishing electrical conduction between the first layer metal film and the second layer metal film is connected to the active element and the fusing portion of the second layer metal film. and between the trimming resistor and the fusing part of the second-layer metal film, and the second-layer metal film covers the active element and trimming resistor near the fusing part, so that active elements and elements of the trimming resistor can be shielded.
また、二層目金属膜の電位をグランド電位または定電位
に設定しているので、電荷が外部に流出される。Furthermore, since the potential of the second layer metal film is set to a ground potential or a constant potential, charges are leaked to the outside.
したがって、金属膜配線の溶断時に発生ずる電荷や汚染
イオンによる溶断部近傍の素子への悪影響を防止するこ
とができ、素子の信頼性の向４二、素子の高集積化に貢
献することができるといった優れた効果がある。Therefore, it is possible to prevent the charge and contaminant ions generated when the metal film wiring is fused from having an adverse effect on the elements near the fused part, contributing to improved reliability of the elements and higher integration of the elements. It has such excellent effects.
第】図は本発明の一実施例を示す半導体装置の要部概略
平面図、第２図は第１図のＣ−Ｃ部分の断面図、第３図
は同じくその製造工程を示す図、第４図は本発明の他の
実施例を示ず半導体装置の断面図、第５図は従来の半導
体装置の平面図である。
ＩＯ二半導体基板、１ｊ：能動素子（トランジスタ）、
１２．トリミング抵抗、１３ニ一層目金属膜、Ｉ４・二
層目金属膜、Ｉ６溶断部、１７ａ、＋７ｂ導通窓。1 is a schematic plan view of the main parts of a semiconductor device showing an embodiment of the present invention, FIG. 2 is a sectional view taken along the line CC in FIG. 1, FIG. FIG. 4 is a sectional view of a semiconductor device, not showing another embodiment of the present invention, and FIG. 5 is a plan view of a conventional semiconductor device. IO2 semiconductor substrate, 1j: active element (transistor),
12. Trimming resistor, 13th first layer metal film, I4 second layer metal film, I6 fusing part, 17a, +7b conduction window.
Claims (1)
れ、該能動素子とトリミング抵抗とが一層目金属膜と二
層目金属膜とで結線された半導体装置において、前記能
動素子と金属膜配線の溶断部との間およびトリミング抵
抗と金属膜配線の溶断部との間に、一層目金属膜と二層
目金属膜とを導通させるための導通窓が形成され、前記
二層目金属膜で金属膜配線の溶断部またはその近傍の能
動素子およびトリミング抵抗が被覆され、該二層目金属
膜の電位がグランド電位または定電位に設定されたこと
を特徴とする半導体装置。In a semiconductor device in which an active element and a trimming resistor are incorporated in a semiconductor substrate, and the active element and the trimming resistor are connected by a first layer metal film and a second layer metal film, fusing of the active element and the metal film wiring is performed. A conduction window is formed between the trimming resistor and the fusing portion of the metal film wiring to conduct the first layer metal film and the second layer metal film, and the second layer metal film connects the metal film with the metal film wiring. 1. A semiconductor device, wherein an active element and a trimming resistor at or near a fused portion of a wiring are coated, and a potential of the second layer metal film is set to a ground potential or a constant potential.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1179500A JP2532944B2 (en) | 1989-07-11 | 1989-07-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1179500A JP2532944B2 (en) | 1989-07-11 | 1989-07-11 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0344063A true JPH0344063A (en) | 1991-02-25 |
| JP2532944B2 JP2532944B2 (en) | 1996-09-11 |
Family
ID=16066906
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1179500A Expired - Fee Related JP2532944B2 (en) | 1989-07-11 | 1989-07-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2532944B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005039220A (en) * | 2003-06-26 | 2005-02-10 | Nec Electronics Corp | Semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5814561A (en) * | 1981-07-17 | 1983-01-27 | Nec Corp | Passive element for trimming |
| JPS5863148A (en) * | 1981-10-09 | 1983-04-14 | Toshiba Corp | Semiconductor device |
| JPS61134053A (en) * | 1984-12-04 | 1986-06-21 | Nec Corp | Semiconductor ic device |
-
1989
- 1989-07-11 JP JP1179500A patent/JP2532944B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5814561A (en) * | 1981-07-17 | 1983-01-27 | Nec Corp | Passive element for trimming |
| JPS5863148A (en) * | 1981-10-09 | 1983-04-14 | Toshiba Corp | Semiconductor device |
| JPS61134053A (en) * | 1984-12-04 | 1986-06-21 | Nec Corp | Semiconductor ic device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005039220A (en) * | 2003-06-26 | 2005-02-10 | Nec Electronics Corp | Semiconductor device |
| US7795699B2 (en) | 2003-06-26 | 2010-09-14 | Nec Electronics Corporation | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2532944B2 (en) | 1996-09-11 |
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