JPS5814561A - Passive element for trimming - Google Patents

Passive element for trimming

Info

Publication number
JPS5814561A
JPS5814561A JP11194881A JP11194881A JPS5814561A JP S5814561 A JPS5814561 A JP S5814561A JP 11194881 A JP11194881 A JP 11194881A JP 11194881 A JP11194881 A JP 11194881A JP S5814561 A JPS5814561 A JP S5814561A
Authority
JP
Japan
Prior art keywords
oxide film
film
capacitor
trimming
subjected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11194881A
Other languages
Japanese (ja)
Inventor
Koichiro Misaki
見崎 光一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11194881A priority Critical patent/JPS5814561A/en
Publication of JPS5814561A publication Critical patent/JPS5814561A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent a trimmer part from breakdown by a method wherein a narrow stripe shaped polycrystalline Si layer is mounted on an oxide film covering a diffused region, subjected to heat treatment for the superficial part thereof to be transformed into SiO2 to work as a mask in a process of providing a window in the oxide film, and an electrode is connected to the diffused region, when an electrode is attached to a diffused region. CONSTITUTION:An N-type semiconductor substrate 101 provided with an N<+> type diffused region 102 is covered with an oxide film 103 and then with a polycrystalline Si layer 104, and is subjected to heat treatment for the conversion of the superficial part of the layer 104 into a thin oxide film 105. Next, the film 105 is subjected to photoetching and, with the film 105 as it is, the layer 104 is subjected to plasma etching, for the formation of a narrow polycrystalline Si stripe 106, in which process the stripe 106 is overetched so that an eaves like narrow oxide film stripe 107 remains of the film 105 to cap the narrow stripe 106. Next, the film 103 on the region 102 is subjected to etching and then to heat treatment, for the formation of a capacitor oxide film 108 and a capacitor trimming oxide film 109 of the same thickness. The film 103 is then provided with a window, and an Al wiring 111 to be an end of the capacitor is attached to the region 102.

Description

【発明の詳細な説明】 本発明はトリミング容易な抵抗、コンデンサなどの受動
素子に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to passive elements such as resistors and capacitors that can be easily trimmed.

抵抗、コンデンサなどのトリミング方法には、レーザー
トリミング、ツェナー破壊トリセング。
Trimming methods for resistors, capacitors, etc. include laser trimming and Zener destruction trimming.

ボリシリヒ、−ズ等によるものがある。レーザートリミ
ングとポリシリヒユーズはトリミング部分の破壊の為、
信頼性上の問題が有り、レーザ) IJミングとツェナ
ー破壊トリミングは、トリミングの為の面積をある程度
必要とするという欠点があった。
There are works by Borislich, -s, etc. Laser trimming and polysilicate use destroy the trimmed part, so
There are reliability problems, laser) IJ trimming and Zener destruction trimming have the disadvantage that they require a certain amount of area for trimming.

本発明の目的は、トリミング部分の破壊が無く、しかも
トリミングの為に必要とされる面積が小さい、トリミン
グ容易な受動素子を提供するにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a passive element that is easy to trim, with no damage to the trimmed portion, and a small area required for trimming.

本発明によるトリミング−1E4:Fi、−導電型(D
半導体基板と、前記半導体基板上に形成された絶縁膜と
、該絶縁膜上に形成された上部がひさし状に張り出した
絶縁性細条と、前記絶縁膜の下で前記半導体基板上に形
成された受動素子と接続されて前記絶縁Hにあけられた
窓を通して該絶縁膜上に引出された複数の配線電極と前
記絶縁膜上にちゃかつ前記ひさし状絶縁性細条をまたぐ
ようにして、かつ、この部分で段切れを生じて前記配線
電極のうちの任意の配線電極間を接続するように設けら
れた導電性細条とを含む構成を有する。
Trimming according to the invention - 1E4: Fi, - conductivity type (D
a semiconductor substrate, an insulating film formed on the semiconductor substrate, an insulating strip formed on the insulating film whose upper part protrudes like an eave, and an insulating strip formed on the semiconductor substrate below the insulating film. a plurality of wiring electrodes connected to the passive elements formed on the insulating film and drawn out onto the insulating film through windows formed in the insulating H; , and a conductive strip provided so as to create a break at this portion and connect arbitrary wiring electrodes among the wiring electrodes.

つぎに本発明を実施例によル説明する。Next, the present invention will be explained based on examples.

第1図(a)、 (b)は、本発明の一実施例としての
M)8コンデンサについての製造工程途中の断面図であ
る。tず第1図(1)に示すように、N 拡散層(図に
は出ていない→を形成したN型半導体基板101上に酸
化膜103、酸化膜103上にポリシリコン104t−
約6000λの厚さに成長させる。ポリシリコン104
Fi酸化してポリシリコン表面に約1000λの酸化膜
105が形成される0次に、第1図(b)に示すように
、写真蝕刻法により酸化膜105tエツチングし、その
ままの状態でポリシリコン104tプラズマで工、チン
グしポリシリコン細条106’に形成する。この時、ポ
リシリコン104は少しオーバエツチングされてポリシ
リコン細条106になるが、ポリシリコン104上の酸
化膜105はポリW 13 :Iン細条106の上にあ
ってひさし状酸化膜細条107となる。つぎに第1図<
C)の平面図および、同図のA−A、B−B断面をそれ
ぞれ示す第4図(d)、(e)!−参照して、N+型型
数散層102上酸化膜103t−エツチングして後熱酸
化を施し、コンデンサ酸化膜108.)り之ング用コン
デンサ酸化膜109を形成する。この時コンデンサ酸化
膜10Bとトリミング用コンデンサ酸化膜は同時に同じ
膜厚に形成される。更に、N+型型数散層102のオー
ミックコンタクトを取る為に、酸化膜403に酸化膜窓
を空け、コンデンサの一端となるべくアル宅配線111
が形成される。コンデンサ酸化1110gはアルミ電極
11&トリミング用コンデンサ液化膜109はアルミ電
極113で覆われ、アルン電極112とアルミ電極11
3はアルミ配線114,115でそれぞれトリミング電
極116,117に接続される。又、アルミ配線114
とアルミ配線115との間をア    □ルミ配線11
Bが接続する形で形成されるが、このアルミ配線118
Fiポリシリコンm条106とその上に形成され九ひさ
し状酸化膜107を横切る為にこの部分で段切れを生じ
ている。なお、上記説明におけるアルミの膜厚は約2.
 OJImである。
FIGS. 1(a) and 1(b) are cross-sectional views during the manufacturing process of an M)8 capacitor as an embodiment of the present invention. As shown in FIG. 1 (1), an oxide film 103 is formed on an N-type semiconductor substrate 101 on which an N diffusion layer (not shown) is formed, and a polysilicon film 104 is formed on the oxide film 103.
It is grown to a thickness of about 6000λ. polysilicon 104
Fi is oxidized to form an oxide film 105 of approximately 1000λ on the surface of the polysilicon. Next, as shown in FIG. Polysilicon strips 106' are formed by plasma etching. At this time, the polysilicon 104 is slightly overetched and becomes a polysilicon strip 106, but the oxide film 105 on the polysilicon 104 is on the polyW 13 :I strip 106 and becomes an eaves-shaped oxide film strip. It becomes 107. Next, Figure 1 <
FIGS. 4(d) and 4(e) showing the plan view of C) and the AA and BB cross sections of the same figure, respectively! - Referring to the above, the oxide film 103t on the N+ type scattering layer 102 is etched and then thermally oxidized, and the capacitor oxide film 108. ) A capacitor oxide film 109 for mounting is formed. At this time, the capacitor oxide film 10B and the capacitor oxide film for trimming are simultaneously formed to have the same thickness. Furthermore, in order to make ohmic contact with the N+ type scattering layer 102, an oxide film window is formed in the oxide film 403, and an aluminum wiring 111 is formed to serve as one end of the capacitor.
is formed. Capacitor oxidation 1110g is covered with aluminum electrode 11 & capacitor liquefied film 109 for trimming is covered with aluminum electrode 113, Arun electrode 112 and aluminum electrode 11
3 are aluminum wires 114 and 115 connected to trimming electrodes 116 and 117, respectively. Also, aluminum wiring 114
Aluminum wiring 11 between and aluminum wiring 115
This aluminum wiring 118 is formed in such a way that B is connected to
In order to cross the Fi polysilicon m-strip 106 and the nine-eaves-shaped oxide film 107 formed thereon, a step is created at this portion. Note that the thickness of the aluminum film in the above explanation is approximately 2.
This is OJIm.

この様にして出来上がったMO8コンデンサ酸化膜10
8の膜厚と面積によって決まる容量値をもつが、トリミ
ング電極116,117に10V程度の電圧を印加する
ことにより、アルミ配線1180段切れ部は短絡となり
、M08コンデンナの値はコンデンサ酸化膜108によ
って決まる値にトリミング用コンデンサ酸化膜による値
を加えた値となる6段切れ部分が電圧印加により短絡と
なるのは、電界がある臨界値を越えると段切れ部分のア
ル電間隔が小さい為にアルミの原子放出が発生し、アル
しのすき間が埋まってしまうからである。
MO8 capacitor oxide film 10 completed in this way
However, by applying a voltage of about 10V to the trimming electrodes 116 and 117, the cut portion of the aluminum wiring 1180 becomes a short circuit, and the value of the M08 capacitor is determined by the capacitor oxide film 108. The reason why the 6-step cut portion, which is the determined value plus the value due to the trimming capacitor oxide film, becomes short-circuited when voltage is applied is that when the electric field exceeds a certain critical value, the aluminum conductor spacing at the step-break portion is small. This is because atomic emission occurs and the gaps between aluminum are filled.

アルこの膜厚はデバイスの特性上決足されるべきもので
あるから、ポリシリコンの膜厚を調整することにより電
界臨界値を制御できる。ポリシリコンの膜厚が約600
0λで、アルミの膜厚が約20μmの時臨界電圧値は4
.0〜9.5vであった。
Since this film thickness must be determined based on the characteristics of the device, the electric field critical value can be controlled by adjusting the polysilicon film thickness. Polysilicon film thickness is approximately 600mm
At 0λ, the critical voltage value is 4 when the aluminum film thickness is approximately 20 μm.
.. It was 0 to 9.5v.

第2図(1)は、第2の実施例としての、トリミング電
極な抵抗体の平面図、同図(b)、 (aはそれぞれ図
(a)OA−AおよびB−Bの断面図である。これらの
図において、NW牛導体基板201円KP型拡散抵抗2
21を形成し、半導体基板201上に酸化膜203t−
形成する1次に、酸化膜203上に第1図の説明と同様
にポリシリコン、酸化膜を順次成長させて、写真蝕刻法
によりポリシリコン細条208、ひさし状酸化膜細条2
09を得る。
FIG. 2 (1) is a plan view of a resistor as a trimming electrode as a second embodiment, FIG. In these figures, NW conductor board 201 yen KP type diffused resistor 2
21 is formed, and an oxide film 203t- is formed on the semiconductor substrate 201.
First, polysilicon and oxide films are sequentially grown on the oxide film 203 in the same manner as described in FIG.
Get 09.

更に、P型拡散抵抗221とのオーミックコンタクト全
敗る為に、酸化膜203に酸化膜窓を空けそれらは抵抗
体の一端となるべくアルン配線22λ抵抗体の他端とな
るべくアルζ配線223、抵抗体+2))Qtソング子
となるぺ〈アル?配置[2z4゜225.226,22
7に接続される。これらのアルさ配線224,225,
226,227の他端はそれぞれアルミ電極228,2
29,230゜231に接続され、アルミ配置224,
225゜226.227の間はアル宅配線232,23
3゜234で接続される形と力るが、これらのアル宅配
線232,233,234はポリシリコン細条208、
酸化膜細条209を横切る為、この部分−で第1図同様
アルミ配線は段切れ状態となっている。
Furthermore, in order to completely eliminate ohmic contact with the P-type diffused resistor 221, an oxide film window is formed in the oxide film 203, and these are connected to the Arun wiring 22, which will become one end of the resistor, the Alζ wiring 223, which will become the other end of the resistor, and the resistor. +2)) Peal who becomes a Qt song child. Placement [2z4゜225.226,22
Connected to 7. These aluminum wires 224, 225,
The other ends of 226 and 227 are aluminum electrodes 228 and 2, respectively.
29,230° connected to 231, aluminum arrangement 224,
Between 225° and 226.227, home wiring is 232 and 23.
Although it is said to be connected at 3°234, these aluminum wires 232, 233, 234 are connected to polysilicon strips 208,
Since it crosses the oxide film strip 209, the aluminum wiring is broken at this portion as in FIG.

この様にして出来上がった抵抗体は、アルミ電極228
.229,230,2310内二つを適mに選び、電圧
を印加することにより種kO抵抗値七得ることができる
。トリミングの臨界電圧値が小さいと)Itングに使用
出来る用途が限定されるが、ポリシリコンの膜厚を更に
厚くすることにより臨界電圧値を高くできるので高電圧
における使用も可能である。
The resistor completed in this way has an aluminum electrode 228
.. By appropriately selecting two of 229, 230, and 2310 and applying a voltage, seven types of kO resistance values can be obtained. If the critical voltage value for trimming is small, the applications that can be used for It ring are limited, but by increasing the thickness of the polysilicon film, the critical voltage value can be increased, so that it can also be used at high voltages.

以上の様にして面積を^必要としない短絡モードのトリ
ミング用抵抗またはコンデンすなどの受動素子が得られ
る。なお、上記説明ではトηンンダ用部分としてポリシ
リコンiWI化膜の組み合わせを用いた例會示したが、
これは例えば気相成長蹟化膜と窒化膜の組み合わせによ
っても得られることは言うまでもない。
In the above manner, a passive element such as a short-circuit mode trimming resistor or capacitor that does not require area can be obtained. Incidentally, in the above explanation, an example was given in which a combination of polysilicon iWI film was used as the conductor part.
Needless to say, this can also be achieved by, for example, a combination of a vapor-grown nitride film and a nitride film.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)、 (b)は本発明の一実施例のMO8コ
ンデンサの製造工程途中の断面図、第1図(clFiそ
の後の工程を径たMO8コンデンサの平面図、同図(d
)、 (e)はそれぞれ図(e)のA−&およびB−B
断面図、第2図(a)は本発明の第2実施例の平面図、
同図(b)、 (Q)はそれぞれ図(a)のA−ムおよ
びB−B断面図である。 101.201・・・・・・N′fJ牛導体基板、10
2・・・・・・N+拡散層、103,203・・・・・
・酸化膜、104゜204・・・・・・ポリシリコン、
105,205・・・・・・ポリシリコン上の酸化膜、
106,206・・・・・・ポリシリコン細条、107
,209・・・・・・ひさし状酸化膜細条、108・・
・・・・コンデンサ酸化膜、109・・・00.トリミ
ング用コンデンサ酸化膜、111・・・・・・N拡散層
に接続されるアル(配線、112・・・・・・コンデン
サ酸化膜を覆うアルミ電極、113・・・・−・トリミ
ング用コンデンサ酸化膜を覆う了ルミ電極、114.1
15・・・・・・コンデンサ酸化Ht覆うアルζ電極と
トリ々ンダ電極とを接続するアル電配線、116.11
7・・・・・・トリミング用アルミ電極、11B・・・
・・・ひさし状酸化膜細条を横切るアル電配線、221
・・・・・・P@拡散抵抗、222,223・・・・・
・抵抗体両端から出るアル電配線%224,225゜2
26.227・・・・・・トリ之ンダ用アル電配線、2
28.229,230,231・・・・・・トリミング
用アルミ電極1232,233,234・・・・・・ひ
さし状酸化膜細条會横切るアル電配線。 10/ 番l 図
FIGS. 1(a) and 1(b) are a cross-sectional view of an MO8 capacitor according to an embodiment of the present invention during the manufacturing process, FIG.
), (e) are A-& and B-B of figure (e), respectively.
A sectional view, FIG. 2(a) is a plan view of the second embodiment of the present invention,
Figures (b) and (Q) are sectional views taken along line A and B in figure (a), respectively. 101.201...N'fJ cow conductor board, 10
2...N+ diffusion layer, 103,203...
・Oxide film, 104°204...Polysilicon,
105,205...Oxide film on polysilicon,
106,206...Polysilicon strip, 107
, 209... Eaves-shaped oxide film strips, 108...
...Capacitor oxide film, 109...00. Capacitor oxide film for trimming, 111... Al (wiring) connected to N diffusion layer, 112... Aluminum electrode covering capacitor oxide film, 113... Capacitor oxide for trimming Luminous electrode covering membrane, 114.1
15... Al wiring connecting the aluminum ζ electrode covering the capacitor oxidized Ht and the tritander electrode, 116.11
7... Aluminum electrode for trimming, 11B...
... Aluminum wiring that crosses the eaves-like oxide film strip, 221
...P@diffused resistance, 222,223...
・Al electric wiring coming out from both ends of the resistor %224,225°2
26.227・・・・・・Alu electric wiring for Torinonda, 2
28.229, 230, 231... Aluminum electrodes for trimming 1232, 233, 234... Aluminum wiring that crosses the eave-shaped oxide film strip. 10/No.l Figure

Claims (1)

【特許請求の範囲】[Claims] 一導電型の半導体基板と、この半導体基板上に形成され
た絶llHと、この絶縁膜にあけられた窓を通して前記
半導体基板上に形成された受動素子に接続して設けられ
た複数の配線電極と、前記絶縁膜上に設けられた上部が
ひさし状に張9出したひさし状絶縁性細条と、このひさ
し状絶縁性細条をtたぐようにして前記複数の配線電極
のうちの任意の配線電極間を接続するように前記絶縁膜
上に設けられ、前記絶縁性細条部で段切れを生じている
導電性細条とを含むことを特徴とするトリ電ング用受動
素子。
A semiconductor substrate of one conductivity type, a conductor formed on the semiconductor substrate, and a plurality of wiring electrodes connected to the passive elements formed on the semiconductor substrate through windows formed in the insulating film. and an eaves-like insulating strip provided on the insulating film, the upper part of which extends out into an eave-like shape, and any one of the plurality of wiring electrodes extending over the eaves-like insulating strip. and a conductive strip provided on the insulating film so as to connect between the wiring electrodes, the conductive strip having a break at the insulating strip.
JP11194881A 1981-07-17 1981-07-17 Passive element for trimming Pending JPS5814561A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11194881A JPS5814561A (en) 1981-07-17 1981-07-17 Passive element for trimming

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11194881A JPS5814561A (en) 1981-07-17 1981-07-17 Passive element for trimming

Publications (1)

Publication Number Publication Date
JPS5814561A true JPS5814561A (en) 1983-01-27

Family

ID=14574154

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11194881A Pending JPS5814561A (en) 1981-07-17 1981-07-17 Passive element for trimming

Country Status (1)

Country Link
JP (1) JPS5814561A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0344063A (en) * 1989-07-11 1991-02-25 Sharp Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0344063A (en) * 1989-07-11 1991-02-25 Sharp Corp Semiconductor device

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