JPS58145146A - Multilayer wiring - Google Patents

Multilayer wiring

Info

Publication number
JPS58145146A
JPS58145146A JP2761882A JP2761882A JPS58145146A JP S58145146 A JPS58145146 A JP S58145146A JP 2761882 A JP2761882 A JP 2761882A JP 2761882 A JP2761882 A JP 2761882A JP S58145146 A JPS58145146 A JP S58145146A
Authority
JP
Japan
Prior art keywords
wiring
conductor
multilayer wiring
multilayer
thereabout
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2761882A
Other languages
Japanese (ja)
Inventor
Masaoki Ishikawa
石川 昌興
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2761882A priority Critical patent/JPS58145146A/en
Publication of JPS58145146A publication Critical patent/JPS58145146A/en
Pending legal-status Critical Current

Links

Landscapes

  • Local Oxidation Of Silicon (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent the generation of protrusions on a conductor wiring as well as to prevent the short-circuit between conductor wiring layers by a method wherein, after the prescribed first wiring pattern has been provided on the conductor using Al, an insulating layer is formed by thinly oxidizing the surface of the conductor, and the second conductor wiring is provided in the same manner. CONSTITUTION:Al, as the first wiring layer, is coated on the whole surface of a semiconductor substrate 1 and after the first wiring layer has been formed by performing an etching so as to obtain the wiring in prescribed measurements, a thin oxide film 7 of 1mA/cm<2> in current density and 500-1,000Angstrom or thereabout in thickness is formed on the wiring using an ammonium borate (NH4)3BO4 solution and the like. Then, an SiO2 film of 4,000Angstrom or thereabout is formed by performing a CVD method, and the second conductor wiring 7 is provided. As for the second wiring, the process same as the first wiring may be performed if necessary. The formation into a particle state of Al, which is the wiring material of said multilayer wiring, is not generated at all even when a heat treatment at 450 deg.C or 490 deg.C is performed, and the breakdown of the insulating layer caused by an Al protrusion, the damage by burning of the wiring and the like due to electrostatic concentration and the like are not generated at all, thereby enabling to obtain an excellent multilayer wiring in high productivity.

Description

【発明の詳細な説明】 本発明は半導体装置の配線、特に集積回路等に用いられ
る導体配線が絶縁物によって分離きれて積層して設けら
れる多層配線に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to interconnects for semiconductor devices, and particularly to multilayer interconnects in which conductor interconnects used in integrated circuits and the like are stacked and separated by insulators.

半導体の集積回路(以下ICと称す)はその構造。The structure of a semiconductor integrated circuit (hereinafter referred to as IC).

集積度などを上げるために、より多層化の配線を必要と
するようになった。通常多層配線は、導体配線上に絶縁
物を堆積した絶縁層と導体を重ねあわせて用いられるが
、前記の理由により、上層と下層の絶縁物を介して配線
が必然的に交叉する部分も発生してくる。このとき、配
線の問題として、導体の平滑性が要求される。例えば配
線材料と(−でアルミニウム(Al)が、電気電導性に
優れていること、加工性が良いこと、さらに材料として
安価であることなどの理由により、一般に広く用いられ
ている。
In order to increase the degree of integration, more multi-layer wiring is now required. Normally, multilayer wiring is used by overlapping an insulating layer with an insulating material deposited on the conductor wiring, but for the reasons mentioned above, there are parts where the wiring inevitably intersects through the upper and lower layers of insulating material. I'll come. At this time, as a wiring issue, smoothness of the conductor is required. For example, wiring materials and (-) aluminum (Al) are generally widely used because they have excellent electrical conductivity, good workability, and are inexpensive as materials.

しかしながらA7は耐熱性に弱いこと、仙の物負とも反
応しゃ−j−<、黙処」M1工程があると粒子什して突
起を発生し、これが、配AQ層間に設けられた絶縁!1
!!A(!l−破損してしまうこと、さらに突起部分に
電界が集中し、導体自体が焼損するなどの原因となる。
However, A7 is weak in heat resistance, and if there is a reaction with it, the M1 process will generate protrusions due to the presence of particles, and this will cause the insulation provided between the AQ layers. 1
! ! A(!l- This may cause damage, and the electric field may concentrate on the protrusion, causing the conductor itself to burn out.

この突起の太ききけ熱処理温度によっても異なるが19
すえば450℃の場合最大2μ径490Cでは3μ径に
も達し、配線が倣細な場合にはこれが原因で良好な特性
も得ることが出来ない。例えば−例として次に′電界効
果トランジスタの多鳩目己純について説明する。
The thickness of this protrusion varies depending on the heat treatment temperature, but 19
For example, at 450° C., the maximum diameter is 2 μm, which reaches 3 μm diameter at 490C, and if the wiring is thin, good characteristics cannot be obtained due to this. For example, next we will explain multi-eye self-purification of a field effect transistor.

第1図は従来の電界効果トランジスタのソース電極とゲ
ート’flU !およびドレイン電極の一部分を示した
もので、(a)はその斜伏図、(blはその多層配&!
部分の断面図を示したものである。
Figure 1 shows the source electrode and gate 'flU!' of a conventional field effect transistor. and a part of the drain electrode, (a) is its oblique view, (bl is its multilayer arrangement &!
It shows a cross-sectional view of the part.

第1図(a)に示すように電界効果トランジスタは半導
体基板1上に導体配線として、ゲート2、ソース3、お
よびドレイン4が形成されたものであり、ここでゲート
2とソース3とが交叉する部分(クロスオーバー)5が
配線上どうしても発生する。この交叉部分5は(b)に
その断面図全示したか、ゲート配#2とソース配線3と
の間には二酸化硅素(5io2) 6 ’r設けて、層
間絶縁を行っている。このとき仮りにゲート配線2に突
起が発生すると、5102が破Is芒れて上層にある、
ソース配線3と短靴して、電界効果トランジスタの機能
か失なわれる原因となる。また配線形状の変動があp1
生産性に障害となっている。
As shown in FIG. 1(a), a field effect transistor has a gate 2, a source 3, and a drain 4 formed as conductive wiring on a semiconductor substrate 1, where the gate 2 and the source 3 intersect. A crossover portion (crossover) 5 inevitably occurs on the wiring. This crossing portion 5 is shown in its entire cross-sectional view in FIG. 2B, and silicon dioxide (5io2) 6'r is provided between the gate wiring #2 and the source wiring 3 for interlayer insulation. At this time, if a protrusion occurs in the gate wiring 2, 5102 is broken and is in the upper layer.
This may interfere with the source wiring 3 and cause the field effect transistor to lose its function. Also, the variation in wiring shape is p1
It is a hindrance to productivity.

本発明の目的は11」述した導体配線に突起物の発生を
防ぎ、導体配線層間で短絡することを防止した多層配線
を提供することにある。
An object of the present invention is to provide a multilayer wiring which prevents the occurrence of protrusions on conductor wiring as described in 11 above and prevents short circuits between conductor wiring layers.

本発明によれは、導体にAlを用い第1の所定の配線パ
ターンを設けたのち、導体の露出している表面を陽+!
!酸化法によって該導体の表面を薄く酸化し、次に絶縁
層全役け、そして第2の導体配線を前記同様にして設け
たことを特徴とした多層配線が得られる。
According to the present invention, after a first predetermined wiring pattern is provided using Al as a conductor, the exposed surface of the conductor is positive!
! A multilayer wiring is obtained, which is characterized in that the surface of the conductor is thinly oxidized by an oxidation method, and then an insulating layer and a second conductor wiring are provided in the same manner as described above.

次に本発明について一実施製造方法と共に、第2図を用
いて説明する。
Next, the present invention will be explained with reference to FIG. 2, together with an embodiment of the manufacturing method.

第2図は本発明により得られた多層配線の断面図を示し
たものである。
FIG. 2 shows a cross-sectional view of a multilayer wiring obtained according to the present invention.

まず半導体基板1上に第1の配線層として、Alを全面
に被着し、所定の配線力性にエツチングによシ設けたの
ち、該配線ヲ、ホウ酸アンモニウム(NH4)a B 
04溶敲などを用いて電流密度1m況4dで500〜1
otioX程度の薄い酸化膜7を設ける。次にSiO2
iS102icVD(Che Vapor Depos
ition)法により4000A形成し、第2の導体配
肪7を設ける。第2の導体配線については必要であれば
前記第1の配線と同様な処理をおこなうこともできる。
First, Al is deposited on the entire surface of the semiconductor substrate 1 as a first wiring layer, and after etching to a predetermined wiring strength, the wiring is coated with ammonium borate (NH4) a B.
500 to 1 at a current density of 1 m and 4 d using a 04 fusing etc.
An oxide film 7 as thin as otioX is provided. Next, SiO2
iS102icVD (Che Vapor Depos
4000A is formed by the second conductor distribution method. The second conductor wiring can be subjected to the same treatment as the first wiring, if necessary.

以上のようにして設けた多層配線の第1の配線材料であ
るAlの粒子化は450℃さらに490℃で熱処理して
も全く発生せずそのためAlの突起による絶縁層の破壊
や、電界集中による配線の焼損などの欠陥が全く発生せ
ず、艮好な多層配線が生産性よく得られる。
Particle formation of Al, which is the first wiring material of the multilayer wiring provided as described above, does not occur even after heat treatment at 450°C and further at 490°C. Defects such as burnout of wiring do not occur at all, and good-looking multilayer wiring can be obtained with high productivity.

尚本発明について、′電界効果トランジスタの多層配線
の場合について述べたが、配線と接触して設けられた基
板の種類、絶縁物の種類また、導体配線が年増の場合で
も本発明による効果は同様にして得られる。
Although the present invention has been described in the case of multilayer wiring of field effect transistors, the effects of the present invention are applicable even when the type of substrate and the type of insulator provided in contact with the wiring, and even when the number of conductor wiring increases over time. obtained in the same way.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(&)は多層配線の一例を示した斜視図、同図(
b)はその断面図を示し、第2図は本発明により得られ
た多層配線の断面図を示したものであり、図中1は基板
、2は第1の導体配線、3は第2の導体配線、6は絶縁
物、7は導体の酸化膜である。 代!1i1人11埋土内原  晋 ¥1図
Figure 1 (&) is a perspective view showing an example of multilayer wiring;
b) shows its cross-sectional view, and FIG. 2 shows a cross-sectional view of the multilayer wiring obtained by the present invention. In the figure, 1 is the substrate, 2 is the first conductor wiring, and 3 is the second conductor wiring. Conductor wiring, 6 is an insulator, and 7 is an oxide film of the conductor. Teens! 1i 1 person 11 buried earth Susumu Uchihara ¥1 diagram

Claims (1)

【特許請求の範囲】[Claims] 基板上に多数の導体配線が絶縁物により分離されて設け
られた多層配線において、前記多数の導体配線全絶縁分
離せしめる絶縁物が前記導体配線全構成する導体材料の
鍍化物であることを特徴とする多層配線。
A multilayer wiring in which a large number of conductor wirings are separated by an insulator on a substrate, characterized in that the insulator that isolates all the conductor wirings is a chloride of a conductive material constituting all of the conductor wirings. multilayer wiring.
JP2761882A 1982-02-23 1982-02-23 Multilayer wiring Pending JPS58145146A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2761882A JPS58145146A (en) 1982-02-23 1982-02-23 Multilayer wiring

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2761882A JPS58145146A (en) 1982-02-23 1982-02-23 Multilayer wiring

Publications (1)

Publication Number Publication Date
JPS58145146A true JPS58145146A (en) 1983-08-29

Family

ID=12225925

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2761882A Pending JPS58145146A (en) 1982-02-23 1982-02-23 Multilayer wiring

Country Status (1)

Country Link
JP (1) JPS58145146A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6984551B2 (en) 1993-01-18 2006-01-10 Semiconductor Energy Laboratory Co., Ltd. MIS semiconductor device and method of fabricating the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6984551B2 (en) 1993-01-18 2006-01-10 Semiconductor Energy Laboratory Co., Ltd. MIS semiconductor device and method of fabricating the same
US7351624B2 (en) 1993-01-18 2008-04-01 Semiconductor Energy Laboratory Co., Ltd. MIS semiconductor device and method of fabricating the same

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