JP2002217353A - Protective apparatus of lithium ion battery - Google Patents
Protective apparatus of lithium ion batteryInfo
- Publication number
- JP2002217353A JP2002217353A JP2001014149A JP2001014149A JP2002217353A JP 2002217353 A JP2002217353 A JP 2002217353A JP 2001014149 A JP2001014149 A JP 2001014149A JP 2001014149 A JP2001014149 A JP 2001014149A JP 2002217353 A JP2002217353 A JP 2002217353A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- bare chip
- ion battery
- chip substrate
- surface side
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/10—Energy storage using batteries
Landscapes
- Protection Of Static Devices (AREA)
- Secondary Cells (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、リチウムイオン電
池の保護装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a protection device for a lithium ion battery.
【０００２】[0002]
【従来の技術】従来、この種のリチウムイオン電池の保
護装置の構成は次のようなものとなっていた。すなわち
基板と、この基板上に実装された電流制御用ＦＥＴ、電
圧制御用ＦＥＴ及び、これらの電流制御用ＦＥＴ、電圧
制御用ＦＥＴの動作制御用の制御素子とを備えた構成と
なっていた。2. Description of the Related Art Hitherto, the structure of a protection device for a lithium ion battery of this type has been as follows. That is, the configuration includes a substrate, a current control FET and a voltage control FET mounted on the substrate, and a control element for controlling the operation of the current control FET and the voltage control FET.
【０００３】[0003]
【発明が解決しようとする課題】上記、従来例において
問題となるのは、基板自体が大型化してしまうというこ
とであった。すなわち上述したごとく、この基板上には
電流制御用ＦＥＴ、電圧制御用ＦＥＴが設けられること
になるので、それらを実装するために基板が大型化して
しまうことになるのであった。A problem in the above-mentioned conventional example is that the size of the substrate itself is increased. That is, as described above, since the current control FET and the voltage control FET are provided on the substrate, the size of the substrate is increased in order to mount them.
【０００４】そこで本発明は、基板の小型化を図ること
を目的とするものである。Therefore, an object of the present invention is to reduce the size of a substrate.
【０００５】[0005]
【課題を解決するための手段】この目的を達成するため
に本発明は、前記電流と電圧制御用ＦＥＴは一枚のベア
チップ基板において、隣接する２個のＦＥＴによって構
成するものであり、これら隣接する２個のＦＥＴは、そ
れぞれ前記一枚のベアチップ基板の上面側にドレイン電
極、下面側にゲート電極とソース電極を有し、これらの
ゲート・ソース電極を前記基板上に電気的に接続し、前
記隣接するＦＥＴのドレイン電極同士間は、これらドレ
イン電極間を覆う前記ベアチップ基板の上面側に設けた
導電性材料により電気的に接続する構成としたものであ
る。In order to achieve this object, the present invention provides a method for controlling a current and a voltage, comprising the steps of: forming two FETs adjacent to each other on a single bare chip substrate; The two FETs each have a drain electrode on the upper surface side of the one bare chip substrate, a gate electrode and a source electrode on the lower surface side, and electrically connect these gate / source electrodes on the substrate. The drain electrodes of the adjacent FETs are electrically connected by a conductive material provided on the upper surface side of the bare chip substrate covering between the drain electrodes.
【０００６】すなわち従来は、基板上に個々に設けられ
た電流制御用ＦＥＴと電圧制御用ＦＥＴを実装していた
ものを、１つのベアチップ基板にこれら２個の電流制御
用ＦＥＴと電圧制御用ＦＥＴを設けたものを実装する構
成とすれば、その実装スペースが小さくなる分だけ基板
自体を小型化することができるものである。That is, conventionally, a current control FET and a voltage control FET which are individually provided on a substrate are mounted, but these two current control FETs and a voltage control FET are mounted on one bare chip substrate. Is mounted, the board itself can be reduced in size by the reduced mounting space.
【０００７】[0007]
【発明の実施の形態】本発明の請求項１に記載の発明
は、基板と、この基板上に実装された電流制御用ＦＥ
Ｔ、電圧制御用ＦＥＴ及び、これらの電流・電圧制御用
ＦＥＴの動作を制御する制御素子とを備え、前記電流と
電圧制御用ＦＥＴは、一枚のベアチップ基板において隣
接する２個のＦＥＴより構成され、一枚のベアチップ基
板の上面側にドレイン電極、下面側にゲート電極とソー
ス電極を有し、これらのゲートとソース電極を、前記基
板上に電気的に接続し、前記の隣接するＦＥＴのドレイ
ン電極同士間はこれらドレイン電極を覆うごとく前記ベ
アチップ基板の上面側に設けた導電性材料により電気的
に接続したリチウムイオン電池の保護装置であって、電
流・電圧制御用ＦＥＴを一枚のベアチップ基板上で構成
することにより、基板上におけるそれらの実装スペース
を小さくし、これによって基板自体を小型化するもので
ある。DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is directed to a substrate and a current control FE mounted on the substrate.
T, a voltage control FET, and a control element for controlling the operation of these current / voltage control FETs, wherein the current and voltage control FETs are composed of two adjacent FETs on one bare chip substrate. A bare chip substrate has a drain electrode on the upper surface side, a gate electrode and a source electrode on the lower surface side, and these gates and source electrodes are electrically connected on the substrate, and the adjacent FETs are connected to each other. A protection device for a lithium ion battery electrically connected by a conductive material provided on the upper surface side of the bare chip substrate so as to cover the drain electrodes between the drain electrodes, wherein the current / voltage control FET is connected to one bare chip. The configuration on the board reduces the space for mounting them on the board, thereby reducing the size of the board itself.
【０００８】本発明の請求項２に記載の発明は、導電性
材料を半田とした請求項１に記載のリチウンイオン電池
の保護装置であって、導電性材料として半田を用いるこ
とにより、一枚のベアチップ基板上において隣接する電
流と電圧制御用ＦＥＴのドレイン電極間を容易に接続す
ることができ、これにより２個のＦＥＴドレイン電極間
の電気抵抗を大幅に下げ、これによってこの部分の発熱
を抑制できるものである。According to a second aspect of the present invention, there is provided the protective device for a lithium ion battery according to the first aspect, wherein the conductive material is solder. The current between the adjacent current and the drain electrode of the voltage control FET on the bare chip substrate can be easily connected, thereby greatly reducing the electrical resistance between the two FET drain electrodes, thereby suppressing heat generation in this area. You can do it.
【０００９】本発明の請求項３に記載の発明は、導電性
材料は、ベアチップ基板の周辺部は薄く、中央部は厚く
なるように設けた請求項１、または請求項２に記載のリ
チウムイオン電池の保護装置であって、ベアチップ基板
の周辺部においては導電性材料を薄くなるように設ける
ことにより、導電性材料がベアチップ基板の外周部に漏
れ出して、他の部分に対する電気的な障害を起こすこと
が無くなるものである。また、中央部を肉厚にすること
により、抵抗値を小さくできることだけではなく、放熱
面積も大きくなり、放熱効果を高めるという事にもつな
がるものである。According to a third aspect of the present invention, the conductive material is provided such that the peripheral portion of the bare chip substrate is thinner and the central portion is thicker. A battery protection device, in which a conductive material is provided so as to be thin in a peripheral portion of a bare chip substrate, so that the conductive material leaks to an outer peripheral portion of the bare chip substrate, and an electrical obstacle to other portions is prevented. It does not happen. In addition, by making the central portion thick, not only the resistance value can be reduced, but also the heat radiation area increases, which leads to an increase in the heat radiation effect.
【００１０】本発明の請求項４に記載の発明は、基板上
に電子部品を半田により実装し、この半田の融点より
も、ベアチップ基板上面側の導電性材料の融点を低くし
た請求項１〜３のいずれか一つに記載のリチウムイオン
電池の保護装置であって、基板上に半田により実装した
他の電子部品の半田よりもベアチップ基板上面側の導電
性材料の融点を低くすることにより、このベアチップ基
板の上面側に導電性材料を設ける際に先に実装が完了し
ている電子部品の半田を溶融させ、それにより実装不良
あるいは電気的な導通障害を無くすものである。According to a fourth aspect of the present invention, an electronic component is mounted on a substrate by soldering, and the melting point of the conductive material on the upper surface side of the bare chip substrate is lower than the melting point of the solder. The protection device for a lithium ion battery according to any one of 3, wherein the melting point of the conductive material on the upper surface side of the bare chip substrate is lower than that of the solder of another electronic component mounted on the substrate by soldering, When a conductive material is provided on the upper surface side of the bare chip substrate, the solder of the electronic component that has been mounted first is melted, thereby eliminating mounting failure or electrical conduction failure.
【００１１】本発明の請求項５に記載の発明は、基板の
上面側においてベアチップ基板上面を絶縁体で覆い、こ
の絶縁体の肉厚を導電性材料の肉厚よりも薄くした請求
項１〜４のいずれか一つに記載のリチウムイオン電池の
保護装置であって、基板の上面側を絶縁体を覆うことに
より、基板の上面側における電気的な絶縁が十分に確保
され、しかもこの絶縁体の肉厚を導電性材料の肉厚より
も薄くすることにより、導電性材料を肉厚にすることに
よって得ている、放熱効果を大きく阻害させることが無
くなるものである。According to a fifth aspect of the present invention, the upper surface of the bare chip substrate is covered with an insulator on the upper surface side of the substrate, and the thickness of the insulator is smaller than the thickness of the conductive material. 4. The protection device for a lithium-ion battery according to any one of items 4, wherein the upper surface of the substrate is covered with an insulator, so that electrical insulation on the upper surface of the substrate is sufficiently ensured. By making the thickness of the conductive material thinner than the thickness of the conductive material, the heat dissipation effect obtained by increasing the thickness of the conductive material is not significantly impaired.
【００１２】（実施の形態）以下に、本発明の一実施形
態におけるリチウムイオン電池の保護装置について、添
付図面に従って説明する。(Embodiment) A protection device for a lithium ion battery according to an embodiment of the present invention will be described below with reference to the accompanying drawings.
【００１３】図１、図２において、１は基板で、この基
板１の上面側には図３に示す制御素子２などが実装され
ている。In FIGS. 1 and 2, reference numeral 1 denotes a substrate, and a control element 2 and the like shown in FIG.
【００１４】すなわち図３はリチウムイオン電池３の保
護回路を示したものであって、リチウムイオン電池３の
ＧＮＤ端子４の間には２個のＦＥＴ５，６が介在してお
り、これら２個のＦＥＴ５，６は制御素子２によって制
御されるようになっている。That is, FIG. 3 shows a protection circuit for the lithium ion battery 3, in which two FETs 5 and 6 are interposed between the GND terminals 4 of the lithium ion battery 3, and these two FETs are provided. The FETs 5 and 6 are controlled by the control element 2.
【００１５】また、これら以外に出力端子７、抵抗８，
９、コンデンサ１０，１１、温度検出素子１２が記載さ
れている。これらの各部品は図１、図２においては基板
１の上面側に実装されている。前記２個のＦＥＴ５，６
は具体的には、図４、図７に示すように１枚のベアチッ
プ基板１３上において、隣接するもので構成されてい
る。In addition to these, the output terminal 7, the resistor 8,
9, capacitors 10, 11 and a temperature detecting element 12 are described. These components are mounted on the upper surface side of the substrate 1 in FIGS. The two FETs 5, 6
Specifically, as shown in FIG. 4 and FIG. 7, on one bare chip substrate 13, it is composed of adjacent ones.
【００１６】すなわち図５は、ＦＥＴのウエハー１４を
示しており、このＦＥＴのウエハー１４は図６に示すご
とくＦＥＴが整列された構成で作られている。That is, FIG. 5 shows a FET wafer 14, and the FET wafer 14 is made of a configuration in which the FETs are arranged as shown in FIG.
【００１７】この図６に示すごとくウエハー１４の上面
側にはゲート電極１５とソース電極１６が設けられてお
り、その下面側には図示していないが、ドレイン電極が
設けられたものとなっている。As shown in FIG. 6, a gate electrode 15 and a source electrode 16 are provided on the upper surface of the wafer 14, and a drain electrode (not shown) is provided on the lower surface thereof. I have.
【００１８】そしてその状態で、図７に示すごとく、隣
接するＦＥＴ５，６をワンセットとして切り出し図１、
図２に示すように実装することになる。その拡大図を示
したものが図４である。In this state, as shown in FIG. 7, adjacent FETs 5 and 6 are cut out as one set, and FIG.
It will be implemented as shown in FIG. FIG. 4 shows the enlarged view.
【００１９】図４に示すごとく、これら２個のＦＥＴ
５，６は、そのゲート電極１５ａ，１５ｂとソース電極
１６ａ，１６ｂが下面側になるように基板１上に実装さ
れ、その上面側が、ドレイン電極となっている。As shown in FIG. 4, these two FETs
5 and 6 are mounted on the substrate 1 such that the gate electrodes 15a and 15b and the source electrodes 16a and 16b are on the lower surface side, and the upper surface side is a drain electrode.
【００２０】これらドレイン電極は、隣接するＦＥＴ
５，６間は、予めドレイン電極間は接続された状態とな
っているが、それだけではなく本実施形態においては、
図４に示すごとく、そのドレイン電極上に更に導電性材
料の一例として、半田１７を設けている。These drain electrodes are connected to adjacent FETs.
Between 5 and 6, the drain electrodes are connected in advance, but in addition to this, in the present embodiment,
As shown in FIG. 4, solder 17 is further provided on the drain electrode as an example of a conductive material.
【００２１】この半田１７は、この図４に示すごとく、
ベアチップ基板１３の周辺部は肉薄になるように、また
中央部は肉厚になるような状態としている。これは半田
１７がベアチップ基板１３の外周部から漏れ出さないと
いう配慮からである。The solder 17 is, as shown in FIG.
The peripheral portion of the bare chip substrate 13 is made thinner and the central portion is made thicker. This is because the solder 17 does not leak from the outer peripheral portion of the bare chip substrate 13.
【００２２】また、中央部を肉厚にした理由は、このよ
うにすることによって隣接するＦＥＴ５，６間の電気抵
抗を、より小さくすることができるという事と、この様
に肉厚にする事によって半田１７の上面側の面積を大き
くし、それによって放熱面積を稼ぐ事ができるという事
からも、以上の様な構成としたものである。The reason why the thickness of the central portion is made thicker is that the electrical resistance between the adjacent FETs 5 and 6 can be made smaller by doing so, and that the thickness is made thicker in this way. The above configuration is also used because the area on the upper surface side of the solder 17 can be increased by this to increase the heat radiation area.
【００２３】なお図４において１８は、ベアチップ基板
１３を基板１上に実装した後に、このベアチップ基板１
３を固定するためのアンダーフィル用の樹脂である。In FIG. 4, reference numeral 18 denotes the bare chip substrate 1 after the bare chip substrate 13 is mounted on the substrate 1.
3 is an underfill resin for fixing 3.
【００２４】図３にも示したが、電気回路的には、ＦＥ
Ｔ６のソース電極１６ｂはＧＮＤ端子４に接続され、ゲ
ート電極１５ｂが制御素子２に接続され、またＦＥＴ５
のゲート電極１５ａは制御素子２に接続され、ソース電
極１６ａがリチウムイオン電池３に接続された状態とな
っている。As shown in FIG. 3, the electric circuit is FE
The source electrode 16b of T6 is connected to the GND terminal 4, the gate electrode 15b is connected to the control element 2, and the FET 5
The gate electrode 15a is connected to the control element 2, and the source electrode 16a is connected to the lithium ion battery 3.
【００２５】この図３においては、ＦＥＴ５，６のそれ
ぞれドレイン電極１７ａ，１７ｂも記載されており、こ
の電気回路図に示す様にドレイン電極１７ａ，１７ｂは
電気的に接続された状態となっている。FIG. 3 also shows the drain electrodes 17a and 17b of the FETs 5 and 6, respectively, and the drain electrodes 17a and 17b are electrically connected as shown in the electric circuit diagram. .
【００２６】更にこれに加えて、これらＦＥＴ５，６の
ドレイン電極１７ａ，１７ｂ上を図４に示すごとく半田
１７によって短絡しているものである。この場合、ただ
単にＦＥＴ５，６のドレイン電極１７ａ，１７ｂだけで
接続するよりは、図４に示すごとく半田１７を盛る事に
より肉厚の電気回路が形成され、これによってこの部分
における電気抵抗を極めて小さく、また放熱面積は極め
て大きくする事ができるものである。In addition, the drain electrodes 17a and 17b of the FETs 5 and 6 are short-circuited by solder 17 as shown in FIG. In this case, rather than merely connecting the drain electrodes 17a and 17b of the FETs 5 and 6, the thicker electric circuit is formed by laying the solder 17 as shown in FIG. It is small and the heat radiation area can be made extremely large.
【００２７】図８は、本発明の他の実施形態を示し、図
１、図２に示すごとく基板１上にＦＥＴ５，６や抵抗
８，９あるいは、コンデンサ１０，１１などを実装した
後に、その上面側を絶縁性の被膜１９を設けたものであ
る。FIG. 8 shows another embodiment of the present invention. As shown in FIGS. 1 and 2, after mounting the FETs 5, 6 and the resistors 8, 9 or the capacitors 10, 11 on the substrate 1, The upper surface is provided with an insulating film 19.
【００２８】この被膜１９によって全ての部品を覆う事
により上面側に対する絶縁を確保しているものである。
但し、絶縁性の被膜１９は、この図８に示すごとく半田
１７の中央部の最も大きい肉厚よりは、薄くなるように
している。By covering all the components with the coating 19, insulation with respect to the upper surface side is ensured.
However, the insulating film 19 is made thinner than the largest thickness at the central portion of the solder 17 as shown in FIG.
【００２９】この半田１７の中央部を肉厚にした理由
は、上述したごとくそれによって放熱面積を確保したい
という狙いがあったのであって、その意味からしても、
被膜１９の肉厚をあまり厚くすると、この放熱効果が阻
害されるので、その肉厚は半田１７の中央部の最も肉厚
の部分よりは薄くしている。The reason why the thickness of the central portion of the solder 17 is made thicker is to secure a heat radiation area by the above as described above.
If the thickness of the coating 19 is too large, this heat radiation effect is impaired, so that the thickness is made smaller than the thickest portion at the center of the solder 17.
【００３０】[0030]
【発明の効果】以上のように本発明は、基板と、この基
板上に実装された電流制御用ＦＥＴ、電圧制御用ＦＥＴ
及び、これらの電流・電圧制御用ＦＥＴの動作を制御す
る制御素子とを備え、前記電流と電圧制御用ＦＥＴは、
一枚のベアチップ基板において隣接する２個のＦＥＴよ
り構成され、一枚のベアチップ基板の上面側にドレイン
電極、下面側にゲート電極とソース電極を有し、これら
のゲートとソース電極を、前記基板上に電気的に接続
し、前記の隣接するＦＥＴのドレイン電極同士間は、こ
れらドレイン電極を覆うごとく前記ベアチップ基板の上
面側に設けた導電性材料により、電気的に接続したもの
であって、基板上において、２個のＦＥＴが１つのベア
チップ基板で実装できるものとなるので、小型化するこ
とができる。As described above, the present invention relates to a substrate, a current control FET and a voltage control FET mounted on the substrate.
And a control element for controlling the operation of these current and voltage control FETs, wherein the current and voltage control FETs are
One bare chip substrate is composed of two adjacent FETs, and has a drain electrode on the upper surface side and a gate electrode and a source electrode on the lower surface side of one bare chip substrate. Electrically connected to each other, between the drain electrodes of the adjacent FETs, electrically connected by a conductive material provided on the upper surface side of the bare chip substrate so as to cover these drain electrodes, Since two FETs can be mounted on one bare chip substrate on the substrate, the size can be reduced.
【図１】本発明の一実施形態の正面図FIG. 1 is a front view of an embodiment of the present invention.
【図２】本発明の一実施形態の平面図FIG. 2 is a plan view of one embodiment of the present invention.
【図３】本発明の一実施形態の電気回路図FIG. 3 is an electric circuit diagram of one embodiment of the present invention.
【図４】本発明の一実施形態の要部の拡大断面図FIG. 4 is an enlarged sectional view of a main part of one embodiment of the present invention.
【図５】ウエハーの平面図FIG. 5 is a plan view of a wafer.
【図６】ウエハーの拡大平面図FIG. 6 is an enlarged plan view of a wafer.
【図７】ベアチップ基板の平面図FIG. 7 is a plan view of a bare chip substrate.
【図８】本発明の他の実施形態の断面図FIG. 8 is a sectional view of another embodiment of the present invention.
１ 基板 ２ 制御素子 ３ リチウムイオン電池 ４ ＧＮＤ端子 ５ ＦＥＴ ６ ＦＥＴ ７ 出力端子 ８ 抵抗 ９ 抵抗 １０ コンデンサ １１ コンデンサ １２ 温度検出素子 １３ ベアチップ基板 １４ ウエハー １５ａ ＦＥＴのゲート電極 １５ｂ ＦＥＴのゲート電極 １６ａ ＦＥＴのソース電極 １６ｂ ＦＥＴのソース電極 １７ 半田 １７ａ ＦＥＴのドレイン電極 １７ｂ ＦＥＴのドレイン電極 １８ 樹脂 １９ 被膜 DESCRIPTION OF SYMBOLS 1 Substrate 2 Control element 3 Lithium ion battery 4 GND terminal 5 FET 6 FET 7 Output terminal 8 Resistance 9 Resistance 10 Capacitor 11 Capacitor 12 Temperature detection element 13 Bare chip substrate 14 Wafer 15a Gate electrode of FET 15b Gate electrode of FET 16a Source of FET Electrode 16b Source electrode of FET 17 Solder 17a Drain electrode of FET 17b Drain electrode of FET 18 Resin 19 Coating
Claims (5)
御用ＦＥＴ、電圧制御用ＦＥＴ及び、これらの電流・電
圧制御用ＦＥＴの動作を制御する制御素子とを備え、前
記電流と電圧制御用ＦＥＴは、一枚のベアチップ基板に
おいて隣接する２個のＦＥＴより構成され、一枚のベア
チップ基板の上面側にドレイン電極、下面側にゲート電
極とソース電極を有し、これらのゲートとソース電極
を、前記基板上に電気的に接続し、前記の隣接するＦＥ
Ｔのドレイン電極同士間は、これらドレイン電極を覆う
ごとく、前記ベアチップ基板の上面側に設けた導電性材
料により電気的に接続したリチウムイオン電池の保護装
置。1. A semiconductor device comprising: a substrate; a current control FET and a voltage control FET mounted on the substrate; and a control element for controlling the operation of the current / voltage control FET. FET is composed of two adjacent FETs on one bare chip substrate, and has a drain electrode on the upper surface side and a gate electrode and a source electrode on the lower surface side of one bare chip substrate. Are electrically connected on the substrate, and the adjacent FE
A protective device for a lithium ion battery in which T drain electrodes are electrically connected to each other by a conductive material provided on the upper surface side of the bare chip substrate so as to cover the drain electrodes.
のリチウムイオン電池の保護装置。2. The protection device for a lithium ion battery according to claim 1, wherein the conductive material is solder.
は薄く、中央部は厚くなるように設けた請求項１、また
は請求項２に記載のリチウムイオン電池の保護装置。3. The protection device for a lithium ion battery according to claim 1, wherein the conductive material is provided so that the peripheral portion of the bare chip substrate is thin and the central portion is thick.
この半田の融点よりも、ベアチップ基板上面側の導電性
材料の融点を低くした請求項１〜３のいずれか一つに記
載のリチウムイオン電池の保護装置。4. An electronic component is mounted on a substrate by soldering,
4. The protection device for a lithium ion battery according to claim 1, wherein the melting point of the conductive material on the upper surface side of the bare chip substrate is lower than the melting point of the solder.
面を絶縁体で覆い、この絶縁体の肉厚は、導電性材料の
肉厚よりも薄くした請求項１〜４のいずれか一つに記載
のリチウムイオン電池の保護装置。5. The bare chip substrate according to claim 1, wherein an upper surface of the bare chip substrate is covered with an insulator on an upper surface side of the substrate, and a thickness of the insulator is smaller than a thickness of the conductive material. Lithium-ion battery protection device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001014149A JP4674401B2 (en) | 2001-01-23 | 2001-01-23 | Lithium ion battery protector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001014149A JP4674401B2 (en) | 2001-01-23 | 2001-01-23 | Lithium ion battery protector |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2002217353A true JP2002217353A (en) | 2002-08-02 |
| JP4674401B2 JP4674401B2 (en) | 2011-04-20 |
Family
ID=18880884
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001014149A Expired - Fee Related JP4674401B2 (en) | 2001-01-23 | 2001-01-23 | Lithium ion battery protector |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4674401B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006210120A (en) * | 2005-01-27 | 2006-08-10 | Mitsumi Electric Co Ltd | Battery protecting ic chip |
| JP2006210409A (en) * | 2005-01-25 | 2006-08-10 | Mitsumi Electric Co Ltd | Battery protection module |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0832060A (en) * | 1994-07-13 | 1996-02-02 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
| JP2000269260A (en) * | 1999-03-16 | 2000-09-29 | Rohm Co Ltd | Field effect transistor chip and its mounting method |
| JP2002314029A (en) * | 2001-04-09 | 2002-10-25 | Taiyo Yuden Co Ltd | Module electronic parts |
-
2001
- 2001-01-23 JP JP2001014149A patent/JP4674401B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0832060A (en) * | 1994-07-13 | 1996-02-02 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
| JP2000269260A (en) * | 1999-03-16 | 2000-09-29 | Rohm Co Ltd | Field effect transistor chip and its mounting method |
| JP2002314029A (en) * | 2001-04-09 | 2002-10-25 | Taiyo Yuden Co Ltd | Module electronic parts |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006210409A (en) * | 2005-01-25 | 2006-08-10 | Mitsumi Electric Co Ltd | Battery protection module |
| JP2006210120A (en) * | 2005-01-27 | 2006-08-10 | Mitsumi Electric Co Ltd | Battery protecting ic chip |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4674401B2 (en) | 2011-04-20 |
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