JP4674401B2 - Lithium ion battery protector - Google Patents

Lithium ion battery protector Download PDF

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Publication number
JP4674401B2
JP4674401B2 JP2001014149A JP2001014149A JP4674401B2 JP 4674401 B2 JP4674401 B2 JP 4674401B2 JP 2001014149 A JP2001014149 A JP 2001014149A JP 2001014149 A JP2001014149 A JP 2001014149A JP 4674401 B2 JP4674401 B2 JP 4674401B2
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JP
Japan
Prior art keywords
substrate
solder
bare chip
surface side
lithium ion
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Expired - Fee Related
Application number
JP2001014149A
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Japanese (ja)
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JP2002217353A (en
Inventor
茂義 古賀
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Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
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Priority to JP2001014149A priority Critical patent/JP4674401B2/en
Publication of JP2002217353A publication Critical patent/JP2002217353A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/10—Energy storage using batteries

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  • Protection Of Static Devices (AREA)
  • Secondary Cells (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、リチウムイオン電池の保護装置に関するものである。
【０００２】
【従来の技術】
従来、この種のリチウムイオン電池の保護装置の構成は次のようなものとなっていた。すなわち基板と、この基板上に実装された電流制御用ＦＥＴ、電圧制御用ＦＥＴ及び、これらの電流制御用ＦＥＴ、電圧制御用ＦＥＴの動作制御用の制御素子とを備えた構成となっていた。
【０００３】
【発明が解決しようとする課題】
上記、従来例において問題となるのは、基板自体が大型化してしまうということであった。すなわち上述したごとく、この基板上には電流制御用ＦＥＴ、電圧制御用ＦＥＴが設けられることになるので、それらを実装するために基板が大型化してしまうことになるのであった。
【０００４】
そこで本発明は、基板の小型化を図ることを目的とするものである。
【０００５】
【課題を解決するための手段】
この目的を達成するために本発明は、前記電流と電圧制御用ＦＥＴは一枚のベアチップ基板において、隣接する２個のＦＥＴによって構成するものであり、これら隣接する２個のＦＥＴは、それぞれ前記一枚のベアチップ基板の上面側にドレイン電極、下面側にゲート電極とソース電極を有し、これらのゲート・ソース電極を前記基板上に電気的に接続し、前記隣接するＦＥＴのドレイン電極同士間は、これらドレイン電極間を覆う前記ベアチップ基板の上面側に設けた半田により電気的に接続する構成としたものである。
【０００６】
すなわち従来は、基板上に個々に設けられた電流制御用ＦＥＴと電圧制御用ＦＥＴを実装していたものを、１つのベアチップ基板にこれら２個の電流制御用ＦＥＴと電圧制御用ＦＥＴを設けたものを実装する構成とすれば、その実装スペースが小さくなる分だけ基板自体を小型化することができるものである。
【０００７】
【発明の実施の形態】
本発明の請求項１に記載の発明は、基板と、この基板上に実装された電流制御用ＦＥＴ、電圧制御用ＦＥＴ及び、これらの電流・電圧制御用ＦＥＴの動作を制御する制御素子とを備え、前記電流と電圧制御用ＦＥＴは、一枚のベアチップ基板において隣接する２個のＦＥＴより構成され、一枚のベアチップ基板の上面側にドレイン電極、下面側にゲート電極とソース電極を有し、これらのゲートとソース電極を、前記基板上に電気的に接続し、前記の隣接するＦＥＴのドレイン電極同士間はこれらドレイン電極を覆うごとく前記ベアチップ基板の上面側に設けた半田により電気的に接続したリチウムイオン電池の保護装置であって、電流・電圧制御用ＦＥＴを一枚のベアチップ基板上で構成することにより、基板上におけるそれらの実装スペースを小さくし、これによって基板自体を小型化するものであると同時に、一枚のベアチップ基板上において隣接する電流と電圧制御用ＦＥＴのドレイン電極間を容易に接続することができ、これにより２個のＦＥＴドレイン電極間の電気抵抗を大幅に下げ、これによってこの部分の発熱を抑制できるものである。
【０００８】
本発明の請求項２に記載の発明は、ベアチップ基板の周辺部における半田の厚みは、中央部における半田の厚みに比較して薄く形成した請求項１に記載のリチウムイオン電池の保護装置であって、ベアチップ基板の周辺部においては導電性材料を薄くなるように設けることにより、導電性材料がベアチップ基板の外周部に漏れ出して、他の部分に対する電気的な障害を起こすことが無くなるものである。また、中央部を肉厚にすることにより、抵抗値を小さくできることだけではなく、放熱面積も大きくなり、放熱効果を高めるという事にもつながるものである。
【０００９】
本発明の請求項３に記載の発明は、基板上に電子部品を半田により実装し、この半田の融点よりも、ベアチップ基板上面側の導電性材料の融点を低くした請求項１、２のいずれか一つに記載のリチウムイオン電池の保護装置であって、基板上に半田により実装した他の電子部品の半田よりもベアチップ基板上面側の導電性材料の融点を低くすることにより、このベアチップ基板の上面側に導電性材料を設ける際に先に実装が完了している電子部品の半田を溶融させ、それにより実装不良あるいは電気的な導通障害を無くすものである。
【００１０】
本発明の請求項４に記載の発明は、基板の上面側においてベアチップ基板上面を絶縁体で覆い、この絶縁体の肉厚を導電性材料の肉厚よりも薄くした請求項１〜３のいずれか一つに記載のリチウムイオン電池の保護装置であって、基板の上面側を絶縁体で覆うことにより、基板の上面側における電気的な絶縁が十分に確保され、しかもこの絶縁体の肉厚を導電性材料の肉厚よりも薄くすることにより、導電性材料を肉厚にすることによって得ている、放熱効果を大きく阻害させることが無くなるものである。
【００１２】
（実施の形態）
以下に、本発明の一実施形態におけるリチウムイオン電池の保護装置について、添付図面に従って説明する。
【００１３】
図１、図２において、１は基板で、この基板１の上面側には図３に示す制御素子２などが実装されている。
【００１４】
すなわち図３はリチウムイオン電池３の保護回路を示したものであって、リチウムイオン電池３のＧＮＤ端子４の間には２個のＦＥＴ５，６が介在しており、これら２個のＦＥＴ５，６は制御素子２によって制御されるようになっている。
【００１５】
また、これら以外に出力端子７、抵抗８，９、コンデンサ１０，１１、温度検出素子１２が記載されている。これらの各部品は図１、図２においては基板１の上面側に実装されている。前記２個のＦＥＴ５，６は具体的には、図４、図７に示すように１枚のベアチップ基板１３上において、隣接するもので構成されている。
【００１６】
すなわち図５は、ＦＥＴのウエハー１４を示しており、このＦＥＴのウエハー１４は図６に示すごとくＦＥＴが整列された構成で作られている。
【００１７】
この図６に示すごとくウエハー１４の上面側にはゲート電極１５とソース電極１６が設けられており、その下面側には図示していないが、ドレイン電極が設けられたものとなっている。
【００１８】
そしてその状態で、図７に示すごとく、隣接するＦＥＴ５，６をワンセットとして切り出し図１、図２に示すように実装することになる。その拡大図を示したものが図４である。
【００１９】
図４に示すごとく、これら２個のＦＥＴ５，６は、そのゲート電極１５ａ，１５ｂとソース電極１６ａ，１６ｂが下面側になるように基板１上に実装され、その上面側が、ドレイン電極となっている。
【００２０】
これらドレイン電極は、隣接するＦＥＴ５，６間は、予めドレイン電極間は接続された状態となっているが、それだけではなく本実施形態においては、図４に示すごとく、そのドレイン電極上に更に導電性材料の一例として、半田１７を設けている。
【００２１】
この半田１７は、この図４に示すごとく、ベアチップ基板１３の周辺部は肉薄になるように、また中央部は肉厚になるような状態としている。これは半田１７がベアチップ基板１３の外周部から漏れ出さないという配慮からである。
【００２２】
また、中央部を肉厚にした理由は、このようにすることによって隣接するＦＥＴ５，６間の電気抵抗を、より小さくすることができるという事と、この様に肉厚にする事によって半田１７の上面側の面積を大きくし、それによって放熱面積を稼ぐ事ができるという事からも、以上の様な構成としたものである。
【００２３】
なお図４において１８は、ベアチップ基板１３を基板１上に実装した後に、このベアチップ基板１３を固定するためのアンダーフィル用の樹脂である。
【００２４】
図３にも示したが、電気回路的には、ＦＥＴ６のソース電極１６ｂはＧＮＤ端子４に接続され、ゲート電極１５ｂが制御素子２に接続され、またＦＥＴ５のゲート電極１５ａは制御素子２に接続され、ソース電極１６ａがリチウムイオン電池３に接続された状態となっている。
【００２５】
この図３においては、ＦＥＴ５，６のそれぞれドレイン電極１７ａ，１７ｂも記載されており、この電気回路図に示す様にドレイン電極１７ａ，１７ｂは電気的に接続された状態となっている。
【００２６】
更にこれに加えて、これらＦＥＴ５，６のドレイン電極１７ａ，１７ｂ上を図４に示すごとく半田１７によって短絡しているものである。この場合、ただ単にＦＥＴ５，６のドレイン電極１７ａ，１７ｂだけで接続するよりは、図４に示すごとく半田１７を盛る事により肉厚の電気回路が形成され、これによってこの部分における電気抵抗を極めて小さく、また放熱面積は極めて大きくする事ができるものである。
【００２７】
図８は、本発明の他の実施形態を示し、図１、図２に示すごとく基板１上にＦＥＴ５，６や抵抗８，９あるいは、コンデンサ１０，１１などを実装した後に、その上面側を絶縁性の被膜１９を設けたものである。
【００２８】
この被膜１９によって全ての部品を覆う事により上面側に対する絶縁を確保しているものである。但し、絶縁性の被膜１９は、この図８に示すごとく半田１７の中央部の最も大きい肉厚よりは、薄くなるようにしている。
【００２９】
この半田１７の中央部を肉厚にした理由は、上述したごとくそれによって放熱面積を確保したいという狙いがあったのであって、その意味からしても、被膜１９の肉厚をあまり厚くすると、この放熱効果が阻害されるので、その肉厚は半田１７の中央部の最も肉厚の部分よりは薄くしている。
【００３０】
【発明の効果】
以上のように本発明は、基板と、この基板上に実装された電流制御用ＦＥＴ、電圧制御用ＦＥＴ及び、これらの電流・電圧制御用ＦＥＴの動作を制御する制御素子とを備え、前記電流と電圧制御用ＦＥＴは、一枚のベアチップ基板において隣接する２個のＦＥＴより構成され、一枚のベアチップ基板の上面側にドレイン電極、下面側にゲート電極とソース電極を有し、これらのゲートとソース電極を、前記基板上に電気的に接続し、前記の隣接するＦＥＴのドレイン電極同士間は、これらドレイン電極を覆うごとく前記ベアチップ基板の上面側に設けた半田により、電気的に接続したものであって、基板上において、２個のＦＥＴが１つのベアチップ基板で実装できるものとなるので、小型化することができると同時に、一枚のベアチップ基板上において隣接する電流と電圧制御用ＦＥＴのドレイン電極間を容易に接続することができ、これにより２個のＦＥＴドレイン電極間の電気抵抗を大幅に下げ、これによってこの部分の発熱を抑制できるものである。
【図面の簡単な説明】
【図１】本発明の一実施形態の正面図
【図２】本発明の一実施形態の平面図
【図３】本発明の一実施形態の電気回路図
【図４】本発明の一実施形態の要部の拡大断面図
【図５】ウエハーの平面図
【図６】ウエハーの拡大平面図
【図７】ベアチップ基板の平面図
【図８】本発明の他の実施形態の断面図
【符号の説明】
１ 基板
２ 制御素子
３ リチウムイオン電池
４ ＧＮＤ端子
５ ＦＥＴ
６ ＦＥＴ
７ 出力端子
８ 抵抗
９ 抵抗
１０ コンデンサ
１１ コンデンサ
１２ 温度検出素子
１３ ベアチップ基板
１４ ウエハー
１５ａ ＦＥＴのゲート電極
１５ｂ ＦＥＴのゲート電極
１６ａ ＦＥＴのソース電極
１６ｂ ＦＥＴのソース電極
１７ 半田
１７ａ ＦＥＴのドレイン電極
１７ｂ ＦＥＴのドレイン電極
１８ 樹脂
１９ 被膜[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a protection device for a lithium ion battery.
[0002]
[Prior art]
Conventionally, the structure of this type of lithium ion battery protection device has been as follows. That is, the configuration includes a substrate, a current control FET and a voltage control FET mounted on the substrate, and a control element for controlling the operation of the current control FET and the voltage control FET.
[0003]
[Problems to be solved by the invention]
The problem in the above conventional example is that the substrate itself becomes large. That is, as described above, since the current control FET and the voltage control FET are provided on this substrate, the substrate becomes large in order to mount them.
[0004]
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to reduce the size of a substrate.
[0005]
[Means for Solving the Problems]
In order to achieve this object, according to the present invention, the current and voltage control FETs are constituted by two adjacent FETs in a single bare chip substrate. A single bare chip substrate has a drain electrode on the upper surface side and a gate electrode and a source electrode on the lower surface side. These gate and source electrodes are electrically connected on the substrate, and between the drain electrodes of the adjacent FETs. Is configured to be electrically connected by solder provided on the upper surface side of the bare chip substrate covering the drain electrodes.
[0006]
That is, in the past, the current control FET and the voltage control FET that were individually provided on the substrate were mounted, and these two current control FETs and the voltage control FET were provided on one bare chip substrate. If a structure is mounted, the board itself can be downsized by the amount of mounting space.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
The invention according to claim 1 of the present invention includes a substrate, a current control FET, a voltage control FET mounted on the substrate, and a control element for controlling the operation of these current / voltage control FETs. The current and voltage control FET is composed of two adjacent FETs in one bare chip substrate, and has a drain electrode on the upper surface side of the bare chip substrate and a gate electrode and a source electrode on the lower surface side. The gate and source electrodes are electrically connected on the substrate, and the drain electrodes of the adjacent FETs are electrically connected by solder provided on the upper surface side of the bare chip substrate so as to cover the drain electrodes. A protection device for a connected lithium ion battery, in which a current / voltage control FET is formed on a single bare chip substrate, so that their mounting space on the substrate is reduced. The scan can be reduced, thereby at the same time as the substrate itself is intended to miniaturize, it is possible to easily connect the drain electrode of the current and voltage control FET adjacent in a single bare chip on a substrate, thereby 2 The electrical resistance between the FET drain electrodes can be greatly reduced, and this can suppress heat generation in this portion.
[0008]
The invention according to claim 2 of the present invention is the protection device for a lithium ion battery according to claim 1, wherein the thickness of the solder in the peripheral portion of the bare chip substrate is formed thinner than the thickness of the solder in the central portion. In addition, by providing a thin conductive material at the periphery of the bare chip substrate, the conductive material does not leak into the outer periphery of the bare chip substrate and cause electrical failure to other parts. is there. In addition, by making the central portion thick, not only can the resistance value be reduced, but also the heat dissipation area is increased, leading to an increase in the heat dissipation effect.
[0009]
According to a third aspect of the present invention, the electronic component is mounted on the substrate by soldering, and the melting point of the conductive material on the upper surface side of the bare chip substrate is made lower than the melting point of the solder. A device for protecting a lithium ion battery according to claim 1, wherein the bare chip substrate has a lower melting point of the conductive material on the upper surface side of the bare chip substrate than the solder of other electronic components mounted on the substrate by solder. When the conductive material is provided on the upper surface side of the solder, the solder of the electronic component that has been mounted first is melted, thereby eliminating the mounting failure or the electrical conduction failure.
[0010]
According to a fourth aspect of the present invention, in the upper surface side of the substrate, the upper surface of the bare chip substrate is covered with an insulator, and the thickness of the insulator is made thinner than the thickness of the conductive material. A protection device for a lithium ion battery according to any one of the above, wherein covering the upper surface side of the substrate with an insulator ensures sufficient electrical insulation on the upper surface side of the substrate, and the thickness of the insulator By making the thickness less than the thickness of the conductive material, the heat dissipation effect obtained by increasing the thickness of the conductive material is not significantly hindered.
[0012]
(Embodiment)
Hereinafter, a protection device for a lithium ion battery according to an embodiment of the present invention will be described with reference to the accompanying drawings.
[0013]
1 and 2, reference numeral 1 denotes a substrate, and a control element 2 shown in FIG. 3 is mounted on the upper surface side of the substrate 1.
[0014]
That is, FIG. 3 shows a protection circuit for the lithium ion battery 3, and two FETs 5 and 6 are interposed between the GND terminals 4 of the lithium ion battery 3. Are controlled by the control element 2.
[0015]
Besides these, the output terminal 7, resistors 8 and 9, capacitors 10 and 11, and temperature detection element 12 are described. These components are mounted on the upper surface side of the substrate 1 in FIGS. Specifically, the two FETs 5 and 6 are configured to be adjacent to each other on a single bare chip substrate 13 as shown in FIGS.
[0016]
That is, FIG. 5 shows a wafer 14 of FETs, and the wafer 14 of FETs is formed in a configuration in which FETs are aligned as shown in FIG.
[0017]
As shown in FIG. 6, a gate electrode 15 and a source electrode 16 are provided on the upper surface side of the wafer 14, and a drain electrode is provided on the lower surface side although not shown.
[0018]
In this state, as shown in FIG. 7, adjacent FETs 5 and 6 are cut out as one set and mounted as shown in FIGS. FIG. 4 shows an enlarged view thereof.
[0019]
As shown in FIG. 4, these two FETs 5 and 6 are mounted on the substrate 1 such that the gate electrodes 15a and 15b and the source electrodes 16a and 16b are on the lower surface side, and the upper surface side is the drain electrode. Yes.
[0020]
These drain electrodes are in a state where the drain electrodes are connected in advance between the adjacent FETs 5 and 6, but in this embodiment, as shown in FIG. As an example of the conductive material, solder 17 is provided.
[0021]
As shown in FIG. 4, the solder 17 is in a state in which the peripheral portion of the bare chip substrate 13 is thin and the central portion is thick. This is because the solder 17 does not leak from the outer peripheral portion of the bare chip substrate 13.
[0022]
The reason why the central portion is thick is that the electrical resistance between the adjacent FETs 5 and 6 can be made smaller by doing this, and the solder 17 can be made thick by making it thick like this. Since the area on the upper surface side of the substrate can be increased and thereby the heat radiation area can be increased, the above configuration is adopted.
[0023]
In FIG. 4, reference numeral 18 denotes an underfill resin for fixing the bare chip substrate 13 after the bare chip substrate 13 is mounted on the substrate 1.
[0024]
As shown in FIG. 3, in terms of electrical circuit, the source electrode 16 b of the FET 6 is connected to the GND terminal 4, the gate electrode 15 b is connected to the control element 2, and the gate electrode 15 a of the FET 5 is connected to the control element 2. Thus, the source electrode 16a is connected to the lithium ion battery 3.
[0025]
In FIG. 3, the drain electrodes 17a and 17b of the FETs 5 and 6 are also shown, and the drain electrodes 17a and 17b are in an electrically connected state as shown in this electric circuit diagram.
[0026]
In addition to this, the drain electrodes 17a and 17b of the FETs 5 and 6 are short-circuited by the solder 17 as shown in FIG. In this case, rather than simply connecting the drain electrodes 17a and 17b of the FETs 5 and 6, a thick electric circuit is formed by depositing the solder 17 as shown in FIG. It is small and the heat radiation area can be extremely large.
[0027]
FIG. 8 shows another embodiment of the present invention. As shown in FIGS. 1 and 2, after the FETs 5, 6 and resistors 8, 9 or the capacitors 10, 11 are mounted on the substrate 1, the upper surface side is shown. An insulating film 19 is provided.
[0028]
By covering all the parts with this film 19, insulation with respect to the upper surface side is ensured. However, the insulating coating 19 is made thinner than the largest thickness at the center of the solder 17 as shown in FIG.
[0029]
The reason why the central portion of the solder 17 is thick is that, as described above, there is an aim to secure a heat radiation area, and even in that sense, if the thickness of the film 19 is too thick, Since this heat dissipation effect is hindered, its thickness is made thinner than the thickest portion at the center of the solder 17.
[0030]
【The invention's effect】
As described above, the present invention includes a substrate, a current control FET mounted on the substrate, a voltage control FET, and a control element for controlling the operation of the current / voltage control FET, and the current The voltage control FET is composed of two FETs adjacent to each other in one bare chip substrate, and has a drain electrode on the upper surface side and a gate electrode and a source electrode on the lower surface side of these bare chip substrates. And the source electrode are electrically connected on the substrate, and the drain electrodes of the adjacent FETs are electrically connected by solder provided on the upper surface side of the bare chip substrate so as to cover the drain electrodes. it is one, on the substrate, because the two FET becomes that can be implemented in a single bare chip substrate, simultaneously can be miniaturized, a single bare chip group The adjacent current and the drain electrode of the voltage control FET can be easily connected to each other, thereby greatly reducing the electrical resistance between the two FET drain electrodes, thereby suppressing the heat generation in this portion. It is.
[Brief description of the drawings]
FIG. 1 is a front view of one embodiment of the present invention. FIG. 2 is a plan view of one embodiment of the present invention. FIG. 3 is an electric circuit diagram of one embodiment of the present invention. Fig. 5 is a plan view of a wafer. Fig. 6 is an enlarged plan view of a wafer. Fig. 7 is a plan view of a bare chip substrate. Fig. 8 is a cross-sectional view of another embodiment of the present invention. Explanation】
1 Substrate 2 Control element 3 Lithium ion battery 4 GND terminal 5 FET
6 FET
7 Output terminal 8 Resistance 9 Resistance 10 Capacitor 11 Capacitor 12 Temperature detection element 13 Bare chip substrate 14 Wafer 15a FET gate electrode 15b FET gate electrode 16a FET source electrode 16b FET source electrode 17 Solder 17a FET drain electrode 17b FET Drain electrode 18 Resin 19 Coating

Claims (4)

基板と、この基板上に実装された電流制御用ＦＥＴ、電圧制御用ＦＥＴ及び、これらの電流・電圧制御用ＦＥＴの動作を制御する制御素子とを備え、前記電流と電圧制御用ＦＥＴは、一枚のベアチップ基板において隣接する２個のＦＥＴより構成され、一枚のベアチップ基板の上面側にドレイン電極、下面側にゲート電極とソース電極を有し、これらのゲートとソース電極を、前記基板上に電気的に接続し、前記の隣接するＦＥＴのドレイン電極同士間は、これらドレイン電極を覆うごとく、前記ベアチップ基板の上面側に設けた半田により電気的に接続したリチウムイオン電池の保護装置。  A substrate, a current control FET mounted on the substrate, a voltage control FET, and a control element for controlling the operation of these current / voltage control FETs. It is composed of two adjacent FETs in one bare chip substrate, and has a drain electrode on the upper surface side of one bare chip substrate, a gate electrode and a source electrode on the lower surface side, and these gate and source electrodes are arranged on the substrate. A device for protecting a lithium ion battery, wherein the drain electrodes of the adjacent FETs are electrically connected to each other by solder provided on the upper surface side of the bare chip substrate so as to cover the drain electrodes. ベアチップ基板の周辺部における半田の厚みは、中央部における半田の厚みに比較して薄く形成した請求項１に記載のリチウムイオン電池の保護装置。The protective device for a lithium ion battery according to claim 1, wherein the thickness of the solder in the peripheral portion of the bare chip substrate is formed thinner than the thickness of the solder in the central portion . 基板上に電子部品を第２の半田により実装し、この第２の半田の融点よりも、ベアチップ基板上面側の半田の融点を低くした請求項１、２のいずれか一つに記載のリチウムイオン電池の保護装置。  The lithium ion according to any one of claims 1 and 2, wherein an electronic component is mounted on the substrate with a second solder, and the melting point of the solder on the top surface side of the bare chip substrate is lower than the melting point of the second solder. Battery protection device. 基板の上面側においてベアチップ基板上面を絶縁体で覆い、この絶縁体の肉厚は、半田の肉厚よりも薄くした請求項１〜３のいずれか一つに記載のリチウムイオン電池の保護装置。  The protection device for a lithium ion battery according to any one of claims 1 to 3, wherein the top surface of the substrate is covered with an insulator on the top surface of the bare chip substrate, and the thickness of the insulator is smaller than the thickness of the solder.
JP2001014149A 2001-01-23 2001-01-23 Lithium ion battery protector Expired - Fee Related JP4674401B2 (en)

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JP2006210409A (en) * 2005-01-25 2006-08-10 Mitsumi Electric Co Ltd Battery protection module
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0832060A (en) * 1994-07-13 1996-02-02 Hitachi Ltd Semiconductor integrated circuit device and manufacture thereof
JP2000269260A (en) * 1999-03-16 2000-09-29 Rohm Co Ltd Field effect transistor chip and its mounting method
JP2002314029A (en) * 2001-04-09 2002-10-25 Taiyo Yuden Co Ltd Module electronic parts

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0832060A (en) * 1994-07-13 1996-02-02 Hitachi Ltd Semiconductor integrated circuit device and manufacture thereof
JP2000269260A (en) * 1999-03-16 2000-09-29 Rohm Co Ltd Field effect transistor chip and its mounting method
JP2002314029A (en) * 2001-04-09 2002-10-25 Taiyo Yuden Co Ltd Module electronic parts

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