JPH05136837A - Orthogonal detector - Google Patents

Abstract

PURPOSE:To set an orthogonal detector to be unregulated and to stabilize an operation by permitting an A/D conversion means to extract a difference frequency component between the carrier frequency of an orthogonal amplitude modulation wave and a two phase clock frequency in accordance with a two phase clock having a phase difference 90 degrees, which is supplied from a clock generation means, so as to obtain demodulation output. CONSTITUTION:The orthogonal amplitude modulation wave IF converted into an intermediate frequency signal is inputted to the A/D converters 211 and 212, and the outputs are inputted to a detection part 124 through a re-timing circuit 22. The output of a local oscillator 125 is inputted to a sampling clock generator 23 and two outputs are inputted to the A/D converters 211 and 212. The re-timing circuit 22 re-times two pieces of orthogonal phase information from an input signal at the period of data speed fh corresponding to the number of bits included in the information, and it gives them to the detection part 124. Thus, demodulation output DATA can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a quadrature detector which demodulates a quadrature amplitude modulation wave in a system adopting a quadrature amplitude modulation system and obtains two quadrature phase information contained in the modulation wave.

[0002]

2. Description of the Related Art In a system for performing digital transmission via a wireless line, as a modulation method, for example, an amplitude / phase modulation method in which an amplitude and a phase of a carrier wave are changed according to individual baseband signals is adopted. Among such modulation methods, the multi-level quadrature amplitude modulation method, which is advantageous in terms of effective use of frequencies, has been widely adopted in recent years with the progress of compensation technology for interference and fading distortion and the sophistication of modulation / demodulation technology. is there.

The quadrature amplitude modulation wave obtained by such a modulation method is obtained by balance-modulating two orthogonal carrier waves by two independent baseband signals and synthesizing the modulated outputs thereof, so that the receiving end. Then, the above-mentioned two baseband signals are demodulated by using a quadrature detector which performs processing opposite to such modulation.

FIG. 12 is a diagram showing a configuration example of a conventional quadrature detector. In the figure, the quadrature amplitude modulation wave I _F converted into the intermediate frequency signal of the frequency f _c is represented by the mixers 121 ₁ and 1 1.
21 _{2 applied} to one input. The output of the mixer 121 ₁ is connected to one input of a detection unit 124 via a low-pass filter 122 ₁ and an analog-digital converter (A / D) 123 ₁ , and its output is included in a demodulated baseband signal. Information DATA is obtained. Mixer 12
The output of 1 ₂ is passed through a low-pass filter 122 ₂ and an analog-digital converter (A / D) 123 ₂ to the detection section 12
4 is connected to the other input. The output of the local oscillator 125 is connected to the other input of the mixer 121 ₁ and the input of the 90 degree hybrid 126, and its output is the mixer 12 1.
Connected to the other input of 1 ₂ . The clock terminal of the detector 124 is connected to the output of the clock generator 127.

[0005] In the quadrature detector having such a configuration, the quadrature amplitude modulation wave I _F described above shown in equation _{I F = cos (2πf c t} + Φ) ... (1), and the output signal L of the local oscillator 125 L = When shown by the equation _{cos (2πf s t) ... (} 2), the output of the mixer 121 ₁

[0006]

[Equation 1]

A baseband signal represented by the equation is obtained, and a signal Q orthogonal to the baseband signal is obtained at the output end of the mixer 121 ₂ . Since the first term of the above equation (1) is removed by the low pass filter 122 ₁ , its output I is

[0008]

[Equation 2]

The low-pass filter 1 given by
The output Q of 22 ₂ is similarly

[0010]

[Equation 3]

It is given by the equation: Also a local oscillator
Frequency f of the signal output from 125_sIs generally on
Since it is set to almost the same frequency as the above-mentioned intermediate frequency signal,
Low-pass filter 122 ₁, 122₂Each output of

[0012]

[Equation 4]

Two orthogonal baseband signals representing the phase information Φ are obtained as shown in the equation: The analog-to-digital converters 123 ₁ and 123 ₂ sequentially convert these baseband signals into digital signals and detect them in the detection unit 1.
24, and the detection section 124 supplies the information DAT contained in the contents in accordance with the digital signal thus provided.
Send A.

[0014]

By the way, in such a conventional quadrature detector, the mixers 121 ₁ , 121 ₂ , the low-pass filters 122 ₁ , 122 ₂ and the 90-degree hybrid 126 are composed of analog circuits, and The large mechanical size of each element that constitutes the device has been a factor that hinders improvement of the mounting efficiency of the device. Also, 90
The bit error rate of the demodulation output greatly influences the phase shift amount of the quadrature hybrid 126, but its adjustment is not easy and the stability of the operation of the quadrature detector is not always required because it changes depending on the operating environment and other factors. It wasn't enough.

It is an object of the present invention to provide a quadrature detector capable of achieving no adjustment and stabilizing the operation.

[0016]

FIG. 1 is a block diagram showing the principle of the present invention. The present invention provides a demodulating a quadrature amplitude modulated wave in quadrature detector to obtain two orthogonal phase information included in the modulated wave, the carrier frequency f _c of the quadrature amplitude modulation wave
For a frequency f _s at which the inequality of f _c / 2 <f _s <2f _c holds, and (1 + n) / 4 on the time axis for an integer n.
A clock generation means 11 for generating two clocks having a phase difference given by f _s , and a quadrature amplitude modulation wave are individually digitally converted according to the two clocks, and a difference frequency component between the modulation wave and the two-phase clock is generated. And an analog-to-digital conversion means 13 for obtaining the phase as the phase information.

[0017]

In the present invention, the analog-digital conversion means 13 is used.
However, the quadrature amplitude modulation wave is individually digitally converted according to the two clocks supplied by the clock generation means 11.

The frequency f _s of such two clocks is (f _c / 2) with respect to the carrier frequency f _c of the quadrature amplitude modulation wave.
Since the inequality of <f _s <2f _c is set to a value that satisfies the above, in the above-described digital conversion process, unnecessary folding does not occur on the frequency axis, and the difference given by | f _c −f _s | , The frequency component of the carrier frequency is directly included in the component. Further, the phase difference between the two clocks described above, since given by (1 + n) / 4f _s for integers n on the time axis, analog - orthogonal to the two outputs of the digital converting means 13 2
One phase information is obtained.

That is, the analog-digital converting means 13 which replaces the mixer and the low-pass filter used in the conventional example, and the clock generating means 1 which determines the orthogonality of the demodulation output by using a digital circuit instead of the 90-degree hybrid.
Since the quadrature detector is configured by using 1 and 1, the mounting efficiency is improved, the circuit can be adjusted, and the operation stability is improved.

[0020]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 2 is a diagram showing a first embodiment of the present invention.

In the figure, parts having the same functions and configurations as those shown in FIG. 12 are designated by the same reference numerals, and the description thereof will be omitted here. The quadrature amplitude modulation wave I _F converted into the intermediate frequency signal is given to the analog-digital converters (A / D) 21 ₁ and 21 _2, and their outputs are respectively detected through the retiming circuit 22 in the detection section 12.
4 inputs. The output of the local oscillator 125 is connected to the input of the sampling clock generator 23, the two outputs of which are respectively the analog-digital converter 2
It is connected to the clock terminals of 1 ₁ and 21 ₂ .

Regarding the correspondence relationship between this embodiment and the block diagram shown in FIG. 1, the local oscillator 125 and the sampling clock generator 23 include the clock generation means 11
Corresponding to the analog-digital converters 21 ₁ , 21 ₂
The retiming circuit 22 corresponds to the analog-digital conversion means 13.

The operation of this embodiment will be described below with reference to FIG. When the quadrature amplitude modulated wave _IF is represented by the above-mentioned formula (1) and the analog-digital converter 21 ₁ operates according to the sampling clock of the frequency f _s given from the sampling clock generator 23 (FIG. 3). , Its output signal I is, as shown by the dotted line in FIG. 3, the frequency of the difference (hereinafter referred to as “folding frequency”) represented by the formula of f _d = f _c −f _s (8)
Say. ) Component of f _d is output, the signal is represented by the formula _{I = cos (2πf c t +} Φ) = cos (2π (f s + f d) t + Φ) ... (9). Regarding the values of f _c and f _s , in order to reliably perform analog-digital conversion under the condition that unnecessary aliasing does not occur on the frequency axis,

[0024]

[Equation 5]

It shall be set to a value that satisfies the inequality of. Further, in the above equation (9), the conversion cycle T _s of the analog-digital converter 21 ₁ is

[0026]

[Equation 6]

Since the sampling timing t which is given by the equation (1) and which arrives at the period is given by the equation (t = kT _s) for the natural number k, substituting these

[0028]

[Equation 7]

Is indicated as As described above, since the folding frequency component obtained at the output of the analog-digital converter 21 ₁ includes the phase information Φ of the quadrature amplitude modulation wave shown in the equation (1) as it is, for example, a dotted line in FIG. As shown, when the phase information Φ changes between 0 radians and π radians, the phase of the folding frequency component also changes.

The above-described sampling clock is synchronized with the quadrature amplitude modulation wave I _F by the local oscillator 125 as in the conventional example, and is generated in accordance with the sampling clock set to substantially the same frequency. From (8), f _d = 0 (11) Therefore, the analog-digital converter 21
_At the output of ₁ , the cosine component of the phase information indicating the baseband signal is obtained by eliminating the first term in parentheses in the above equation (10). Further, since the analog-to-digital converter 21 ₂ is provided with the sampling clock having a phase difference of 90 degrees from the above-mentioned sampling clock from the sampling clock generator 23, the output thereof is expressed by the formula of Q = sin (2πf _d t + Φ). The signal given by is obtained, and the sine component of the phase information indicating the baseband signal is obtained based on the above equation (11).

Since the retiming circuit 22 retimes the two orthogonal phase information given in this way at a cycle of the data rate f _b according to the number of bits included in them, the retiming circuit 22 gives them to the detection section 124. A demodulated output DATA is obtained at the output as in the conventional example. Thus, according to the present embodiment, analog mixers and 90
Since the quadrature detector is configured without using the hybrid, the circuit scale is reduced, the hybrid phase shift amount and other complicated adjustments are not required, and the operation is stabilized against changes in the operating environment. You can

In this embodiment, the frequency of the sampling clock is set to the natural number n.

[0033]

[Equation 8]

When the value f _s ′ shown in the equation is set, the baseband signal I obtained at the output of the analog-digital converter 21 ₁ is calculated from the above equation (9).

[0035]

[Equation 9]

It is given by the equation: Therefore, if such a baseband signal is sampled at the output terminal of the analog-to-digital converter 21 _{1 at} the frequency shown in the above equation (12), the first term in the parenthesis is eliminated in the above equation (13). Because it is possible

[0037]

[Equation 10]

[0038] That is, the above equation (14) is equal to the equation (10). For example, even if the frequency of the sampling clock is set to a value that is a fraction of an integer as shown in FIGS.
Since the same folding frequency component is obtained as indicated by the dotted line in Fig. 1, the same quadrature detection can be performed by setting the frequency of the sampling clock small, and the power consumption of the quadrature detector can be reduced.

FIG. 6 is a diagram showing a second embodiment of the present invention. In the figure, parts having the same functions and configurations as those shown in FIG. 2 are designated by the same reference numerals, and the description thereof will be omitted here.

The difference between this embodiment and the embodiment shown in FIG. 2 is that, instead of the sampling clock generator 23, a sampling clock generator 61 for sending out two sampling clocks having different phase differences is provided. is there. Since the demodulation operation of this embodiment is the same as that of the first embodiment, its explanation is omitted here, and in the following description, the phase difference between the sampling clocks given to the analog-digital converters 21 ₁ and 21 ₂ will be described. The relationship with the accuracy of demodulation output will be described.

Since an amplitude signal indicating the phase information Φ is obtained at the output of the analog-digital converter 21 ₁ as described above, in order to extract the phase information, the equation (1
A signal orthogonal to the output signal I shown in 4) is required. In the following, such orthogonal signals are referred to as "co
They are called "s component" and "sin component". Here, when the phase difference between the two sampling clocks output from the sampling clock generator 61 is given by Δt on the time axis, the sampling timing t corresponding to these sampling clocks is a natural number n.

[0042]

[Equation 11]

It is shown by the equation. Of the two sampling clocks described above, the folding frequency component S _d1 obtained by sampling the quadrature amplitude modulation wave I _F according to one of the sampling clocks is, for example, as shown in FIG. When the phase of the wave) is advanced compared to the other sampling timing (FIG. 7), S _d1 = cos (2πf _d t + Φ−φ) = cos (2πf _d t + Φ−2πf _c Δt) ... (16) The folding frequency component S _{d2, which} is represented by the formula and is similarly obtained according to the other sampling clock, is represented by the formula S _d2 = cos (2πf _d t + Φ) (17). Therefore, if φ = 0.5π in the above equations (16) and (17), S _d1 = sin (2πf _d t + Φ) S _d2 = cos (2πf _d t + Φ) and the sin and cos components are extracted, and ,

[0044]

[Equation 12]

Even if is set, the sign of the sin component is inverted from the above equations (16) and (17), but two orthogonal components are similarly extracted. However, at the receiving end, the frequency f _c of the carrier component of the quadrature amplitude modulated wave I _F cannot be actually obtained without error, and therefore f _c ′ that substantially matches the frequency is reproduced and used for demodulation processing. That is, if φ = 0.5π,
The actual sampling timing t ′ shown in the above equation (15) is

[0046]

[Equation 13]

The phase difference between the two sampling clocks given by the equation

And

[Equation 14]

It is given by the equation: Here, m is an integer and is a constant that should be set in order to exclude the period from the sampling timing difference when the above-mentioned phase difference is larger than the carrier period. In the above equation (19), T _c ≈
Since T _c ′ and n = m can be considered, the above equation (19)
Is

[0050]

[Equation 15]

It can be transformed into an approximate expression of The phase difference φ ′ between the folding frequencies f _d1 ′ and f _d2 ′ obtained by sampling the carrier wave according to the sampling clock having such a time difference is

[0052]

[Equation 16]

The value of the second term is T _c
Can be deleted because it is an integer multiple of

[0054]

[Equation 17]

It is given by the equation: The two folding frequencies thus obtained are the cos component and si described above when the phase difference φ ′ given by the above equation is 0.5 radian.
Since the phase difference with the n component is equal, the frequency f _c ′ of the reproduction carrier to be used for demodulation is given by the above when the tolerance of the orthogonality determined according to the requirements of the system is given by the percentage value a. According to the phase difference φ ′

[0056]

[Equation 18]

It may be set to a value that satisfies the inequality of.
As described above, according to the present embodiment, the phase difference between the two sampling clocks output from the sampling clock generator 61 is not limited to 0.5 radian, and the required orthogonality and the feasible frequency accuracy of the reproduced carrier wave can be obtained. sampling timing under the equilibrium (FIG. 8) of the time difference (T _S
/ 4 + nT _S ).

Therefore, in this embodiment, the operating speed of the circuit can be slowed down, and the power consumption is reduced.
FIG. 9 is a diagram showing a third embodiment of the present invention.

In the figure, the embodiment shown in FIGS. 2 and 6 is used.
The same reference numerals for the same functions and configurations as
Are added and shown, and the description thereof is omitted here. Implementation
The difference in configuration between the example and the first and second embodiments is that
Log-digital converter 21₁, 21₂Instead of a single
Analog-digital converter (A / D) 91 and its output
A force holding force corresponding to two orthogonal channels I and Q.
Lip flop 92₁, 92₂And the sample
The analog clock is used instead of the analog clock generator 23 (61).
Digital converter 91 and flip-flop 92₁, 9
Two ₂Sampling clock that gives a predetermined clock to
The point is that the genitals 93 are provided.

In the quadrature detector having such a configuration, the sampling clock generator 93 gives a clock to the analog-digital converter 91 at two timings T _S / 4 apart on the time axis with the period T _S (see FIG. 10). The analog-digital converter 91 changes the instantaneous value of the quadrature amplitude modulation wave I _{F at} the clock timing into a digital signal. In addition, the sampling clock generator 93
Is the flip-flop 92 at the timing at which the conversion output of the analog-digital converter 91 is determined in the above-described cycle.
_One clock is applied to each of ₁ and 92 ₂ (FIG. 10). Flip-flop 92 _1, 92 _2, analog in accordance with the clock provided in this way - so to hold the output of the digital converter 91, the output phase information in the same manner as in the first and second embodiments Two orthogonal baseband signals representing Φ are obtained.

As described above, in this embodiment, since the quadrature amplitude modulation wave can be demodulated by using a single analog-digital converter, the circuit scale of the quadrature detector can be reduced. FIG. 11 is a diagram showing a fourth embodiment of the present invention.

In the figure, parts having the same functions and configurations as those of the embodiment shown in FIGS. 2 and 6 are designated by the same reference numerals, and the description thereof will be omitted here. The difference between this embodiment and the first and second embodiments is that the outputs of the analog-digital converters 21 ₁ and 21 ₂ are given to the detection section 124 without passing through the retiming circuit 22, and the sampling clock generator is provided. 23 (61) instead of the analog-digital converters 21 ₁ and 21 ₂ and the detector 124.
Clock generator 1 for supplying clock signal to
11 is provided.

In the quadrature detector having such a configuration, the sampling clock generator 111 generates a sampling clock which is synchronized with the clock indicating the data rate f _b , and is separated by a quarter of the period T _S of the sampling clock. Analog-digital converters 21 ₁ and 21
By ₂ one to provide a sampling clock. further,
The sampling clock generator 111 gives a clock to the detection unit 124 in synchronization with the sampling clock at the timing when the digital signals output from the analog-digital converters 21 ₁ and 21 ₂ are determined.

That is, since the clock that gives the data rate f _b and the frequency f _{c of the} sampling clock are synchronized, the equation of f _S = nf _b is established, and the analog-digital converter shown by the above equation (13) is established. As an output of the above, an equalized signal can be obtained as in the case of operating with a sampling clock of a frequency given by the expression f _S ′ = f _b , so the retiming circuit 22 used in the first to third embodiments is used. The same demodulation processing is possible without doing so, and the circuit scale of the quadrature detector is reduced.

Further, in the present embodiment, the sampling clock generator 111 generates two sampling clocks whose period is equal to (1 / f _b ) and which is separated by T _S on the time axis, and the detection unit 124 receives the data rate. Similar folding frequency components can be obtained even when a clock having the same frequency as f _b is applied.

That is, since the demodulation processing of the quadrature amplitude modulation wave is performed in the same manner even when the operating speeds of the analog-digital converters 21 ₁ and 21 ₂ are lowered, the power consumption is reduced and the analog-digital converter operates at high speed. Since no operation is required, the cost can be reduced.

[0067]

As described above, in the present invention, the analog-to-digital conversion means has the above-mentioned carrier frequency of the quadrature amplitude modulation wave according to the two-phase clock having the phase difference of 90 degrees supplied from the clock generation means. A difference frequency component with respect to the frequency of the two-phase clock is extracted, and a demodulation output is obtained from the phase information included in the difference frequency component.

That is, since the quadrature detector is composed of a clock generating means and an analog-digital converting means which can be realized by a digital circuit instead of the mixer, the low-pass filter and the 90-degree hybrid used in the conventional example, no adjustment is required. It is possible to improve the mounting efficiency and operation stability, and improve the performance of the quadrature detector.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a diagram showing a first embodiment of the present invention.

FIG. 3 is a diagram illustrating a process of generating a folding frequency.

FIG. 4 is a diagram showing information represented by a phase of a folding frequency.

FIG. 5 is a diagram showing a relationship between a sampling period and a folding frequency.

FIG. 6 is a diagram showing a second embodiment of the present invention.

FIG. 7 is a diagram illustrating a process of extracting orthogonal folding frequency components.

FIG. 8 is a diagram showing a relationship between a sampling timing and a phase of a folding frequency.

FIG. 9 is a diagram showing a third embodiment of the present invention.

FIG. 10 is an operation timing chart of the present embodiment.

FIG. 11 is a diagram showing a fourth embodiment of the present invention.

FIG. 12 is a diagram showing a configuration example of a conventional quadrature detector.

[Explanation of symbols]

11 clock generation means 13 analog-digital conversion means 21, 91, 123 analog-digital converter (A
/ D) 22 Retiming circuit 23, 61, 93, 111 Sampling clock generator 92 Flip-flop (F / F) 121 Mixer 122 Low-pass filter 124 Detection unit 125 Local oscillator 126 90 degree hybrid 127 Clock generator

Claims (1)

[Claims] 1. A demodulating quadrature amplitude modulation wave quadrature detector to obtain two orthogonal phase information included in the modulated wave, f _c / 2 relative to the carrier frequency f _c of the quadrature amplitude modulated wave < A frequency f _s at which the inequality of f _s <2f _c holds, and a phase difference given by (1 + n) / 4f _s on the time axis with respect to the integer n 2
Clock generating means (11) for generating one clock, and digitally converting the quadrature amplitude modulated wave individually according to the two clocks, and the phase of the difference frequency component between the modulated wave and the two-phase clock is the phase. A quadrature detector comprising an analog-digital conversion means (13) for obtaining information.