JPH05136426A - Semiconductor element with ferroelectric layer and manufacture thereof - Google Patents

Abstract

PURPOSE:To form a ferroelectric film having excellent crystallizability, and to obtain an MFS type semiconductor element, in which ions are hardly diffused, by reducing the difference of lattice constants. CONSTITUTION:The specified section of a semiconductor element composed of a ferroelectric layer 3 bridged and laminated onto a P-type SiC substrate 1, to which an N-type impurity diffusion layer 2 is formed, and a gate electrode 4 laminated onto the layer 3 is insulated by a layer insulating film 5, and a wiring-layer conductive film 6 is shaped to the impurity diffusion layer 2, thus constituting the semiconductor element. The P-type SiC substrate 1 is used as the substrate because the substrate 1 has a lattice constant of 4.36Angstrom , the difference of lattice constants between the substrate 1 has a small impurity diffusion coefficient as approximately one hundredth of Si. MFS type structure is formed of the impurity diffusion layer 2, the ferroelectric layer 3 and the gate electrode 4 in a ferroelectric memory transistor, and a large-sized semiconductor element can be manufactured though an SiC layer is used.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an MFS type semiconductor device and its manufacturing method.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 7, an MF in which a ferroelectric layer 103 and an electrode 104 are laminated in this order on a semiconductor substrate 101 on which an impurity diffusion layer 102 is formed.
An S-type semiconductor element and a semiconductor device using the same are used.

However, in the conventional MFS type semiconductor device, since the Si substrate or the GaAs substrate is used for the semiconductor substrate 101 and the PZT type ferroelectric substance is used for the ferroelectric substance 103, the following problems occur. ..

Since the difference in lattice constant is large, a ferroelectric film having good crystallinity cannot be obtained.

Ions of ferroelectric constituent elements, such as PZ
In the case of T-based ferroelectrics, Pb ions, etc.
It diffuses in the As substrate.

An unnecessary film such as SiO ₂ is formed at the interface between the Si or GaAs substrate and the PZT type ferroelectric layer.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems of the prior art. By reducing the difference in lattice constant, a ferroelectric film having good crystallinity can be formed, and It is an object of the present invention to provide an MFS type semiconductor element in which ions of a ferroelectric constituent element are less likely to diffuse into a semiconductor substrate, and a manufacturing method thereof.

[0008]

The semiconductor device of the present invention comprises:
A semiconductor substrate made of a SiC substrate, an impurity diffusion layer formed on the surface layer portion of the semiconductor substrate at a predetermined interval, a ferroelectric layer bridged between the impurity diffusion layers on the semiconductor substrate, and the ferroelectric layer. It is characterized by comprising an electrode laminated on a dielectric layer.

In the semiconductor device of the present invention, the Si
The C substrate is preferably laminated on the Si substrate. In the semiconductor element of the present invention, the ferroelectric substance is P
It is preferably a b-element-containing perovskite structure.

The method of manufacturing a semiconductor device of the present invention is characterized in that a SiC layer is formed on a Si substrate, and then a ferroelectric layer and a gate electrode are formed in this order on the SiC layer.

[0011]

In the present invention, since a SiC substrate having a small difference in lattice constant and a small impurity diffusion coefficient from the PZT type ferroelectric is used as the semiconductor substrate, a ferroelectric film having good crystallinity is formed. be able to. Further, since SiC is chemically stable, it is possible to prevent the ions of the ferroelectric constituent elements from diffusing into the semiconductor substrate.

Further, according to the manufacturing method of the present invention, S is added to the Si substrate.
Since the iC layer is formed as a film, it is possible to cope with an increase in size of the semiconductor element.

[0013]

Embodiments of the present invention will be described below with reference to the accompanying drawings, but the present invention is not limited to these embodiments.

FIG. 1 is a cross-sectional view of an essential part of an embodiment of a ferroelectric memory transistor using a semiconductor element of the present invention, FIG. 2 is a graph showing the relationship between voltage and polarization of the memory transistor shown in FIG. 1, and FIG. Is an explanatory view of an example of the film forming process of the first embodiment of the semiconductor element of the present invention; FIG. 4 is an explanatory view of an example of the film forming process of the second embodiment of the semiconductor element of the present invention;
FIG. 5 is an explanatory view of an example of a film forming process of the third embodiment of the semiconductor device of the present invention, and FIG. 6 is a fourth view of the semiconductor device of the present invention.
The explanatory view of one example of the film-forming process of an example is shown.

The ferroelectric memory transistor shown in FIG. 1 has a p-type SiC substrate 1 on which an n-type impurity diffusion layer 2 is formed.
A predetermined portion of the semiconductor element including the ferroelectric layer 3 and the gate electrode 4 laminated on the n-type impurity diffusion layer 2 and bridged to the n-type impurity diffusion layer 2 is insulated by an interlayer insulating film. After that, the wiring layer conductive film 6 is formed on the impurity diffusion layer 2.

In the embodiment shown in FIG. 1, p is used as the substrate.
Type SiC substrate 1 has a lattice constant of 4.36Å
(3C), the difference in lattice constant from PZT (lattice constant: about 4.08 to 4.12Å) used as a ferroelectric is small, and the impurity diffusion coefficient is as small as about 1/100 of Si. It is also stable at high temperature, and since the oxidation rate is particularly slow, an unnecessary film such as a SiO ₂ film is not formed.

The ferroelectric layer 3 has PZT, PLZT, Pb having an ABO ₃ type perovskite structure.
TiO ₃ , BaTiO ₃ or the like (hereinafter, also referred to as a perovskite structure) is used, but the material is not limited to this, and any material having ferroelectricity can be used. Specific examples thereof include BaMgF ₄ , N
aCaF ₃ , a halogen compound such as K ₂ ZnCl ₄ , Zn
Examples thereof include chalcogen compounds such as _1-x Cd _x Te, GeTe, and Sn ₂ P ₂ S ₆ .

In the ferroelectric memory transistor shown in FIG. 1, the impurity diffusion layer 2, the ferroelectric layer 3 and the gate electrode 4 form an MFS type structure. A buffer layer may be formed between the SiC substrate and the ferroelectric layer 3 and / or between the ferroelectric layer 3 and the gate electrode 4. The MFS type ferroelectric memory transistor has the characteristics shown in FIG. In FIG. 2, the horizontal axis represents the electric field and the vertical axis represents the polarization. As is apparent from FIG. 2, when a voltage (Vmax> 0) that causes an electric field of Esat or more in the ferroelectric layer 3 is applied to the gate electrode 4, the state is polarized to the state A and a channel is formed. After that, even if the gate voltage is set to 0, the state becomes B, the polarization remains, and the channel remains formed. On the contrary, the gate electrode 4
When a voltage of Vmax (or a voltage of + Vmax to the substrate 1) is applied, it is polarized to the C state, and when the voltage is set to 0, the D state is entered. No channels are formed in this process.

Next, the semiconductor element (semiconductor device) of the present invention
The film forming process will be described. FIG. 3 shows an example of the film forming process of the first embodiment of the semiconductor device of the present invention.
In the figure, 7 is a p-type SiC substrate, 8 is a ferroelectric thin film,
Reference numeral 9 indicates a gate electrode, and 10 indicates an n-type impurity diffusion layer.

Step 1: PZT on p-type SiC substrate 7
The ferroelectric thin film 8 and the gate electrode 9 are formed in this order at a film thickness of 3000Å and 3000Å, respectively.
For the film formation, a sputtering method, a CVD method, a sol-gel method or the like is used. However, the substrate temperature is about 650 ° C for crystallization.
Or the heat treatment is performed at 650 ° C. after the film formation. (See Fig. 3 (a))

Step 2: By etching,
The unnecessary portion of the ferroelectric thin film 8 and the gate electrode 9 are removed. The etching can be wet etching with a strong acid, but dry etching is preferable in consideration of fine workability. Specifically, ion milling with Ar ions and Cl ions, R with halogen compounds and CH ₄ / H ₂ etc.
There are IE etc. (See Fig. 3 (b))

Step 3: P is implanted into the p-type SiC substrate 7 on the side where the ferroelectric thin film 8 and the gate electrode 9 are laminated by the ion implantation method. At this time, if the substrate temperature is increased (up to about 700 ° C.), the injection becomes easy. (Fig. 3
(See (c))

Hereinafter, a semiconductor device is manufactured in the same manner as the conventional MOS type transistor.

FIG. 4 shows an embodiment of the film forming process of the second embodiment of the present invention. In the figure, 11 is an n-type SiC epitaxial layer, and 12 is a conductive film. The same reference numerals as in FIG. 3 indicate the same or similar elements.

Step 1: The n-type SiC epitaxial layer 11 is formed on the p-type SiC substrate 7 by the epitaxial film formation layer.
To a film thickness of 2 μm. (See Fig. 4 (a))

Step 2: A conductive film 12 made of polysilicon is formed in a predetermined pattern on the n-type SiC epitaxial layer 11 by the LP-CVD method to a film thickness of 3000 Å. (See Fig. 4 (a))

Step 3: A ferroelectric film 8 made of PZT is formed on the p-type SiC substrate 7 on which the conductive film 12 is formed with a film thickness of 3000 Å in the same manner as described above. (Fig. 4 (c)
reference)

Step 4: The ferroelectric film 8 is patterned in a predetermined pattern as described above. After that, P
The wiring layer 13 made of t or Al is formed in a predetermined pattern with a film thickness of 3000 by an ordinary method such as a sputtering method.
Deposition with Å. (See Fig. 4 (d))

FIG. 5 shows an embodiment of the film forming process of the third embodiment. In the figure, 14 is a p-type Si substrate, and 15 is n.
-Type SiC layer, 16 is a ferroelectric thin film, 17 is a gate electrode,
Reference numeral 18 denotes a p-type impurity diffusion layer.

Step 1: n on the p-type silicon substrate 14
Type SiC layer 15 is formed to a thickness of 2 μm by an atmospheric pressure CVD method.
To form a film. At that time, as reaction gases, SiH ₄ , C ₃
Using H _8, a substrate temperature of about 1400 ° C., the gas pressure of about 0.1
Perform at μTorr. In addition, an appropriate amount of PH ₃ is mixed into the reaction gas in order to make it n-type.

Step 2: The ferroelectric thin film 16 made of PZT and the gate electrode 17 made of Pt or Al have film thicknesses of 3000 Å and 3000 Å, respectively, as described above.
To form a film. (See FIG. 5 (b))

Step 3: The unnecessary portions of the ferroelectric thin film 16 and the gate electrode 17 are removed by etching as in the above. (See FIG. 5 (c))

Step 4: p-type impurity diffusion layer 18 is doped with boron by ion implantation to form n-type SiC.
It is formed in a predetermined area in the layer 15. At this time, if the substrate temperature is increased (up to about 700 ° C.), the injection becomes easy.
(See FIG. 5 (d))

FIG. 6 shows an embodiment of the film forming process of the fourth embodiment of the present invention. In the figure, 19 is a p-type SiC epitaxial layer, 20 is a conductive film, and 21 is a wiring layer. The same reference numerals as those in FIG. 5 indicate the same or similar elements.

Step 1: n on the p-type silicon substrate 14
The type SiC layer 15 is formed to a film thickness of up to 2 μm in the same manner as described above, and then the p-type Si layer 15 is formed by the epitaxial film forming method.
The C epitaxial layer 19 is formed to a thickness of 2 μm. (See FIG. 6 (a))

Step 2: Conductive film 2 made of polysilicon
Similarly to the above, 0 is formed in a predetermined pattern with a film thickness of 3000 Å. (See FIG. 6 (b))

Step 3: The ferroelectric layer 16 is formed on the p-type silicon substrate 14 on which the conductive film 20 is formed in a thickness of 3000 Å as described above. (See FIG. 6 (c))

Step 4: The ferroelectric layer 16 is patterned into a predetermined pattern, and then the wiring layer 21 made of Pt or Al is formed into a predetermined pattern with a film thickness of 3000 Å by sputtering. (Fig. 6
(See (d))

[0039]

As described above, according to the present invention, the following effects can be obtained.

Since the difference in lattice constant is small, a ferroelectric film having good crystallinity can be obtained.

Ions of ferroelectric constituent elements (in the case of a Pb-containing perovskite structure, for example, a PZT type ferroelectric,
(Pb ions) do not diffuse into the Si substrate or GaAs substrate.

An unnecessary film such as SiO ₂ is not formed at the interface between the Si substrate or GaAs substrate and the PZT system ferroelectric layer.

Further, according to the manufacturing method of the present invention, a large-sized semiconductor element can be manufactured although the SiC layer is used.

[Brief description of drawings]

FIG. 1 is a sectional view of an essential part of an embodiment of a ferroelectric memory transistor using a semiconductor device of the present invention.

FIG. 2 is a graph showing the relationship between the voltage and polarization of the memory transistor shown in FIG.

FIG. 3 is an explanatory diagram of an example of a film forming process of the first example of the semiconductor device of the present invention.

FIG. 4 is an explanatory view of an example of a film forming process of the second example of the semiconductor device of the present invention.

FIG. 5 is an explanatory diagram of an example of a film forming process of the third example of the semiconductor device of the present invention.

FIG. 6 is an explanatory view of an example of a film forming process of the fourth example of the semiconductor device of the present invention.

FIG. 7 is a cross-sectional view of essential parts of a conventional MFS type semiconductor device.

[Explanation of symbols]

 1 p-type SiC substrate 2 n-type impurity diffusion layer 3 ferroelectric layer 4 gate electrode 5 interlayer insulating film 6 wiring layer conductive film 7 p-type SiC substrate 8 ferroelectric thin film 9 gate electrode 10 n-type impurity diffusion Layer 11 n-type SiC epitaxial layer 12 conductive film 13 wiring layer 14 p-type Si substrate 15 n-type SiC layer 16 ferroelectric thin film 17 gate electrode 18 p-type impurity diffusion layer 19 p-type SiC epitaxial layer 20 conductive film 21 wiring layer

Claims (4)

[Claims] 1. A semiconductor substrate made of SiC, an impurity diffusion layer formed on the surface layer portion of the semiconductor substrate at a predetermined interval, and a ferroelectric layer bridged between the impurity diffusion layers on the semiconductor substrate. And an electrode laminated on the ferroelectric layer. 2. The semiconductor device according to claim 1, wherein the semiconductor substrate made of SiC is laminated on the Si substrate. 3. The semiconductor device according to claim 1, wherein the ferroelectric is a Pb element-containing perovskite structure. 4. A method of manufacturing a semiconductor device, comprising forming a SiC layer on a Si substrate, and then forming a ferroelectric layer and a gate electrode in this order on the SiC layer.