JPH0294559A - Semiconductor storage device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a ferrodielectric memory having easy manufacture, satisfactory write/read characteristics and high reliability by so forming a thin ferrodielectric film as to be brought into contact with the source or drain region of a MOSFET as the first electrode of the source or drain capacitor, and composing a ferrodielectric capacitor of a second electrode laminated on the thin ferrodielectric film. CONSTITUTION:A capacitor is composed of N-type source, drain regions 5 of N-type impurity of a MOSFET as lower electrodes, a thin ferrodielectric film 8 of bismuth titanate formed on the surface thereof, and a thin tungsten film formed on the upper layer as an upper electrode 9. A gate electrode 4 is continuously arranged in one direction of a memory array to form a word line. An interlayer insulating film 7 covering the upper layer is formed, a contact hole is formed, and a bit line 14 is connected. Since the thin ferrodielectric film is formed not on the gate electrode but brought into direct contact with the source, drain regions, a complicated step of patterning the interlayer insulating film can be eliminated.

Description

[Detailed Description of the Invention] [Object of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor memory device and a method for manufacturing the same;
In particular, it relates to capacitor structures for ferroelectric memories.

(Prior Art) In recent years, with advances in semiconductor technology, particularly advances in microfabrication technology, high integration and large scale integration of memories are rapidly progressing.

Among these, ferroelectric memory, which combines an MO8 field effect transistor and a capacitor using a ferroelectric thin film as the capacitor insulating film, is non-volatile, resistant to α-ray soft errors, and suitable for integration. For these reasons, development as a large-scale storage device has been progressing in recent years.

This ferroelectric memory usually has a MOSFET 13 and a ferroelectric capacitor 12 as a unit memory cell, as shown in the circuit shown in FIG. One of the drain electrodes is connected to one electrode of a ferroelectric capacitor 12, the other of which is connected to the drive line 10. The other source/drain electrode of this MOSFET 13 is connected to a bit line 14, a sense amplifier 15, and a bit line capacitor 16.

The element structure of this ferroelectric memory is as shown in FIG. 4, an example of a cross-sectional view, in which a unit memory cell consists of a MOS FET 13 formed in a p-type silicon substrate 1 and a ferroelectric transistor formed in the upper layer. It has been proposed that a unit memory cell is constructed from a body capacitor 12 (1987 National WA
Electronic Devices Society Technology Digest 87' Inte
rna oral Electron Dvce He
eting (IEDH) Technical Dic
+est 87'pp, 850-851>.

This MOSFET 13 consists of an n-type high impurity concentration region 5.6 as a source/drain electrode formed in a p-type silicon substrate 1 and a p-type silicon substrate located between these bird impurity concentration regions 5.6. A gate electrode Vi14 is formed on the surface of the gate electrode 1 with a gate insulating film 3 interposed therebetween.

The ferroelectric capacitor 12 is connected to this MOSFET1.
The capacitor lower electrode i19, the ferroelectric thin film as the capacitor insulation WA8, and the capacitor upper electrode 9 are sequentially laminated on the capacitor 3 via the first interlayer insulating film 17. An insulating film 18 is formed, a contact hole is opened in this second interlayer insulating film 18, and metal arrangement 9! The capacitor upper electrode 9 and the source/drain electrodes of the MOSFET 13 are connected through the layer 20.

In a ferroelectric memory having such a structure, the metal wiring layer 20 for connecting the n-type high impurity concentration region 5, which becomes the source/drain electrode, and the capacitor upper electrode 9 is formed on a step formed by a multilayer interlayer insulating film, etc. In addition, since the wiring is formed in a single layer and connected through a contact hole, the process is complicated, and there are problems in that the reliability of the wiring and the yield are lowered.

Furthermore, since the ferroelectric thin film of this ferroelectric capacitor is formed on the capacitor lower electrode 19 or the first interlayer insulation WA 17, it is extremely difficult to obtain a thin film with good orientation, and the Zanuma polarization There are problems such as the ferroelectric field becomes low, the coercive electric field becomes high, and the hysteresis width of the electric field-dividing characteristic curve becomes narrow, making it impossible to obtain good ferroelectric properties and It has been difficult to obtain good memory cell characteristics, such as adversely affecting the characteristics.

Furthermore, since it is a structure in which a ferroelectric 7Iv film is formed directly above the Goo1 electrode, the interface between the gate electrode and the gate oxide film, due to the electrostrictive effect and pyroelectric effect of the ferroelectric film Alternatively, stress is generated at the interface between the gate oxide film and the substrate surface, causing strain in the channel region, resulting in instability or deterioration of device characteristics.

(Problem to be solved by the invention) 1)! As mentioned above, the conventional memory cell structure of ferroelectric memory has a problem in that the manufacturing process is complicated and the reliability of wiring is likely to deteriorate.

Furthermore, in addition to the deterioration of the characteristics of the MOSFET due to the electrostrictive effect or pyroelectric effect of the ferroelectric thin film, the poor orientation of the ferroelectric thin film has also become a serious problem.

The present invention has been made in consideration of the above-mentioned circumstances, and an object of the present invention is to provide a ferroelectric memory that is easy to manufacture, has good read/write characteristics, and is highly reliable.

[Structure of the Invention] (Means for Solving the Problems) Therefore, in the present invention, a ferroelectric a film is formed so as to be in contact with the source or drain region of a MOSFET, and this M
A ferroelectric capacitor is constructed by using the source or drain region of the OSFET as a first electrode of the capacitor and a second electrode laminated on the ferroelectric thin film.

Preferably, the ferroelectric thin film is comprised of a small crystal thin film.

Furthermore, in the method of the present invention, a ferroelectric thin film as a capacitor insulating film is formed directly on the surface of the source or drain region of this MOSFET by epitaxial growth.

(Function) According to the above structure, the ferroelectric thin film serving as the capacitor insulating film is not formed on the gate electrode with an interlayer insulating film in between, but is formed in direct contact with the source/drain region. , the structure is simple, and it can be easily formed without going through complicated steps such as patterning an interlayer insulating film.

Also, before forming the ferroelectric thin film, do you expose the semiconductor surface in the source/drain region? Since the ferroelectric λ9 film is formed directly on the semiconductor surface, a thin film with better orientation can be obtained than when it is formed on an insulating film. Therefore, a ferroelectric thin film with excellent ferroelectricity, which has a low coercive electric field, high residual polarization, and a wide hysteresis width, can be produced.

In addition, if a small crystalline thin film is used for this ferroelectric material M, since there is no grain boundary, it will be possible to create a strong ferroelectric material with low coercive electric field, high remanent polarization, and wide hysteresis width. A dielectric thin film can be obtained.

In addition, since the ferroelectric ag+ is formed not on the gate electrode but on the source/drain region, the stress and strain generated by light from the ferroelectric thin film have little effect on the gate oxide film and the MO8 interface, and the MOS FET Deterioration and instability of characteristics can be reduced.

In addition, prior to forming the ferroelectric thin film, the semiconductor surface in the source/drain region is exposed, and by selecting appropriate pretreatment and thin film deposition conditions, the exposed semiconductor surface and the ferroelectric thin film can be bonded. It is known that lattice matching can be achieved and ferroelectric thin films can be grown epitaxially (
IEEE Trans, EIectron Dev
+ce, vol, ED -21, DD, 459-50
4 (1974)).

The ferroelectric thin film grown by one bitaxy cell in this manner has high orientation, and therefore has excellent ferroelectricity, and can improve memory cell characteristics.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a cross-sectional view showing a ferroelectric memory cell M4 structure according to an embodiment of the present invention.

In this ferroelectric memory, the unit cell has an impurity concentration of 101
An n-channel MOSFET and a ferroelectric capacitor are formed in an activation region separated by an element isolation field insulation v2 formed in a p-type silicon substrate 1 of approximately 5 to 1017C11.
A ferroelectric thin film 8 as a capacitor insulating film of a ferroelectric capacitor is grown directly on the source/drain region 5 of the ferroelectric capacitor by epitaxy cell growth.

That is, this MOS FET consists of a gate insulating film 4 made of a polycrystalline silicon film formed on the surface of a p-type silicon substrate 1 via a silicon oxide film as a gate insulating film 3, and an n-type impurity region. It is composed of source and drain regions 5.6.

In addition, the ferroelectric capacitor uses the source/drain region 5 made of this n-type impurity region as a lower electrode, and the ferroelectric thin film 8 made of a bismuth titanate (BiTiO3) thin film formed on the surface of this, and the upper layer of this. and an upper electrode 9 made of a thin tungsten film.

The gate electrodes 4 are continuously arranged in one direction of the memory array to form word lines.

Further, a contact hole for bit line contact is formed in the silicon oxide film as the interlayer insulating film 7 covering this upper layer, and the bit line is made of a composite film of a heavily doped polycrystalline silicon layer and an aluminum silicide film. Fi114 is connected.

Next, the BB process of this ferroelectric memory will be explained.

First, a field insulating film 2 for element isolation is formed in a p-type silicon substrate 1 with an impurity concentration of about 1015 to 10 is cm by the usual LOCO8 method.

Then, as shown in FIG. 2(a), a silicon oxide layer with a thickness of 100r+n is formed by thermal oxidation. - After depositing an insulating film 3 and a polycrystalline silicon layer with a film thickness of 300 r+ro and patterning them by photolithography and reactive ion etching to form a gate insulating film 3 and a gate electrode 4, this gate electrode 4 is By implanting arsenic ions as a mask and forming n-type impurity regions that will become source/drain regions 5 and 6 in a self-aligned manner, a MOSFE as a switching transistor is formed.
Form a T.

After this, as shown in FIG. 2(b), C
By VD method, the thickness of the interlayer insulating film 7 is several thousand to several μm.
Deposit a silicon oxide film of approximately

Subsequently, as shown in FIG. 2(C), a contact hole is formed by photolithography and reactive ion etching.

After cleaning the substrate surface exposed in the contact hole, as shown in FIG. 2(d), the CVD method is used to
A ferroelectric thin film 8 made of a single crystal bismuth titanate thin film is grown by epitaxy cell.

Further, as shown in FIG. 2(e), this ferroelectric thin film is patterned so as to remain only on the source/drain regions 5 by 7TL-lithography and reactive ion etching.

Subsequently, as shown in FIG. 2(f), a tungsten thin film is deposited on the upper layer of this capacitor insulating film 8 by the CVD method, and this is patterned to form an upper electrode 9.
Form.

Then, a bit line contact is opened at at by photolithography and reactive ion etching, an aluminum layer is deposited, and patterned by photolithography and reactive ion etching.
, and the basic M4 structure of the cell part as shown in Figure 1 is completed.

According to this ferroelectric memory, the ferroelectric a film as a capacitor insulating film is not formed on the gate electrode with an interlayer insulating film in between, but is formed in direct contact with the source/drain region. Therefore, the W structure is extremely simple, the interlayer insulating film only needs to be scraped, and it can be easily formed without going through complicated processes such as patterning the interlayer insulating film.
The reliability will also be high.

In addition, prior to forming the ferroelectric thin film, the semiconductor surface in the source/drain region is exposed and the ferroelectric thin film is formed directly on the semiconductor surface, so that lattice matching between the exposed semiconductor surface and the ferroelectric thin film is achieved. It is possible to obtain a thin film with excellent orientation. Therefore, it is possible to obtain a ferroelectric material MII2 having excellent ferroelectricity with a low coercive electric field, high residual polarization, and a wide hysteresis width, and it is possible to improve memory cell characteristics.

Also, the ferroelectric thin film is not the gate electrode, but the source electrode.
Since it is formed on the drain region, the influence of stress and strain generated from the ferroelectric material and the ferroelectric film on the gate oxide film and the MO3 interface is suppressed, and the characteristics of the MOS FET are good and stable.

In the above embodiment, a bismuth titanate thin film was used as the capacitor insulating film, but it goes without saying that other ferroelectric λg films such as zirconium lead titanate may be used.

In addition, when forming a ferroelectric thin film, the above-mentioned Example T-C,
Instead of the CVD method, other methods such as MOCVD and RF sputtering may be used. At this time, the ferroelectric thin film does not necessarily have to be a single crystal; even if it is polycrystalline, if the conditions are set so that the lattice matching is good by inheriting the crystallinity of the substrate, A ferroelectric thin film with high orientation and high ferroelectricity can be obtained.

Furthermore, although a tungsten film is used as the capacitor upper electrode, it is not necessarily limited to the tungsten group, and can be changed as appropriate.

(Effects of the Invention) As explained above, according to the semiconductor memory device of the present invention, a ferroelectric Ti film as a capacitor insulating film is directly formed on the surface of the source/drain region of a MOSFET. , it becomes possible to obtain a ferroelectric memory that is easy to manufacture and has good characteristics.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a ferroelectric memory structure according to an embodiment of the present invention;
Figures 2(a) to 2(f) are manufacturing process diagrams of the same ferroelectric memory, Figure 3 is an equivalent circuit diagram of a normal ferroelectric memory, and Figure 4 is a conventional ferroelectric memory. It is a figure showing a structure. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... Field insulating film for element isolation, 3... Gate insulating film, 4... Gate electrode, 5.6... Source/drain region, 7...・Interlayer insulating film, 8...ferroelectric thin film (gabacitor insulating film)
, 9... Capacitor upper electrode, h... Contact hole, 10... Drive line, 11... Word line, 12...
...Ferroelectric capacitor, 13...MOSFET, 1
4... Bit line, 15... Sense amplifier, 16...
... Bit line capacitor, 17... First interlayer insulating film, 18... Second interlayer insulating film, 19... Capacitor upper electrode, 20... Arrangement i1 layer. Figure 2 Figure n Figure

Claims (3)

[Claims] (1) In a semiconductor memory device in which a cell is configured by a MOSFET and a ferroelectric capacitor, the MOSFET
A ferroelectric thin film is formed in contact with the source or drain region of the ET, and the MO
A semiconductor memory device characterized in that a ferroelectric capacitor is configured by using a source or drain region of an SFET as a first electrode of a capacitor and a second electrode laminated on the ferroelectric thin film. . (2) The semiconductor memory device according to claim (1), wherein the ferroelectric thin film is composed of a single crystal thin film. (3) MOSF to form MOSFET on semiconductor substrate
Manufacturing a semiconductor memory device including a step of forming an ET and a capacitor forming step of forming a capacitor, in which a ferroelectric capacitor is laminated on the surface of the MOSFET so that the source or drain region of the MOSFET serves as a first electrode of the capacitor. In the method, the capacitor forming step includes forming a ferroelectric thin film as a capacitor insulating film by epitaxial growth on the surface of the source or drain region of the MOSFET, and forming a second electrode on the upper layer. A method of manufacturing a semiconductor memory device, characterized in that: