JPH0513614A - Plastic pga package - Google Patents

Plastic pga package

Info

Publication number
JPH0513614A
JPH0513614A JP16655291A JP16655291A JPH0513614A JP H0513614 A JPH0513614 A JP H0513614A JP 16655291 A JP16655291 A JP 16655291A JP 16655291 A JP16655291 A JP 16655291A JP H0513614 A JPH0513614 A JP H0513614A
Authority
JP
Japan
Prior art keywords
pins
substrate
hole
pin
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16655291A
Other languages
Japanese (ja)
Inventor
Atsuhiko Izumi
篤彦 和泉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP16655291A priority Critical patent/JPH0513614A/en
Publication of JPH0513614A publication Critical patent/JPH0513614A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To improve the flatness of external lead-out/in pins by making a structure so that pins are fixed in throughholes only by a brazing material on a board and so that pins in four corners of the board are pressed to fit in throughholes. CONSTITUTION:Throughholes 4 have external lead-out pins 11a inserted by press fit method only at four corners of a board 1 to input electric signal from outside or output it to outside. The remains use loose contact pins 11b. These pins should be longer than those of press fit method and have a form of being kept mechanically on the board 1 by a brazing material 12 such as solder without press-fit into throughholes 4. A loose contact pin 11b comes in a loose contact state with the board 1 due to remelting of the brazing material 12; then, the board 1 lowers to the position of the pins 11a by its own weight, resulting in finish of mounting.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はプラスチックピン・グリ
ッド・アレイ(以下P−PGAと略す)パッケージに関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plastic pin grid array (hereinafter abbreviated as P-PGA) package.

【0002】[0002]

【従来の技術】従来の表面実装型P−PGAパッケージ
は、図3に示す様に、少なくともガラスエポキシ等によ
りなる絶縁基材2を積層(または1層のみ)して成る基
板1aに、少なくともボンディングパッド3,スルーホ
ール,ボンディングパッドとスルーホールを電気的に接
続させる為の配線5及びキャビティ部6を有する構造に
なっている。このPGAパッケージのキャビティ部6中
にはAgペースト,または絶縁性のある樹脂等よりなる
接着剤7を介して半導体素子8が固着される。半導体素
子8の上面には、電極(図中省略)が形成されており、
半導体素子の電極と基板1に形成されたボンディングパ
ッドとがボンディング・ワイヤー9により接続される。
キャビティ部6の内部は液状のエポキシ樹脂等の樹脂1
0をポッティングした後、固化させることにより封止樹
脂が形成される。スルーホール4には、電気信号を外部
から入力,または外部へ出力させることを目的として外
部導出用ピン11aが、圧入(プレスヒット)により挿
入されており、挿入後、半田等よりなるロウ材12によ
り固定されていた。
2. Description of the Related Art As shown in FIG. 3, a conventional surface mount P-PGA package has at least bonding to a substrate 1a formed by laminating (or only one layer) an insulating base material 2 made of at least glass epoxy or the like. The structure has a pad 3, a through hole, a wiring 5 for electrically connecting the bonding pad and the through hole, and a cavity portion 6. A semiconductor element 8 is fixed in the cavity 6 of the PGA package with an adhesive 7 made of Ag paste or insulating resin. An electrode (not shown) is formed on the upper surface of the semiconductor element 8,
The electrodes of the semiconductor element and the bonding pads formed on the substrate 1 are connected by the bonding wires 9.
The inside of the cavity 6 is a resin 1 such as a liquid epoxy resin.
After potting 0, the encapsulating resin is formed by solidifying. An external lead-out pin 11a is inserted into the through hole 4 by press fitting (press hit) for the purpose of inputting or outputting an electric signal from the outside. After the insertion, the brazing material 12 made of solder or the like is used. It was fixed by.

【0003】[0003]

【発明が解決しようとする課題】この従来の表面実装型
P−PAGパッケージでは各ピンどうしの基板底面から
の高さ(コプラナリティー:平坦性)をどの様にして一
定にするかが重要な問題である。この従来例では各ピン
を圧入している為、各ピンどうしのコプラナリティーの
コントロールは困難であり、かつピンの圧入により基板
自身の反りが発生する様な問題点があった。コプラナリ
ティーが悪いと、実装時に、各ピンどうしに平坦性がな
いので、半田実装ができないという問題点が発生する。
また、実装用基板へ搭載機を用いて搭載しようとしても
精度よく搭載することができない。
In this conventional surface mount type P-PAG package, it is an important problem how to make the height (coplanarity: flatness) of each pin from the bottom surface of the substrate constant. Is. In this conventional example, since the pins are press-fitted, it is difficult to control the coplanarity between the pins, and there is a problem that the press-fitting of the pins causes warping of the substrate itself. If the coplanarity is poor, there is a problem that soldering cannot be performed because each pin has no flatness at the time of mounting.
Further, even if an attempt is made to mount the mounting board on the mounting board, the mounting cannot be carried out accurately.

【0004】[0004]

【課題を解決するための手段】本発明の表面実装型プラ
スチックPGAパッケージは少なくとも絶縁基板に、キ
ャビティ部、ボンディング・パッド,外部へ電気信号を
導出入させるピンを挿入する為のスルー・ホール,及び
該スルーホールとボンディング・パッドとを電気的に接
続させる為の配線を有し、前記スルーホール中に電気信
号を外部に導出入させる為のピンが挿入されているプラ
スチックPGAパッケージにおいて、前記ピンは前記ス
ルーホール中に半田等のロウ材でのみ前記基板に固定さ
れているピン(以下ルーズ・コンタクトピンと称す)と
し、かつ前記基板の四隅のピンは、スルーホールに圧入
した構造、または基板の四隅に柱を設け、基板に装着さ
れた全てのピンは半田等のロウ材でのみ固定した構造と
する。
A surface mount type plastic PGA package of the present invention has at least an insulating substrate, a cavity portion, a bonding pad, a through hole for inserting a pin for introducing and outputting an electric signal to the outside, and In a plastic PGA package having wiring for electrically connecting the through hole and a bonding pad, and a pin for inserting and extracting an electric signal to the outside is inserted in the through hole, the pin is Pins (hereinafter referred to as loose contact pins) fixed to the substrate only by brazing material such as solder in the through hole, and pins at four corners of the substrate are press-fitted into the through hole, or four corners of the substrate. Columns are provided on all the pins, and all pins mounted on the board are fixed only by brazing material such as solder.

【0005】[0005]

【実施例】次に本発明の実施例について添付の図面を参
照して説明する。
Embodiments of the present invention will now be described with reference to the accompanying drawings.

【0006】図1は本発明の第1の実施例に係る表面実
装型P−PGAパッケージを示す縦断面図である。
FIG. 1 is a vertical sectional view showing a surface mount type P-PGA package according to a first embodiment of the present invention.

【0007】基板1は少なくともガラスエポキシ樹脂,
またはトリアジン樹脂等よりなる絶縁基板2を積層(ま
たは1層のみ)した構造である。PAGパッケージは、
この基板1に、ボンディングパッド3,スルーホール
4,ボンディングパッドとスルーホール間を電気的に接
続させる為の配線5、及びキャビティ部6を形成した構
成になっている。このPAGパッケージのキャビティ部
6中にはAgペースト等よりなる導電性の樹脂,または
絶縁性のある樹脂等よりなる接着剤7を介して半導体素
子8が固着される。半導体素子8の上面には電極が形成
されており、半導体素子の電極と基板1に形成されたボ
ンディングパッド3とがボンディング・ワイヤーにより
接続される。キャビティ部6の内部は液状のエポキシ樹
脂等の樹脂10をポッティングした後、固化させること
により封止樹脂が形成される。スルーホール4には、電
気信号を外部から入力,または外部へ出力させることを
目的として、外部導出用のピン11aが基板の4隅にの
みプレスヒット方式により挿入されている。残りのピン
についてはルーズコンタクトピン11bを使用する。こ
のルーズコンタクトピン11bは、プレスヒット方式の
ピンよりは長くし、かつ形状は基板1に設けられたスル
ーホール4に圧入することなく、半田等のロウ材12に
よってのみ機械的に基板に保持されている形状となって
いる。このルーズコンタクトピン11bは、マザーボー
ドに実装する際、基板1と機械的にピンを保持する為の
例えば半田12は再溶融しルーズコンタクトピン11b
と基板1とがルーズコンタクトの状態となる。しかる
後、基板1は、基板自体の自重によりピン11aの位置
まで下がり、実装を完了する。
The substrate 1 is at least glass epoxy resin,
Alternatively, the insulating substrate 2 made of triazine resin or the like is laminated (or only one layer). The PAG package is
The substrate 1 is formed with a bonding pad 3, a through hole 4, a wiring 5 for electrically connecting the bonding pad and the through hole, and a cavity portion 6. A semiconductor element 8 is fixed in the cavity 6 of the PAG package via an adhesive 7 made of a conductive resin such as Ag paste or an insulating resin. An electrode is formed on the upper surface of the semiconductor element 8, and the electrode of the semiconductor element and the bonding pad 3 formed on the substrate 1 are connected by a bonding wire. A resin 10 such as a liquid epoxy resin is potted inside the cavity 6 and then solidified to form a sealing resin. Pins 11a for external lead-out are inserted into the through-holes 4 only at the four corners of the substrate by a press hit method for the purpose of inputting or outputting an electric signal from the outside. Loose contact pins 11b are used for the remaining pins. The loose contact pin 11b is longer than the pin of the press hit type, and its shape is mechanically held only by the brazing material 12 such as solder without being press-fitted into the through hole 4 provided in the substrate 1. It has a shape. When the loose contact pin 11b is mounted on the mother board, the solder 12 for mechanically holding the pin with the substrate 1 is re-melted to loosen the contact pin 11b.
And the substrate 1 are in loose contact. Then, the substrate 1 is lowered to the position of the pin 11a by its own weight, and the mounting is completed.

【0008】図2は本発明の第2の実施例に係る表面実
装型プラスチップPGAパッケージを示す縦断面図であ
る。本実施例は第1の実施例の基板1の4隅にプレスヒ
ット方式により挿入されたピン11aに替えて、基板4
隅に、ガラスエポキシ樹脂等よりなる柱15が接着剤1
4を介して接着された実施例であるので、図2において
図1と同一物には同一符号を付して、その詳細な説明を
省略する。
FIG. 2 is a vertical sectional view showing a surface mount type plus chip PGA package according to a second embodiment of the present invention. In this embodiment, the pins 11a inserted by the press hit method at the four corners of the substrate 1 of the first embodiment are replaced by the substrate 4
In the corner, the pillar 15 made of glass epoxy resin or the like is the adhesive 1
Since it is the embodiment bonded by way of 4, the same parts as those in FIG. 1 are designated by the same reference numerals in FIG. 2 and their detailed description is omitted.

【0009】ピンは全てルーズコンタクトピン11bを
用い、ルーズコンタクトピン11bと基板1とは半田等
の再溶融できる接着剤12でのみ保持されており、かつ
電気的に接続されている。基板1の4隅には、ガラスエ
ポキシ樹脂等よりなり角柱状の形状をした柱15が接着
剤14を介して固着されている。
All the pins are loose contact pins 11b, and the loose contact pins 11b and the substrate 1 are held only by a remeltable adhesive 12 such as solder, and are electrically connected. Pillars 15 made of glass epoxy resin or the like and having a prismatic shape are fixed to the four corners of the substrate 1 with an adhesive 14.

【0010】[0010]

【発明の効果】以上説明したように本発明は、基板4隅
にのみプレスヒット方式で基板にピンを圧入するか、ま
たは、基板の4隅に接着剤を介して角柱状の柱を設け残
りのピン全てはルーズコンタクトピンによって電気信号
を外部に導出入させる様になっているので、基板4隅に
のみ設けたピン、または柱の高さのみが一致していれ
ば、P−PGAパッケージをマザーボードに実装する
際、ルーズコンタクトピンは基板のソリ,またはマザー
ボード自体の反りに応じてピン自体が上下に変動し実装
できる構造としたので、全ピンに対するコプリナリティ
ーの管理を行なう必要がない為、コストが低減できると
いう効果を有する。
As described above, according to the present invention, the pins are press-fitted into the substrate only at the four corners of the substrate by the press hit method, or the prismatic pillars are provided at the four corners of the substrate through the adhesive. All of the pins are designed so that electric signals can be led in and out by loose contact pins, so if the pins provided only at the four corners of the board or only the height of the pillars match, the P-PGA package can be used. When mounting on a motherboard, loose contact pins have a structure that allows the pins themselves to fluctuate up and down depending on the warp of the board or the warp of the motherboard itself, so there is no need to manage coplanarity for all pins. This has the effect of reducing costs.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の表面実装型プラスチックP
GAパッケージの縦断面図。
FIG. 1 is a surface mount type plastic P according to an embodiment of the present invention.
FIG. 3 is a vertical sectional view of a GA package.

【図2】第2の実施例の縦断面図。FIG. 2 is a vertical sectional view of a second embodiment.

【図3】従来の表面実装型プラスチックPGAパッケー
ジの縦断面図。
FIG. 3 is a vertical cross-sectional view of a conventional surface mount plastic PGA package.

【符号の説明】[Explanation of symbols]

1 基板 2 絶縁基板 3 ボンディング・パッド 4 スルーホール 5 配線 6 キャビティ部 7 接着剤 8 半導体素子 9 ボンディング・ワイヤー 10 樹脂 11a ピン 11b ルーズコンタクトピン 12 ロウ材 14 接着剤 15 柱 1 substrate 2 insulating substrate 3 Bonding pad 4 through holes 5 wiring 6 cavity 7 adhesive 8 Semiconductor elements 9 Bonding wire 10 resin 11a pin 11b loose contact pin 12 brazing material 14 Adhesive 15 pillars

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 少なくとも絶縁基板に、半導体素子固着
部であるキャビティ部、半導体素子の電極に接続される
ボンディング・パッド,外部へ電気信号を導出入させる
ピンを挿入する為のスルー・ホール,及び該スルー・ホ
ールとボンディング・パッドとを電気的に接続させる為
の配線を有し、前記スルーホール中に電気信号を外部に
導出入させる為のピンが挿入されているプラスチックP
GAパッケージにおいて、前記ピンは、前記スルーホー
ル中に半田等のロウ材でのみ前記基板に固定されている
ピンとし、かつ、前記基板の四隅のピンは前記スルーホ
ール中に圧入したことを特徴とするプラスチックPGA
パッケージ。
1. A cavity portion, which is a semiconductor element fixing portion, a bonding pad connected to an electrode of the semiconductor element, a through hole for inserting a pin for introducing an electric signal to the outside, and at least an insulating substrate. Plastic P having wiring for electrically connecting the through hole and the bonding pad, and a pin for inserting and extracting an electric signal to the outside is inserted into the through hole.
In the GA package, the pin is a pin fixed to the substrate only by a brazing material such as solder in the through hole, and the pins at four corners of the substrate are press-fitted into the through hole. Plastic PGA
package.
【請求項2】 少なくとも絶縁基板に、半導体素子固着
部であるキャビティ部、半導体素子の電極に接続される
ボンディング・パッド,外部へ電気信号を導出入させる
ピンを挿入する為のスルー・ホール,及び該スルー・ホ
ールとボンディング・パッドとを電気的に接続させる為
の配線を有し、前記スルーホール中に電気信号を外部に
導出入させる為のピンが挿入されているプラスチックP
GAパッケージにおいて、基板4隅に柱を設け、基板に
装着された全てのピンは半田等のロウ材でのみ固定され
ているルーズ・コンタクトピンとしたことを特徴とする
プラスチックPGAパッケージ。
2. A cavity portion, which is a semiconductor element fixing portion, a bonding pad connected to an electrode of the semiconductor element, a through hole for inserting a pin for leading and receiving an electric signal to the outside, and at least an insulating substrate. Plastic P having wiring for electrically connecting the through hole and the bonding pad, and a pin for inserting and extracting an electric signal to the outside is inserted into the through hole.
A plastic PGA package characterized in that in the GA package, pillars are provided at four corners of the substrate, and all pins mounted on the substrate are loose contact pins fixed only by a brazing material such as solder.
JP16655291A 1991-07-08 1991-07-08 Plastic pga package Pending JPH0513614A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16655291A JPH0513614A (en) 1991-07-08 1991-07-08 Plastic pga package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16655291A JPH0513614A (en) 1991-07-08 1991-07-08 Plastic pga package

Publications (1)

Publication Number Publication Date
JPH0513614A true JPH0513614A (en) 1993-01-22

Family

ID=15833381

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16655291A Pending JPH0513614A (en) 1991-07-08 1991-07-08 Plastic pga package

Country Status (1)

Country Link
JP (1) JPH0513614A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08330464A (en) * 1995-05-31 1996-12-13 Nec Kyushu Ltd Pin grid array structure lsi

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08330464A (en) * 1995-05-31 1996-12-13 Nec Kyushu Ltd Pin grid array structure lsi

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