JPH05135812A - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device

Info

Publication number
JPH05135812A
JPH05135812A JP3293979A JP29397991A JPH05135812A JP H05135812 A JPH05135812 A JP H05135812A JP 3293979 A JP3293979 A JP 3293979A JP 29397991 A JP29397991 A JP 29397991A JP H05135812 A JPH05135812 A JP H05135812A
Authority
JP
Japan
Prior art keywords
thick film
film resistance
integrated circuit
circuit device
thick
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3293979A
Other languages
Japanese (ja)
Inventor
Iwao Takiguchi
岩夫 滝口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP3293979A priority Critical patent/JPH05135812A/en
Publication of JPH05135812A publication Critical patent/JPH05135812A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/144Stacked arrangements of planar printed circuit boards

Abstract

PURPOSE:To miniaturize or high by integrate the area of a thick film resistant board, and rationalize the assembling work by using the same clip reeds. CONSTITUTION:In a hybrid integrated circuit device which includes two or more layers of thick film resistor boards 1 and 1, these thick film resistant boards have reed mounting lands for mounting clip reeds 7 in both side margins, and all of the clip reeds 7 are in the same dimensions, and besides each clip reed 7 has multistage of clamp parts 8 and 9 so as to clamping all thick resistant boards 1 whether it is connected to the reed mounting land or not.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は二層以上の厚膜抵抗基
板を含む混成集積回路装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit device including two or more layers of thick film resistance substrates.

【0002】[0002]

【従来の技術】図5乃至図7は従来の混成集積回路装置
を示す図であり、図5は全体的な斜視図、図6はその正
面図、図7は図5および図6に示された混成集積回路装
置の厚膜抵抗基板の一側縁に接続されるクリップリード
の部分拡大斜視図である。これら図において、1は厚膜
抵抗基板、2はアルミニウム等の金属からなるヒートシ
ンク、3はシリコン系の接着剤、4は外部へ電気接続す
るためのクリップリード、5はクリップリード4をハン
ダ付により固定するリード取付けランドである。このリ
ード取付けランド5は印刷導体である。6は厚膜抵抗基
板1の他のランドにハンダ付された半導体素子である。
5 to 7 are views showing a conventional hybrid integrated circuit device. FIG. 5 is an overall perspective view, FIG. 6 is a front view thereof, and FIG. 7 is shown in FIGS. FIG. 6 is a partially enlarged perspective view of a clip lead connected to one side edge of a thick film resistance substrate of the hybrid integrated circuit device. In these figures, 1 is a thick film resistance substrate, 2 is a heat sink made of metal such as aluminum, 3 is a silicon-based adhesive, 4 is a clip lead for electrical connection to the outside, 5 is a clip lead 4 by soldering. It is a lead mounting land to be fixed. The lead mounting land 5 is a printed conductor. Reference numeral 6 is a semiconductor element soldered to another land of the thick film resistance substrate 1.

【0003】発熱する半導体素子6等を搭載した厚膜抵
抗基板1を複数枚有する混成集積回路装置は同一投影面
積内で集積を上げるために、ヒートシンク2に二枚の厚
膜抵抗基板1を適当な接着剤3で接着して、二層構造に
なされる。上下の厚膜抵抗基板は同一機能のものであっ
てもよいし、別の機能のものでもよい。いずれにしても
厚膜抵抗基板1の一側縁に沿って複数のリード取付けラ
ンド5が形成されているので、ヒートシンク2に対して
上下の厚膜抵抗基板を相互にずらして、その一側縁を突
出させてクリップリード4を取り付けている。
In a hybrid integrated circuit device having a plurality of thick film resistance substrates 1 on which heat-generating semiconductor elements 6 and the like are mounted, two thick film resistance substrates 1 are suitable for a heat sink 2 in order to increase integration within the same projected area. Adhesive 3 is used to form a two-layer structure. The upper and lower thick film resistance substrates may have the same function or different functions. In any case, since the plurality of lead mounting lands 5 are formed along one side edge of the thick film resistance substrate 1, the upper and lower thick film resistance substrates are displaced from each other with respect to the heat sink 2 so that one side edge thereof is formed. And the clip lead 4 is attached.

【0004】[0004]

【発明が解決しようとする課題】従来の混成集積回路装
置では厚膜抵抗基板1の複数のリード取付けランド5は
一側にまとめて形成されているので、そこへ通じる導体
パターンを厚膜抵抗基板上に形成する際に基板上を這い
まわすことになり、その導体パターンの総面積が大きく
なって厚膜抵抗基板の面積を必然的に大きくしていたの
である。更に、二層の厚膜抵抗基板がヒートシンクに対
して相互にずらされて段違いになされているので、クリ
ップリードの寸法を大小の二種類を用意しなければなら
ないという問題点があった。
In the conventional hybrid integrated circuit device, the plurality of lead mounting lands 5 of the thick film resistance substrate 1 are collectively formed on one side. Therefore, the conductor pattern leading to them is formed on the thick film resistance substrate 1. When it was formed on the substrate, it crawled over the substrate, and the total area of the conductor pattern became large, which inevitably made the area of the thick film resistor substrate large. Further, since the two-layer thick-film resistance substrates are offset from each other with respect to the heat sink, there is a problem in that two types of clip lead sizes, large and small, must be prepared.

【0005】この発明は上記のような問題点を解消する
ためになされたもので、厚膜抵抗基板の面積を小型化又
は高集積化し、かつ同一クリップリードを使用すること
により組立作業を合理化することを目的とする。
The present invention has been made in order to solve the above problems, and the area of the thick film resistance substrate is reduced or highly integrated, and the same clip lead is used to rationalize the assembling work. The purpose is to

【0006】[0006]

【課題を解決するための手段】この発明による混成集積
回路装置は、二層以上の厚膜抵抗基板を含む混成集積回
路装置であって、これら厚膜抵抗基板から外部へ電気接
続するためのクリップリードを取り付けるリード取付け
ランドが厚膜抵抗基板の両側に形成されており、かつ前
記の複数の層の数に対応した複数の段においてクランプ
部を有した同一寸法のクリップリードで前記の複数の厚
膜抵抗基板を両側においてクランプして必要なリード取
付けランドに接続したことを特徴とする。
A hybrid integrated circuit device according to the present invention is a hybrid integrated circuit device including two or more layers of thick film resistance substrates, and a clip for electrically connecting the thick film resistance substrates to the outside. The lead mounting lands for mounting the leads are formed on both sides of the thick film resistance substrate, and the clip leads of the same size have the clamp portions in the plurality of steps corresponding to the number of the plurality of layers. It is characterized in that the membrane resistance substrate is clamped on both sides and connected to necessary lead mounting lands.

【0007】[0007]

【作用】本発明によれば、厚膜抵抗基板の両側にリード
取付けランドが形成されているので、厚膜抵抗基板の面
積を小さくするかあるいは同じ面積であるとして高集積
化することが出来、また、多段のクランプ部を有した同
一クリップリードの使用により、多層の厚膜抵抗基板の
クランプは一段ごとではなくすべてを一回で済ませるこ
とが出来る。
According to the present invention, since the lead mounting lands are formed on both sides of the thick film resistance substrate, it is possible to reduce the area of the thick film resistance substrate or to achieve high integration with the same area. Further, by using the same clip lead having the multi-stage clamp portion, it is possible to clamp the multi-layer thick-film resistance substrate in one step, not in each step.

【0008】[0008]

【実施例】以下この発明の混成集積回路装置の一実施例
を図1乃至図4を参照して説明する。図1はこの発明の
混成集積回路装置の一実施例を示す斜視図、図2は図1
のうち二段クリップリードのまわりの部分拡大側面図、
図3は図2の側断面図、図4は二段クリップリードの部
分斜視図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the hybrid integrated circuit device of the present invention will be described below with reference to FIGS. 1 is a perspective view showing an embodiment of the hybrid integrated circuit device of the present invention, and FIG.
Partial enlarged side view around the two-stage clip lead,
3 is a side sectional view of FIG. 2, and FIG. 4 is a partial perspective view of the two-stage clip lead.

【0009】これら図において、1は厚膜抵抗基板、2
はヒートシンク、3は接着剤、5はリード取付けラン
ド、6は半導体素子、7は二段クリップリード、8は上
の厚膜抵抗基板用のクランプ部、8は下の厚膜抵抗基板
用のクランプ部である。
In these figures, 1 is a thick film resistor substrate, 2 is
Is a heat sink, 3 is an adhesive, 5 is a lead mounting land, 6 is a semiconductor element, 7 is a two-stage clip lead, 8 is a clamp portion for an upper thick film resistor substrate, and 8 is a clamp for a lower thick film resistor substrate. It is a department.

【0010】本発明ではリード取付けランド5は厚膜抵
抗基板1の両側に設けられていることが図1より理解さ
れる。このため各リード取付けランド5に通じる厚膜抵
抗基板1上の導体パターンの長さは短くなり、厚膜抵抗
基板1全体の面積が小さくなっている。かかる厚膜抵抗
基板1にそれぞれ従来と同じように半導体素子6が装着
されている。これから出る熱をヒートシンク2に伝える
ために接着剤3を介して厚膜抵抗基板1が二枚、ヒート
シンク2の上下面に接着されている。これら二枚の厚膜
抵抗基板は上下が整列されていて同一の投影位置にあ
り、二段クリップリード7はその上下のクランプ部8お
よび9で同時に双方の厚膜抵抗基板をクランプする。そ
して厚膜抵抗基板1の両側における二段クリップリード
の寸法はすべて同一である。次工程でハンダディップさ
れて二段クリップリード7は適宜のリード取付けランド
5に固着される。なお、二段クリップリード7は上下の
クランプ部8,9が必ず上下の厚膜抵抗基板1,1のリ
ード取付けランド5に接続されるとは限らない。上下の
いずれか一方のクランプ部が対応する厚膜抵抗基板のリ
ード取付けランド5に接続される場合もある。つまり、
二段クリップリード7の各クランプ部がクランプする厚
膜抵抗基板の各部分にリード取付けランド5が必ず存在
するとは限らない。とはいえ、その部分に厚膜抵抗基板
上の電気回路に接続されていない開放端のランドを設け
てもよい。
It will be understood from FIG. 1 that the lead mounting lands 5 are provided on both sides of the thick film resistance substrate 1 in the present invention. For this reason, the length of the conductor pattern on the thick film resistance substrate 1 leading to each lead mounting land 5 is shortened, and the area of the entire thick film resistance substrate 1 is reduced. A semiconductor element 6 is mounted on each of the thick film resistance substrates 1 in the same manner as the conventional one. Two thick film resistance substrates 1 are adhered to the upper and lower surfaces of the heat sink 2 via an adhesive 3 in order to transfer the heat generated therefrom to the heat sink 2. These two thick film resistance substrates are vertically aligned and in the same projection position, and the two-stage clip lead 7 clamps both thick film resistance substrates at the same time by the upper and lower clamp portions 8 and 9. The dimensions of the two-stage clip leads on both sides of the thick film resistance substrate 1 are the same. In the next step, the two-stage clip lead 7 is soldered and fixed to an appropriate lead mounting land 5. The upper and lower clamp portions 8 and 9 of the two-stage clip lead 7 are not always connected to the lead mounting lands 5 of the upper and lower thick film resistance substrates 1 and 1, respectively. In some cases, one of the upper and lower clamp parts is connected to the corresponding lead mounting land 5 of the thick film resistance substrate. That is,
The lead mounting lands 5 do not always exist in each portion of the thick film resistance substrate clamped by each clamp portion of the two-stage clip lead 7. However, an open-end land that is not connected to an electric circuit on the thick film resistance substrate may be provided at that portion.

【0011】図1乃至図4の実施例では二層の厚膜抵抗
基板1,1の間にヒートシンク2を備えた構造になって
いるが、ヒートシンク2を必要としない場合には厚膜抵
抗基板の両面に表面実装し、かかる二層の厚膜抵抗基板
1,1間の位置を固定するスペーサで位置決めして、二
段クリップリード7を取り付けてもよい。また、厚膜抵
抗基板は二層に限られない。従って多段クリップリード
となる。しかし複数の厚膜抵抗基板は同一の投影位置に
あり、多段クリップリードはすべて同一寸法である。
In the embodiment shown in FIGS. 1 to 4, the heat sink 2 is provided between the two layers of thick film resistance substrates 1 and 1. However, when the heat sink 2 is not required, the thick film resistance substrate is used. It is also possible to mount the two-stage clip leads 7 by surface mounting on both surfaces of the two and positioning them with a spacer that fixes the position between the two layers of thick film resistance substrates 1 and 1. Further, the thick film resistance substrate is not limited to two layers. Therefore, it becomes a multi-stage clip lead. However, the plurality of thick film resistance substrates are in the same projection position, and the multi-stage clip leads are all the same size.

【0012】[0012]

【発明の効果】以上の様にこの発明によればクリップリ
ードを多段クリップリードになすことにより、上下の厚
膜抵抗基板を同時にクランプ出来、また、リード取付け
ランドを厚膜抵抗基板の両側に形成することにより厚膜
抵抗基板の面積を小さく出来るという効果がある。
As described above, according to the present invention, by forming the clip lead into a multi-stage clip lead, the upper and lower thick film resistance substrates can be simultaneously clamped, and the lead mounting lands are formed on both sides of the thick film resistance substrate. This has the effect of reducing the area of the thick film resistance substrate.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の混成集積回路装置の一実施例を示す斜
視図である。
FIG. 1 is a perspective view showing an embodiment of a hybrid integrated circuit device of the present invention.

【図2】図1の一部を拡大して示す部分拡大正面図であ
る。
FIG. 2 is a partially enlarged front view showing an enlarged part of FIG.

【図3】図1の一部を拡大して示す部分断面図である。FIG. 3 is a partial sectional view showing a part of FIG. 1 in an enlarged manner.

【図4】図1のうち一部材のみを取り出して示す拡大斜
視図である。
FIG. 4 is an enlarged perspective view showing only one member taken out of FIG.

【図5】従来の混成集積回路装置を示す斜視図である。FIG. 5 is a perspective view showing a conventional hybrid integrated circuit device.

【図6】図5のものを側面から見た側面図である。FIG. 6 is a side view of the device of FIG. 5 seen from the side.

【図7】図5のうち一部材のみを取り出して示す拡大斜
視図である。
FIG. 7 is an enlarged perspective view showing only one member taken out of FIG.

【符号の説明】[Explanation of symbols]

1 厚膜抵抗基板 2 ヒートシンク 3 接着剤 5 リード取付けランド 6 半導体素子 7 二段クリップリード 8 上のクランプ部 9 下のクランプ部 1 Thick Film Resistor Board 2 Heat Sink 3 Adhesive 5 Lead Mounting Land 6 Semiconductor Element 7 Two-stage Clip Lead 8 Upper Clamp 9 Lower Clamp

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 二層以上の厚膜抵抗基板を含む混成集積
回路装置において、前記厚膜抵抗基板は外部へ電気接続
するためのクリップリードを取り付けるためのリード取
付けランドを両側に有し、かつ上下の厚膜抵抗基板は同
一の投影位置にあり、またクリップリードはすべて同じ
寸法でありかつ各クリップリードはリード取付けランド
に接続されるか否かにかかわらず各層の厚膜抵抗基板を
クランプする多段のクランプ部を有し、かかる多段のク
ランプ部を有するクリップリードで多層の厚膜抵抗基板
を両側においてクランプする構成にしたことを特徴とす
る混成集積回路装置。
1. A hybrid integrated circuit device including two or more layers of thick-film resistance substrate, wherein the thick-film resistance substrate has lead mounting lands on both sides for mounting clip leads for electrical connection to the outside, and The upper and lower thick film resistor boards are in the same projection position, the clip leads are all the same size, and each clip lead clamps the thick film resistor board of each layer regardless of whether it is connected to the lead mounting land or not. A hybrid integrated circuit device having a multi-stage clamp part, wherein the multi-layer thick-film resistance substrate is clamped on both sides by clip leads having the multi-stage clamp part.
JP3293979A 1991-11-11 1991-11-11 Hybrid integrated circuit device Pending JPH05135812A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3293979A JPH05135812A (en) 1991-11-11 1991-11-11 Hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3293979A JPH05135812A (en) 1991-11-11 1991-11-11 Hybrid integrated circuit device

Publications (1)

Publication Number Publication Date
JPH05135812A true JPH05135812A (en) 1993-06-01

Family

ID=17801677

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3293979A Pending JPH05135812A (en) 1991-11-11 1991-11-11 Hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPH05135812A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111511108A (en) * 2019-01-31 2020-08-07 华为技术有限公司 Circuit board assembly and terminal

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111511108A (en) * 2019-01-31 2020-08-07 华为技术有限公司 Circuit board assembly and terminal
CN111511108B (en) * 2019-01-31 2021-11-09 华为技术有限公司 Circuit board assembly and electronic terminal

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