JPH0513042U - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To prevent the shift of metal wiring around the chip area caused by thermal stress due to temperature cycling. [Structure] A groove parallel to the metal wiring 4 is provided in an interlayer insulating film 3 immediately below at least four corners of the metal wiring 4 provided on the outer periphery of a chip region 5 so that a part of the bottom of the metal wiring 4 is embedded.
Prevent slippage.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a semiconductor integrated circuit.

[0002]

[Prior Art]

 In the conventional semiconductor integrated circuit, as shown in FIG. 2, the metal wiring 4 provided on the outer periphery of the chip area 5 provided on the semiconductor substrate causes a shift due to thermal stress during a temperature cycle test, which causes a defect. I had a problem. Therefore, the thermal stress is dispersed by removing the four corners of the metal wiring layer in the chip region 5.

[0003]

[Problems to be solved by the device]

 In this conventional semiconductor integrated circuit, it was attempted to prevent the displacement of the metal wiring by distributing the thermal stress by using the four corners of the metal wiring provided on the outer periphery of the chip area. Only the durability of metal wiring against stress increased, and the countermeasures against the deviation of metal wiring were insufficient.

[0004]

[Means for Solving the Problems]

 The semiconductor integrated circuit according to the present invention comprises an interlayer insulation film formed in a region including a periphery of a chip area on a semiconductor substrate, and an interlayer insulation layer formed in an outer periphery of the chip area at least at four corners of the interlayer insulation layer. The semiconductor device has a groove formed in the film, and a metal wiring having a bottom surface partially embedded in the groove and provided on the outer periphery of the chip region.

[0005]

【Example】

 Next, the present invention will be described with reference to the drawings.

1A and 1B are a plan view and an enlarged cross-sectional view taken along the line A-A ′ showing an embodiment of the present invention.

As shown in FIGS. 1A and 1B, an interlayer insulating film 3 is provided on an insulating film 2 provided on a semiconductor substrate 1, and a chip region 5 around which a device region is formed is provided. At least four corners of the metal wiring formation region to be formed are selectively etched to form a groove 6 parallel to the metal wiring. Next, an aluminum layer is deposited on the surface including the groove 6 and patterned to form a metal wiring 4 having a part of the bottom surface buried in the groove 6 around the chip region 5.

[0008] By disposing the four corners of the metal wiring 4, the dispersion of thermal stress is enhanced, and the effect of preventing misalignment is increased.

[0009]

[Effect of the device]

 As described above, according to the present invention, by providing a groove in the inter-layer insulating film immediately below the metal wiring provided around the chip area, a part of the bottom surface of the metal wiring can be embedded and fixed in the premises, and the thermal stress This has the effect of preventing the displacement of the metal wiring.

[Brief description of drawings]

FIG. 1 is a plan view showing an embodiment of the present invention and an enlarged sectional view taken along the line AA ′.

FIG. 2 is a plan view showing an example of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 1 semiconductor substrate 2 insulating film 3 interlayer insulating film 4 metal wiring 5 chip area 6 groove

Claims (1)

[Scope of utility model registration request] 1. An interlayer insulation film provided in a region including an outer periphery of a chip region on a semiconductor substrate and an interlayer insulation film provided at least at four corners of a metal wiring formation region formed on the outer periphery of the chip region. A semiconductor integrated circuit comprising: a groove; and a metal wire having a bottom surface partially embedded in the groove and provided on an outer periphery of the chip region.