JPH05130169A - Digital data transmission line selection system - Google Patents

Abstract

PURPOSE:To provide the digital data transmission line selection system in which a clock signal is supplied continuously and reception data are not affected by a fault of other transmission line when any transmission line is faulty. CONSTITUTION:The system is provided with plural integrators 4,5 integrating clock signals of clock lines a', b' of transmission lines A, B respectively, plural level discrimination circuits 6, 7 detecting whether or not the output of the integrators 4, 5 is a prescribed value or over and outputting a 1-level fault signal when the output is the prescribed value or over, and selection circuits 8,9 receiving the 1-level fault signal and inhibiting the output of the data line and the clock line of the relevant transmission lines A, B.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital data transmission line selection system in a data bus system for serial digital data transmission.

[0002]

2. Description of the Related Art Conventionally, in a data bus system for individually transmitting digital data and a clock signal, when a bus line has a redundant configuration, a receiver 1 as shown in FIG.
On the 01 side, the received signals of the bus A system and the bus B system are set to O
Received by the data processing circuit 103 via the R gate 102,
In addition, it is general that the transmitter 110 side actively outputs a signal in only one of the systems.

[0003]

In the data bus system, the failure modes of the bus line include short circuit to the "0" level side, short circuit to the "1" level side and phase shift. However, in the conventional method, although there is no problem in the above-mentioned mode, the output of the receiving unit is always at the "1" level in the mode of, and the data latch timing changes in the mode of, and in any case, the received data is transmitted to other transmission lines. It becomes abnormal under the influence of the failure.

It is an object of the present invention that, in the case of a transmission line failure, the received data is not affected by the failure of another transmission line,
Another object of the present invention is to provide a digital data transmission line selection method capable of continuously supplying a clock signal even if any transmission line fails.

[0005]

According to the present invention, in the digital transmission line selection system having a plurality of transmission lines each including a data line for transmitting digital data and a clock line for transmitting a clock signal, each transmission line is provided. A plurality of integrators for respectively integrating the clock signals of the clock lines, and whether or not the outputs of these integrators are equal to or more than a predetermined value are detected, and a one-level failure signal is output when the output is equal to or more than the predetermined value. Digital data transmission line selection, comprising a plurality of failure determination means and output prohibition means for receiving the one-level failure signal and inhibiting output of the data line and clock line of the corresponding transmission line. The scheme is obtained.

Further, according to the present invention, in the digital transmission line selection system having a plurality of transmission lines each including a data line for transmitting digital data and a clock line for transmitting a clock signal, the data line of each transmission line is selected. A synchronization determination means that detects the header of digital data and determines whether or not it matches a predetermined header, outputs a LOCK-ON signal when they match, and outputs a LOCK-OFF signal when they do not match. When,
A digital data transmission line selection system is provided, which comprises a selection means for receiving the LOCK-OFF signal and validating the outputs of transmission lines other than the corresponding transmission line.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. Reference numeral 1 indicates a receiving device connected to the data bus system. The receiving device 1 includes a plurality of transmission lines A and B (hereinafter referred to as A system) which are composed of data lines a and b lines (hereinafter referred to as management buses a and b) for transmitting serial digital data and clock lines a'and b '. , B system). In the management buses a and b, a data block composed of a plurality of bits called a frame is serially digitally transmitted, and a header for achieving synchronization is added to the head of the frame. Clock line a ',
The clock signal transmitted by b'is a signal having a duty of 50% which is synchronized with the data on the management buses a and b in order to correctly latch the data on the management buses a and b.

The data of a and b of the management bus are input to the frame synchronizing circuits 2 and 3 together with the clock signal.
The frame synchronization circuits 2 and 3 sense a header from the bit strings of the data on the management buses a and b, and compare with a prescribed header to output a LOCK-ON signal until the next frame when they match. If they do not match, a LOCK-OFF signal (negative logic signal of LOCK-ON signal) is output.

On the other hand, the clock signals on the clock lines a'and b'are also input to the integrators 4 and 5. These integrators 4 and 5 output the averaging level of the clock signal. Since the clock signal is a logic signal having a duty of 50% as described above, its averaging level becomes 1/2 of the input level to the integrators 4 and 5, and the clock signal is disconnected, that is, "1" level, "0" level failure. If so, the averaging level changes and it is possible to determine the presence or absence of a failure. When the "0" level failure occurs, the frame synchronization circuits 2 and 3 also become LOCK-OFF and do not affect other devices. Therefore, only when the "1" level failure occurs, a countermeasure should be taken. Therefore, the outputs of the integrators 4 and 5 are input to the level judgment circuits 6 and 7, and in the level judgment circuits 6 and 7,
For example, if the input level of the clock signal to the integrators 4 and 5 is ⅔ or more of the normal level, it is determined to be "1" level failure, and the level error flag is set to "1" level at this time to output the level error signal.

The above frame synchronization circuits 2 and 3, the integrators 4 and 5, and the level determination circuits 6 and 7 are provided independently for each of the A system and the B system. LOCK of B-system frame synchronization circuit 3
The -OFF signal and the level error signal of the A system level determination circuit 7 are input to the A system selection circuit 8. The LOCK-OFF signal of the A-system frame synchronization circuit 2 and the level error signal of the B-system level determination circuit 6 are input to the B-system selection circuit 9.

The selection circuits 8 and 9 have no level error signal of their own system, and the frame synchronization of other systems is LOCK-OF.
Only when F, OR the data and clock signal of the management bus
It outputs through to the gates 10 and 11. OR gate 1
0, 11, 12 OR the data of the management bus, the clock signal, and the LOCK-ON signals of the A system and the B system, respectively, and output them to the data processing circuit 13.

Next, the operation of the present invention will be described.

In the transmitter, the clock signal is A
A clock signal is always output to each of the A and B systems, and a frame synchronization header is always output to either the A system or the B system on the management bus. Only when control or a message to the receiving side is necessary, Output data following the header.
However, during non-steady operation such as when the system is started up or when an error is taken, both systems may not output signals to the management bus, but neither system outputs the header.

Assuming that the A-system is operating now, on the receiving side, the A-system frame synchronization circuit 3 is at L level.
It becomes OCK-ON, and the B system becomes LOCK-OFF.
Further, the level judgment circuits 6 and 7 do not output the level error signal. Therefore, the A-system selection circuit 8 is the B-system LOCK-O.
Upon receiving the FF signal, the data of the management bus of the A system and the clock signal are output through, and the B system selection circuit 9 outputs the A system LOCK-.
Upon receiving the ON signal, the output is prohibited, and as a result, the OR gates 10 and 11 output the A-system signal to the data processing circuit 13. That is, the data and clock signal of the management bus of the system that is LOCK-ON is automatically selected.

Considering the case where the A system clock line a'has failed, when there is a "1" level short circuit failure, A
A level error signal is output from the system level determination circuit 6 to prohibit the output of the data and clock signal of the A system management bus, and as a result, the data and clock signal of the B system management bus are automatically selected. When the "0" level short-circuit failure of the A system, the selection circuits 8 and 9 both become through, but since it is at the "0" level, the OR does not affect the clock signals of other systems, and as a result, It is equivalent to selecting the B system. Therefore, in any of the failure modes, the B system is selected, the influence of the failure is automatically avoided, and the clock signal supplied to the data processing circuit 13 does not become discontinuous even when there is a failure.

For a "1" or "0" level short-circuit failure of the A-system management bus a and a phase shift failure between the data and the clock signal of the management bus, the A-system frame synchronization circuit 2 is set to LOCK-OFF. Therefore, the selection circuits 8 and 9 are both through, but the clock signal is normally processed by the data processing circuit 1.
3 is output. Although the data on the management bus is not normal data, both outputs are locked in the data processing circuit 13 by using the output obtained by ORing the LOCK-ON signals of the A and B systems.
It is possible to avoid malfunction by prohibiting the processing when OFF.

In any of the above failure modes of the A system, the receiving device 1 switches to the B system and stands by, so it is detected that the control or message output from the transmitting side is not normally processed by the receiving side. The transmission side can be restored by switching to the operation of the B-system management bus, and the output of the data and clock signal of the A-system management bus is prohibited so that the transmission to the B-system is eliminated. B as above
In any failure mode of the system, the receiving device 1 switches to the A system and stands by.

Although various methods are conceivable for detecting the processing status of the receiving side, a response bus is provided as an example, and the processing status of the receiving side is sent to the transmitting side via the response bus for each frame of the management bus. A method of replying can be considered.

[0020]

According to the digital data transmission line selection method of the present invention, when the transmission line fails, the received data is not affected by the failure of another transmission line, and even if one of the transmission lines fails. The clock signal can be supplied continuously.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Receiver 2,3 Frame synchronization circuit 4,5 Integrator 6,7 Level determination circuit 8 A system selection circuit 9 B system selection circuit 10, 11, 12 OR gate 13 Data processing circuit

Claims (2)

[Claims] 1. A digital transmission line selection system having a plurality of transmission lines each comprising a data line for transmitting digital data and a clock line for transmitting a clock signal, wherein the clock signals of the clock lines in the respective transmission lines are respectively integrated. A plurality of integrating means, a plurality of failure determining means for detecting whether the outputs of these integrating means are equal to or more than a predetermined value and outputting a one-level failure signal when the output is more than the predetermined value; A digital data transmission line selection method, comprising: an output inhibiting means for receiving a failure signal and inhibiting the output of the data line and the clock line of the corresponding transmission line. 2. A digital transmission line selection system having a plurality of transmission lines consisting of a data line for transmitting digital data and a clock line for transmitting a clock signal, wherein a header of digital data in the data line of each transmission line. Is detected, it is determined whether or not it matches a predetermined header, and if they match, a LOCK-ON signal is output,
And a synchronization determining means for outputting a LOCK-OFF signal when they do not match, and a selecting means for receiving the LOCK-OFF signal and validating the output of a transmission line other than the corresponding transmission line. Characteristic digital data transmission line selection method.